Patent Application
20090014887
The present invention relates to a method of producing a multilayer interconnection structure having groove wiring and a method of producing such a multilayer interconnection structure.
Recent super LSI devices require integration of more than several millions of elements within a several-millimeter square chip. It is therefore imperative for these devices to miniaturize and form the elements in a multilayer structure. It is particularly important for increasing the device operation speed to reduce the wiring resistance and interlayer capacitance.
In order to decrease the wiring resistance and interlayer capacitance, it is a common practice to use a film having a lower dielectric constant than a silicon oxide film as an interlayer insulating film while using copper as a wiring material. A Dual Damascene method is also used to decrease the wiring resistance. Using the Dual Damascene method, the number of processes including those for burying copper and those for mechanically and chemically polishing copper can be reduced substantially in comparison with a Single Damascene method. Further, the absence of a barrier film on the top of a via makes it possible to decrease the via resistance.
Thus, a via first process is characterized in that the number of exposures to oxygen plasma is great and a structure obtained by the process has a thick oxide layer.
According to the via first process described above, ashing is performed twice in the state in which an interlayer film is exposed. As a result, if a so-called low dielectric constant film having a dielectric constant lower than a silicon oxide film is used as a wiring interlayer film, the amount of carbon contained in the low dielectric constant film is reduced and hence the relative dielectric constant is increased (ashing damage). Further, if ashing is performed in the state in which misalignment has occurred during exposure of a wiring groove pattern, the low dielectric constant film will undergo more serious damages.
It is therefore an object of the present invention to provide a method of producing a multilayer interconnection having a low dielectric constant film used as a wiring interlayer film, in which ashing damage is reduced between wiring layers, and to provide multilayer interconnection having high reliability, reduced increase in the relative dielectric constant of a groove insulating film, and improved adhesion between a via insulating film and a barrier film.
The present invention provides a production method capable of etching a low dielectric constant film with less damage in Dual Damascene interconnection using a SiOCH low dielectric constant insulating film, and also provides a multilayer interconnection structure obtained by this method.
More specifically, the present invention provides a method of producing multilayer interconnection which includes stacking, on an underlayer wiring, a barrier insulating film, a via interlayer insulating film, a wiring interlayer insulating film, and a hard mask film sequentially in this order, forming a via hole pattern in the insulating film structure, then forming a groove pattern in the hard mask film, and forming a groove in the insulating film structure using this groove pattern as a mask.
The hard mask film is formed using a material having resistance against oxygen ashing, and may be formed of two or more layers, for example, formed by using a silicon oxide film as a lower layer and a silicon nitride film as an upper layer so that the upper hard mask layer is thin. Further, a stacked film with a metallic material, such as titanium, tantalum, tungsten or aluminum, an alloy thereof, or a compound thereof, may be used as the hard mask. A porous film, for example, having a lower relative dielectric constant than a silicon oxide film is used as the via and the wiring interlayer film. The wiring interlayer film is characterized by being a single-layer low dielectric constant film, or a stacked film including at least one type of low dielectric constant film such as a stacked film of different types of low dielectric constant films. When two or more layers are stacked, in the wiring interlayer film an upper-layer low dielectric constant film has a lower carbon/silicon ratio than that of a lower-layer low dielectric constant film. In the hard mask, the lower-layer hard mask has resistance against ashing and contains at least one or several selected from among silicon, nitrogen, and carbon. Further, the upper-layer hard mask is not limited to an inorganic film but also may be of a metal such as titanium, tantalum, tungsten, or aluminum, or an alloy or a compound thereof.
As a result, provided is a multilayer interconnection structure in which a side wall of a wiring groove insulating film is oxidized less than the inside thereof, while a side wall of a wiring insulating film directly above a via is oxidized, and in which a side wall of a via hole insulating film is oxidized more than the inside thereof.
The present invention provides a method of production a multilayer interconnection having a low dielectric constant film used as a wiring interlayer film, in which ashing damage is reduced between wiring layers, and provides highly reliable multilayer interconnection in which the increase in relative dielectric constant of a groove insulating film is reduced and adhesion between a via insulating film and a barrier film is high.
a), (b), (c), and (d) are diagrams showing a production method of multilayer interconnection using a via first process, as an example of conventional Dual Damascene processing;
a), (b), (c), and (d) are diagrams showing a production method of multilayer interconnection using a via first process, as an example of the conventional Dual Damascene processing;
a), (b), (c), and (d) show a production method of multilayer interconnection according to a first exemplary embodiment of the present invention;
a), (b), (c), and (d) show the production method of multilayer interconnection according to the first exemplary embodiment of the present invention;
a), (b), (c), and (d) show the production method of multilayer interconnection according to the first exemplary embodiment of the present invention;
a), (b), and (c) show other examples to which the production method of multilayer interconnection according to the first exemplary embodiment of the present invention is applied;
a) and (b) show comparison between the first exemplary embodiment of the present invention and a conventional process;
a), (b), (c), and (d) show a production method of multilayer interconnection according to a second exemplary embodiment of the present invention;
a), (b), (c), and (d) show the production method of multilayer interconnection according to the second exemplary embodiment of the present invention;
a), (b), and (c) show the production method of multilayer interconnection according to the second exemplary embodiment of the present invention;
a), (b), and (c) show the production method of multilayer interconnection according to the second exemplary embodiment of the present invention;
a), (b), (c), and (d) show a production method of multilayer interconnection according to a third exemplary embodiment of the present invention;
a), (b), (c), and (d) show the production method of multilayer interconnection according to the third exemplary embodiment of the present invention;
a), (b), and (c) show the production method of multilayer interconnection according to the third exemplary embodiment of the present invention;
a) and (b) show other example of the production method of the multilayer interconnection according to the third exemplary embodiment of the present invention; and
Before describing exemplary embodiments of the present invention, production methods of multilayer interconnection and multilayer interconnection structures according to the prior art will be described in order to facilitate the understanding of the present invention.
The prior art includes a so-called via first process.
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A production method of multilayer interconnection according to the present invention will be described. In the production method of multilayer interconnection according to the present invention, an Aurora-ULK film produced by ASM which is a plasma CVD-SiOCH film is used as the via interlayer insulating film, and a MPS (Molecular Pore Stack) film which is a molecular pore film is used as the wiring interlayer insulating film. The MPS has a carbon/silicon ratio of 2.7, that is greater than 0.7 of the Aurora-ULK film. SiO2 is used as the first hard mask, and SiN is used as the second hard mask.
According to the production method of multilayer interconnection of the present invention, a via is previously formed, then an organic film and a resist film are formed, a trench resist pattern is formed, the trench resist pattern is transferred to the hard mask, and then a trench is formed by using the hard mask. This method is characterized in that oxidation progresses on the via hole side wall since it is subjected to ashing occurring twice, while the side wall of the wiring interlayer film is not damaged by ashing since the trench formation is performed with the use of the hard mask.
A highly selective processing technique is required to realize the production method of the present invention. An etching selection ratio of five or more can be obtained between a SiOCH low dielectric constant insulating film and a silicon oxide film by performing etching with the use of mixture gas plasma in which oxygen gas is added to 40% or more nitrogen gas and 40% or more fluorocarbon gas.
Further, a selection ratio of three or more can be obtained by performing etching with the use of mixture gas plasma in which 15% or more oxygen gas and 5% or more but less than 20% fluorocarbon gas are diluted with nitrogen, while using SiOCH low dielectric constant films having different carbon/silicon ratios for the via and the wiring interlayer insulating film. Specifically, the formation of a Dual Damascene structure without a stopper is made possible by using Aurora-ULK having a low carbon/silicon ratio between the via layers and using MPS having a high carbon/silicon ratio between the wiring layers.
Further, the use of the above-mentioned two different mixture gas plasma conditions in combination makes it possible to perform processing to realize a desirably shaped structure for a wiring interlayer film having a low dielectric constant film and porous low dielectric constant film stacked, even if no stopper is provided.
Using the present invention, the via insulating film is oxidized sufficiently and hence the adhesion between the barrier film and the side wall of the via interlayer insulating film can be enhanced. Further, as a result of the sufficient oxidation, leakage between the vias can be prevented and hence the reliability can be improved. Since the groove insulating film is not ashed, multilayer interconnection having a low dielectric constant can be formed.
According to the present invention, multilayer interconnection having a low dielectric constant film used as a wiring interlayer film can be formed such that the trench side wall is not damaged by ashing, the adhesion and the leakage of the via interlayer film can be suppressed. Thus, multilayer interconnection having a low effective relative dielectric constant and high via reliability can be provided.
Exemplary embodiments of the present invention will be described with reference to the drawings.
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Although the above description of this exemplary embodiment has been made using an Aurora-ULK film as the via interlayer film, the material of the via interlayer film is not limited to Aurora-ULK, but CVD-SiOCH films such as other Aurora series products produced by ASM Japan, Orion produced by Tricon, BD/BD II (Black Diamond/Black Diamond II) produced by Applied Materials, and Coral produced by Novellus, or SiOCH films formed by applying a material such as porous SiLK produced by Dow-Chemical or NCS produced by Catalysts and Chemicals may be used. Further, SiOCH films formed by plasma polymerization as described in Japanese Laid-Open Patent Publication No. 2004-047873 (Document 1) also may be used. Although the above description has been made using a MPS film as the wiring interlayer insulating film, the same materials as mentioned in the above can be used instead. When taking package resistance into consideration, it is preferable to select a material having a higher density for the via interlayer insulating film than a material for the wiring interlayer insulating film.
Although the above description of the exemplary embodiment has been made using a silicon carbon nitride film as the Cu cap film, any other material may be used without any specific restriction as long as the material has Cu barrier property and is able to ensure a necessary etching selection ratio with respect to the low dielectric constant film. For example, a silicon carbide film and a silicon nitride film may be used. Further, an organic film formed by a plasma polymerization method, or an organic film containing siloxane such as divinyl-siloxane benzocyclobuten (DVS-BCB) may be used. Although the description above has been made using a silicon oxide film as the etching stopper film, any other material may be used without any specific restriction as long as the material is able to ensure a necessary etching selection ratio with respect to the low dielectric constant film, and a low dielectric constant film having SiOCH composition may be may be used, for example. Although in the description above the combination of SiN/SiO2 is used as the hard mask, any other combination may be used without any specific restriction as long as it is able to ensure a necessary selection ratio. For example, combinations such as SiC/SiO2, SiCN/SiO2, SiO2/SiN, SiO2/SiC, and SiO2/SiCN, and other combinations that exhibit a high selection ratio with respect to a porous SiOCH film may be used. In addition, titanium, tantalum, tungsten, aluminum, or an alloy thereof, or an oxide or nitride thereof may be used for one or both of the hard masks. Further, a low dielectric constant film or a modified film thereof may be used as long as it has resistance against ashing.
Although the above-description of this exemplary embodiment has been made in terms of the method in which the via etching is conducted to about a half of the Aurora-ULK film, the via etching may be performed to remove the entire of the Aurora-ULK film as shown in
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c) shows an example in which a low dielectric constant film 221 is used as the Cu cap film. As described before, an organic film formed by a plasma polymerization method or an organic film containing siloxane, such as divinyl-siloxane benzocyclobuten (DVS-BCB), may be used.
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The second exemplary embodiment relates to formation of so-called stopperless Dual Damascene Cu interconnection in which a via and a trench are formed in an insulating film structure consisting of a silicon oxide film, MPS, and Aurora-ULK, and in which the stopperless Dual Damascene structure can be obtained without causing damages to the side walls of the MPS film in the trench portion by applying an organic material and resist after forming a via to reach halfway of the Aurora-ULK film, forming a trench resist pattern, and forming a groove by a silicon nitride film/silicon oxide film hard mask process. This production method will be specifically described below.
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Although the above description of this exemplary embodiment has been made using an Aurora-ULK film as the via interlayer film, the material of the via interlayer film is not limited to Aurora-ULK, but CVD-SiOCH films, such as other Aurora series products produced by ASM Japan, Orion produced by Tricon, BD/BD II (Black Diamond/Black Diamond II) produced by Applied Materials, and Coral produced by Novellus, or SiOCH films formed by applying porous SiLK produced by Dow-Chemical or NCS produced by Catalysts and Chemicals may be used. Further, SiOCH films formed by plasma polymerization as described in Document 1 also may be used. Although the above description has been made using a MPS film as the wiring interlayer insulating film, the same materials as mentioned in the above can be used instead. In order to ensure a necessary etching selection ratio and to form a desirable Dual Damascene structure, it is preferable to use a wiring interlayer insulating film having a higher carbon/silicon ratio than that of the via interlayer insulating film. When taking package resistance into consideration, it is preferable to select a material having a higher density for the via interlayer insulating film than a material for the wiring interlayer insulating film.
Although the above description of the exemplary embodiment has been made using a silicon carbon nitride film as the Cu cap film, any other material may be used without any specific restriction as long as the material has Cu barrier property and is able to ensure a necessary etching selection ratio with respect to the low dielectric constant film. For example, a silicon carbide film and a silicon nitride film may be used. Further, an organic film formed by a plasma polymerization method, or an organic film containing siloxane such as divinyl-siloxane benzocyclobuten (DVS-BCB), may be used. Although in the description above the combination of SiN/SiO2 is used as the hard mask, any other combination may be used without any specific restriction as long as it is able to ensure a necessary selection ratio. For example, combinations, such as SiC/SiO2, SiCN/SiO2, SiO2/SiN, SiO2/SiC, and SiO2/SiCN, and other combinations, that exhibit a high selection ratio with respect to a porous SiOCH film may be used. Further, titanium, tantalum, tungsten, aluminum, or an alloy thereof, or an oxide or nitride thereof may be used for one or both of the hard masks. Further, a low dielectric constant film or a modified film thereof may be used as long as it has resistance against ashing.
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The third exemplary embodiment relates to formation of Dual Damascene Cu interconnection having a so-called low dielectric constant film (low-k) hard mask/porous SiOCH/stopperless structure in which a via and a trench are formed in an insulating film structure composed of a silicon oxide film, rigid SiOCH, MPS, and Aurora-ULK, and in which the process is a via first process and a stopperless Dual Damascene structure can be obtained without damaging the side wall of the MPS film in the trench portion by applying an organic material and resist after forming a via to reach halfway of the Aurora-ULK film, forming a trench resist pattern, and forming a groove by a silicon nitride film/silicon oxide film hard mask process. Further, according to this exemplary embodiment, the dielectric constant of the hard mask can be decreased, and hence decrease of the effective dielectric constant can be expected.
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Although the above description of this exemplary embodiment has been made using an Aurora-ULK film as the via interlayer film, the material of the via interlayer film is not limited to Aurora-ULK, but CVD-SiOCH films, such as other Aurora series products produced by ASM Japan, Orion produced by Tricon, BD/BD II (Black Diamond/Black Diamond II) produced by Applied Materials, and Coral produced by Novellus, or SiOCH films formed by applying porous SiLK produced by Dow-Chemical or NCS produced by Catalysts and Chemicals, may be used.
Further, SiOCH films formed by plasma polymerization as described in Document 1 also may be used. Although the above description has been made using a MPS film as the wiring interlayer insulating film, the same materials as mentioned in the above can be used instead. In order to ensure a necessary etching selection ratio and to form a desirable Dual Damascene structure, it is preferable to use a wiring interlayer insulating film having a higher carbon/silicon ratio than that of the via interlayer insulating film. When taking package resistance into consideration, it is preferable to select a material having a higher density for the via interlayer insulating film than a material for the wiring interlayer insulating film. Further, although a rigid SiOCH film is used as the low-k hard mask in the above description, any of the low dielectric constant films as described above may be used without any restriction as long as it is a low-k film having resistance against CMP.
Although the above description of the exemplary embodiment has been made using a silicon carbon nitride film as the Cu cap film, any other material may be used without any specific restriction as long as the material has Cu barrier property and is able to ensure a necessary etching selection ratio with respect to a low dielectric constant film. For example, a silicon carbide film and a silicon nitride film may be used. Further, an organic film formed by a plasma polymerization method, or an organic film containing siloxane, such as divinyl-siloxane benzocyclobuten (DVS-BCB), may be used. Although in the description above the combination of SiN/SiO2 is used as the hard mask, any other combination may be used without any specific restriction as long as it is able to ensure a necessary selection ratio. For example, combinations such as SiC/SiO2, SiCN/SiO2, SiO2/SiN, SiO2/SiC, and SiO2/SiCN, and other combinations that exhibit a high selection ratio with respect to a porous SiOCH film may be used. Further, titanium, tantalum, tungsten, aluminum, or an alloy thereof, or an oxide or nitride thereof may be used for one or both of the hard masks. Further, a low dielectric constant film or a modified film thereof may be used as long as it has resistance against ashing.
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A silicon oxide film 605 having a W contact plug 604 is formed on the MOSFET 603, and a 30 nm thick silicon carbon nitride film 613 is formed on the silicon oxide film 605, as an etch stop film of a wiring groove corresponding to a first-layer copper wiring 606. A 110 nm thick MPS film 614 and a 30 nm thick BD film 615 as a hard mask thereof are formed on this silicon carbon nitride film. The first-layer copper wiring has a structure in which a wiring groove passing through a stacked insulating film consisting of the BD film 615, the MPS film 614 and the silicon carbon nitride film 613 is filled with a Cu film 617 covered with a barrier film 616 consisting of Ta (10 nm) and TaN (5 nm). This first Cu wiring layer 606 is connected to the W contact plug 604.
A 30 nm thick silicon carbon nitride film 613a is formed as a via etch-stop layer on the first Cu wiring layer 606. Further, a 130 nm thick Aurora-ULK film 614a is formed thereon. The Aurora-ULK film 614a may be flattened by CMP or the like. A 130 nm thick MPS film 614b and a 30 nm thick BD film 615b as a hard mask thereof are formed on the Aurora-ULK film 614a. This stacked insulating film is formed with a second Cu wiring 608 in which a wiring groove passing through the BD film 615b and the MPS film 614b is filled with a Cu film. A first Cu via plug 607 is formed to extend from the bottom of this second copper wiring 608, passing through the Aurora-ULK film 614a and the silicon carbon nitride film 613a, and is connected to the first Cu wiring layer 606. The side wall of the Aurora-ULK film 614a has an oxide layer 618b formed by two ashing steps, and the side wall of the MPS film 614b also has an oxide layer at its region aligned vertically with the via side walls. The presence of the oxide layer improves the adhesion with a barrier material and reduces the via leakage.
A third Cu wiring layer 610 and a Cu via plug 609 connecting the third and second layers also can be formed into the same structure as that of the second wiring layer 608 and the via plug 607, and multilayer interconnection can be obtained by stacking these structures.
As described above, the production methods of multilayer interconnection according to the present invention are applicable to production of semiconductor devices and interconnection them.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-001854 | Jan 2006 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2007/050365 | 1/5/2007 | WO | 00 | 7/7/2008 |
