Patent Application
20250183034
As modern integrated circuits shrink in size, the associated features shrink in size as well. Lithography is a mechanism by which a pattern on a mask is projected onto a substrate such as a semiconductor wafer. In areas such as semiconductor photolithography, it has become necessary to create images on the semiconductor wafer which incorporate minimum feature sizes under a resolution limit or critical dimension (CD). Semiconductor photolithography typically includes the steps of applying a coating of photoresist (also referred to as resist) on a top surface (e.g., a thin film stack) of a semiconductor wafer and exposing the photoresist to a pattern. The semiconductor wafer is then transferred to a developing chamber to remove the exposed resist, which is soluble to an aqueous developer solution. As a result, a patterned layer of photoresist exists on the top surface of the wafer.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, “around,” “about,” “approximately,” or “substantially” may generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around,” “about,” “approximately,” or “substantially” can be inferred if not expressly stated. One skilled in the art will realize, however, that the values or ranges recited throughout the description are merely examples, and may be reduced or varied with the down-scaling of the integrated circuits.
The advanced lithography process, method, and materials described in the current disclosure can be used in many applications, including fin-type field effect transistors (FinFETs). For example, the fins may be patterned to produce a relatively close spacing between features, for which the above disclosure is well suited. In addition, spacers used in forming fins of FinFETs can be processed according to the above disclosure.
As semiconductor devices continue to shrink, a pitch between elements is tightened. The tightened pitch with worse image log slope (ILS) causes a worse lithography performance and a worse profile of a photoresist. For a negative tone developed (NTD) resist, there is rare description about modifying a material for lithography performance and profile improvement like positive tone developed resist.
The present disclosure provides a method for smoothing a profile of a negative tone photoresist layer such that a lithography performance of the negative tone photoresist layer can be improved.
In some embodiments, the substrate 110 is a silicon substrate doped with a p-type dopant such as boron (for example a p-type substrate). Alternatively, the substrate 110 could be another suitable semiconductor material. For example, the substrate 110 may be a silicon substrate that is doped with an n-type dopant such as phosphorous or arsenic (an n-type substrate). The substrate 110 could include other elementary semiconductors such as germanium and diamond. The substrate 110 could optionally include a compound semiconductor and/or an alloy semiconductor. Further, the substrate 110 could include an epitaxial layer (epi layer), may be strained for performance enhancement, and may include a silicon-on-insulator (SOI) structure.
In some embodiments, the target layer 112 is substantially conductive or semi-conductive. The electrical resistance may be less than about 103 ohm-meter. In some embodiments, the target layer 112 contains metal, metal alloy, or metal nitride/sulfide/selenide/oxide/silicide with the formula MXa, where M is a metal, and X is N, S, Se, O, Si, and where “a” is in a range from about 0.4 to 2.5. For example, the target layer 112 may contain Ti, Al, Co, Ru, TiN, WN2, or TaN.
In some other embodiments, the target layer 112 contains a dielectric material with a dielectric constant in a range from about 1 to about 40. In some other embodiments, the target layer 112 contains Si, metal oxide, or metal nitride, where the formula is MXb, wherein M is a metal or Si, and X is N or O, and wherein “b” is in a range from about 0.4 to 2.5. For example, the target layer 112 may contain SiO2, silicon nitride, aluminum oxide, hafnium oxide, or lanthanum oxide.
A photoresist composition is applied on the target layer 112 to form a photoresist layer 114. The photoresist composition applied on the target layer 112 to form the photoresist layer 114 may be applied by spin coating process or deposition process. In some embodiments, the photoresist composition includes a solvent, a first polymer and a photo acid generator (PAG). For example, the first polymer of the photoresist composition may include a polymer backbone and one or more acid labile groups (ALGs) bonded to the polymer backbone. The PAG may release an acid by an exposure using a radiation of light. The acid released by the PAG will cleave the ALGs in a subsequent post exposure baking (PEB) process such that the first polymer becomes more hydrophilic (see carboxyl group (—COOH) in
Reference is made to
In some embodiments, after exposing the photoresist layer 114 to the actinic radiation 116, a post-exposure bake (PEB) process is performed to the photoresist layer 114 to intensify the chemical amplified reaction. As discussed above, the PEB process allow the acid released by the PAG to cleave the ALGs such that the first polymer of the photoresist layer 114 has a hydrophilic polarity (or has carboxyl group (—COOH)).
The photoresist layer 114 is subsequently developed using a developer such as a solvent-based solution which is a negative tone developer (NTD), such as n-butyl acetate (nBA). An unexposed region of the photoresist layer 114 may be removed by a developer while an exposed region of the photoresist layer 114 remains. The resulting structure is shown in
Reference is made to
For example, the cyclic monomer 122 with the 3D cyclic structure may be represented by one of formulae (4) to (6):
In some embodiments, the linker moiety 124 includes hydrocarbons with carbon atoms of 1 to 3, COOH, the like, or a combination thereof. Reference is made to
In some embodiments, the solvent of the hydrophobic material 118 has a cLogP greater than or equal to a cLogP of the butyl acetate, which is about 1.8. That is, the solvent is more hydrophobic than the developer in some embodiments. The cLogP is a logP value of a compound, which is the logarithm of its partition coefficient between n-octanol and water log (Coctanol/Cwater), is a measure of the compound's hydrophilicity. In some embodiments, the solvent has the cLogP in a range from about 1.8 to about 10. If the cLogP of the solvent is less than about 1.8, the solvent might not be easily dissolved by the butyl acetate, which may be used to remove the hydrophobic material 118 in a subsequent process. In some embodiments, the solvent of the hydrophobic material 118 is butyl acetate, a hydrophobic solvent, the like, or a combination thereof.
Since the plasticizer is configured to adjust the glass transition temperature of the hydrophobic material 118, the plasticizer has a low molecular weight. In some embodiments, the plasticizer is a polymer having a molecular weight lower than a molecular weight of the second polymer. In some embodiments, the plasticizer is a small molecule including a rotatable moiety such as a long chain of carbon atoms, a C—O bond, a C═O bond, a C═N bond, the like, or a combination thereof at a backbone of the molecule, a side chain of the molecule, or as an end group of the molecule.
Reference is made to
Reference is made to
Reference is made to
Reference is made to
The photoresist layer 45 is removed after etching the substrate 44 by using a suitable photoresist stripper solvent or by a photoresist ashing operation. Isolation regions such as shallow trench isolation (STI) regions 56 may be formed on the substrate 44, filling into the trenches 54. The resulting structure in shown in
The STI regions 56 may include a liner oxide (not shown). The liner oxide may be formed of a thermal oxide formed through a thermal oxidation of a surface layer of the substrate 44. The liner oxide may also be a deposited silicon oxide layer formed using, for example, Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). The STI regions 56 may also include a dielectric material over the liner oxide, and the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, or the like.
Referring to
Referring to
The dummy gate dielectric 60 may further include an interfacial layer (not shown) including silicon oxide. The dummy gate electrode 62 may be formed, for example, using polysilicon, and other materials may also be used. The dummy gate electrode 62 may be made of other materials that have a high etching selectivity from the etching of STI regions 56. The dummy gate stack 58 may also include hard mask layers 64a and 64b over the dummy gate electrode 62. The hard mask layers 64a and 64b may be formed of silicon nitride and silicon oxide, respectively. The dummy gate stack 58 may cross over a single one or a plurality of protruding fins 104 and/or STI regions 56. The dummy gate stack 58 also has a lengthwise direction perpendicular to the lengthwise directions of protruding fins 104.
A photoresist layer 66 is formed over the dummy gate stack 58. In some embodiments, a pad layer (not shown) and a hard mask layer (not shown) may be formed between the photoresist layer 66 and the dummy gate stack 58. The pad layer and the hard mask layer have an etch selectivity with respect to the photoresist layer 66. The pad layer may be a silicon oxide layer and the hard mask layer may be a silicon nitride layer, for example. The above discussion of the operation to treating the photoresist layer 114 applies to the photoresist layer 66, unless mentioned otherwise. Therefore, the photoresist layer 66 can have a smooth profile. A lithography performance of the photoresist layer 66 is thus improved.
In
Next, as illustrated in
In
The source/drain regions of the fins 104 can be recessed using suitable selective etching processing that attacks the fins 104, but hardly attacks the gate spacers 72 and the hard mask layer 64b of the dummy gate stack 58. For example, recessing the fins 104 may be performed by a dry chemical etch with a plasma source and an etchant gas. The plasma source may be inductively coupled plasma (ICR) etch, transformer coupled plasma (TCP) etch, electron cyclotron resonance (ECR) etch, reactive ion etch (RIE), or the like and the etchant gas may be fluorine, chlorine, bromine, combinations thereof, or the like, which etches the protruding fins 104 at a faster etch rate than it etches the gate spacers 72 and the hard mask layer 64b of the dummy gate stack 58. In some other embodiments, recessing the protruding fins 104 may be performed by a wet chemical etch, such as ammonium peroxide (APM), NH4OH, tetramethylammonium hydroxide (TMAH), combinations thereof, or the like, which etches the fins 104 at a faster etch rate than it etches the gate spacers 72 and the hard mask layer 64b of the dummy gate stack 58. In some other embodiments, recessing the protruding fins 104 may be performed by a combination of a dry chemical etch and a wet chemical etch.
Once recesses are created in the source/drain regions of the fins 104, source/drain epitaxial structures 74 are formed in the source/drain recesses in the fins 104 by using one or more epitaxy or epitaxial (epi) processes that provides one or more epitaxial materials on the protruding fins 104. During the epitaxial growth process, the gate spacers 72 limit the one or more epitaxial materials to source/drain regions in the fins 104. In some embodiments, the lattice constants of the source/drain epitaxial structures 74 are different from the lattice constant of the fins 104, so that the channel region in the fins 104 and between the source/drain epitaxial structures 74 can be strained or stressed by the source/drain epitaxial structures 74 to improve carrier mobility of the semiconductor device and enhance the device performance. The epitaxy processes include CVD deposition techniques (e.g., PECVD, vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the fins 104.
In some embodiments, the source/drain epitaxial structures 74 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The source/drain epitaxial structures 74 may be in-situ doped during the epitaxial process by introducing doping species including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the source/drain epitaxial structures 74 are not in-situ doped, an implantation process (i.e., a junction implant process) is performed to dope the source/drain epitaxial structures 74. In some exemplary embodiments, the source/drain epitaxial structures 74 in an n-type transistor include SiP, while those in a p-type include GeSnB and/or SiGeSnB. In embodiments with different device types, a mask, such as a photoresist, may be formed over n-type device regions, while exposing p-type device regions, and p-type epitaxial structures may be formed on the exposed fins 104 in the p-type device regions. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type device region while exposing the n-type device regions, and n-type epitaxial structures may be formed on the exposed fins 104 in the n-type device region. The mask may then be removed.
Once the source/drain epitaxial structures 74 are formed, an annealing process can be performed to activate the p-type dopants or n-type dopants in the source/drain epitaxial structures 74. The annealing process may be, for example, a rapid thermal anneal (RTA), a laser anneal, a millisecond thermal annealing (MSA) process or the like.
Next, in
In some examples, after forming the ILD layer 78, a planarization process may be performed to remove excessive materials of the ILD layer 78 and the CESL 76. For example, a planarization process includes a chemical mechanical planarization (CMP) process which removes portions of the ILD layer 78 and the CESL 76 overlying the dummy gate stack 58. In some embodiments, the CMP process also removes hard mask layers 64a and 64b (as shown in
An etching process is performed to remove the dummy gate electrode 62 and the dummy gate dielectric 60, resulting in gate trenches between corresponding gate spacers 72. The dummy gate stack 58 are removed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof) that etches materials in the dummy gate stack 58 at a faster etch rate than it etches other materials (e.g., gate spacers 72 and/or the ILD layer 78).
Thereafter, replacement gate structures 80 are respectively formed in the gate trenches. The gate structures 80 may be the final gates of FinFETs. In FinFETs, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. The final gate structures each may be a high-k/metal gate (HKMG) stack, however other compositions are possible. In some embodiments, each of the gate structures 80 forms the gate associated with the three-sides of the channel region provided by the fin 104. Stated another way, each of the gate structures 80 wraps around the fin 104 on three sides. In various embodiments, the high-k/metal gate structure 80 includes a gate dielectric layer 82 lining the gate trench, a work function metal layer 84 formed over the gate dielectric layer 82, and a fill metal 86 formed over the work function metal layer 84 and filling a remainder of gate trenches. The gate dielectric layer 82 includes an interfacial layer (e.g., silicon oxide layer) and a high-k gate dielectric layer over the interfacial layer. High-k gate dielectrics, as used and described herein, include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The work function metal layer 84 and/or the fill metal 86 used within high-k/metal gate structures 80 may include a metal, metal alloy, or metal silicide. Formation of the high-k/metal gate structures 80 may include multiple deposition processes to form various gate materials, one or more liner layers, and one or more CMP processes to remove excessive gate materials.
In some embodiments, the interfacial layer of the gate dielectric layer 82 may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. The high-k dielectric layer of the gate dielectric layer 82 may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer 82 may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitrides (SiON), and combinations thereof.
The work function metal layer 84 may include work function metals to provide a suitable work function for the high-k/metal gate structures 80. For an n-type FinFET, the work function metal layer 84 may include one or more n-type work function metals (N-metal). The n-type work function metals may exemplarily include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAIN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AIC)), aluminides, and/or other suitable materials. On the other hand, for a p-type FinFET, the work function metal layer 84 may include one or more p-type work function metals (P-metal). The p-type work function metals may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials.
In some embodiments, the fill metal 86 may exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSIN, TaCN, TiAl, TiAIN, or other suitable materials.
In some embodiments, the semiconductor device 42 includes other layers or features not specifically illustrated. In some embodiments, back end of line (BEOL) processes are performed on the semiconductor device 42. In some embodiments, the semiconductor device 42 is formed by a non-replacement metal gate process or a gate-first process.
Based on the above discussions, it can be seen that the present disclosure offers advantages over conventional methods. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that by forming a hydrophobic material on the photoresist layer to surround the photoresist layer followed by performing a reflow process to the photoresist layer and the hydrophobic material, the hydrophobic material can act as a wall for the photoresist layer during the reflow process such that the photoresist can have a smooth profile. Another advantage is that after performing the reflow process, the hydrophobic material can be easily removed such as using a developer.
In some embodiments, a lithography method includes the following steps. A target layer is formed over a substrate. A photoresist composition is applied over the target layer to form a photoresist layer. The photoresist layer is exposed. A hydrophobic material is formed over the photoresist layer. A reflow process is performed to the photoresist layer and the hydrophobic material. The hydrophobic material is removed. The target layer is patterned using the photoresist layer as an etch mask. In some embodiments, the hydrophobic material has a glass transition temperature greater than a glass transition temperature of the photoresist layer. In some embodiments, the hydrophobic material is made of a polymer, a plasticizer and a solvent. In some embodiments, the polymer is an acrylate-based polymer or a methyl methacrylate-based polymer. In some embodiments, the polymer of the hydrophobic material comprises a backbone, a linker moiety and a cyclic monomer bonded to the backbone through the linker moiety. In some embodiments, the cyclic monomer is represented by formulae (1) to (6):
In some embodiments, the plasticizer includes a C—O bond, a C═O bond, a C═N bond, or a combination thereof. In some embodiments, the plasticizer has a molecular weight lower than a molecular weight of the polymer. In some embodiments, the solvent is butyl acetate. In some embodiments, the method comprises after exposing the photoresist layer, developing the photoresist layer using the developer, and the solvent has a cLogP greater than or equal to about 1.8, and the solvent is more hydrophobic than the developer. In some embodiments, the polymer has a glass transition temperature greater than about 130° C. In some embodiments, the polymer has a molecular weight greater than about 8000.
In some embodiments, a lithography method includes the following steps. A target layer is formed over a substrate. A photoresist pattern is formed over the target layer. Opposite sidewalls and a top surface of the photoresist pattern are covered with a hydrophobic material, wherein the photoresist pattern is more hydrophilic than the hydrophobic material. The photoresist pattern and the hydrophobic material are heated. The hydrophobic material is removed to expose the photoresist pattern. The target layer is etched using the photoresist pattern as an etch mask. In some embodiments, removing the hydrophobic material to expose the photoresist pattern is performed using a first developer. In some embodiments, the first developer is butyl acetate. In some embodiments, wherein forming the photoresist pattern over the target layer comprises the following steps. A photoresist composition is applied on the target layer to form a photoresist layer. The photoresist layer is exposed using a radiation of light. The photoresist layer is developed using a second developer, wherein the first developer and the second developer include the same composition.
In some embodiments, a hydrophobic material comprises a solvent, a polymer dissolved in the solvent and a plasticizer dissolved in the solvent. In some embodiments, the polymer comprises a backbone, a cyclic monomer connected to the backbone and represented by formulae (1) to (6):
In some embodiments, the polymer further comprises a linker moiety connected between the backbone and the cyclic monomer, the linker moiety comprising hydrocarbons with carbon atoms of 1 to 3 or COOH. In some embodiments, the polymer has a glass transition temperature greater than about 130° C. In some embodiments, the polymer is acrylate-based polymer or a methyl methacrylate-based polymer.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
