Patent Application
20130277828
Integrated circuits or chips are made up of millions of active and passive devices such as transistors and capacitors. These devices are initially isolated from each other, and are later interconnected to form integrated circuits. Connector structures are further formed for integrated circuits, which may include bond pads or metal bumps formed on the surface of the circuits. Electrical connections are made through the bond pads or metal bumps to connect the chip to a package substrate or another die. In general, chips may be assembled into a package such as a pin grid array (PGA), or ball grid array (BGA), using wire bonding (WB) or flip chip (FC) packaging technology.
A flip-chip (FC) packaging technology may connect a chip to a package substrate using a bump-on-trace (BOT) structure, wherein the connections are made through the metal bumps to connect the chip to the metal traces of the package substrate or die. The BoT structure offers a low cost alternative to microelectronic packaging industry. However, the reliability issues for BOT structure rises as substrate structure goes thinner.
When using a BoT structure, bumps for the chip are soldered onto the trace on the package substrate by a reflow process. When the bumps are joined to the substrate and cooled down from the reflow condition to a room temperature, thermal force caused by coefficient of thermal expansion (CTE) mismatch drives the substrate shrinkage and leads to relative twist on each bump. Once stress level rises over the adhesive criteria between the substrate and the trace, a trace peeling failure occurs.
For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:
a)-(c) illustrate an embodiment of a method and an apparatus of a solder mask trench used in a BOT structure to form a FC package; and
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the disclosure, are simplified for explanatory purposes, and are not drawn to scale.
The making and using of the embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the embodiments of the present disclosure provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.
As will be illustrated in the following, methods and apparatus for a solder mask trench used in a BOT structure to form a semiconductor package are disclosed. A solder mask layer is formed on a trace and on a substrate. An opening of the solder mask layer, called a solder mask trench, is formed to expose the trace on the substrate. A chip is connected to the trace exposed in the solder mask trench. With the formation of the solder mask trench, the trace exposed in the trench can have a better grab force, which reduces the trace peeling failure for the semiconductor package.
a) illustrates an embodiment of a single solder mask trench 210 on a substrate 206, which may be any of the trenches in
b) illustrates the top view where a post 202 is on the trace 204, which is surrounded by the solder mask 211. The chip 201 and the substrate 206 are not shown in
c) illustrates an exemplary process of manufacturing the embodiment shown in
The process starts at step 220, where a substrate such as the substrate 206 in
A trace 204 may be on the surface of the substrate 206. The trace 204 may be for expanding the footprint of a die. The width or diameter of the trace may be about the same as the ball (or bump) diameter, or can be as much as two to four times narrower than the ball (or bump) diameter. For example, the trace 204 may have a line width between about 10 μm and 40 μm and trace pitch P between about 30 μm and 70 μm. The trace may have a narrow, wide, or tapered shape. The terminal of the trace may be of a different shape from the body of the trace. The trace body may be of a substantially constant thickness. The terminal of the trace and the body of the trace are formed as one piece, which is different from placing a pad on a trace. The trace may have a substantially longer length than the diameter of the ball (or bump) diameter. On the other hand, a connection pad may be of similar length or width as the ball or bump diameter.
There may be multiple traces on the substrate, each electrically insulated from one another, and the space between two adjacent traces may be between about 10 μm and 40 μm.
The trace 204 may comprise conductive materials such as Al, Cu, Au, alloys thereof, other materials, or combinations and/or multiple layers thereof, as examples. Alternatively, the trace 204 may comprise other materials. In some embodiments, a dielectric layer may cover some portions of the trace 204. The trace 204 may be covered by a metal finish, such as a layer of organic film or a mix material such as Ni/Pd/Au, coated on the trace 204.
The trace 204 and the substrate are connected by merely interfacial adhesion between them, which may not be enough grabbing force to make a strong connection between the trace 204 and the substrate 206.
At step 221, a solder mask layer such as the solder mask layer 211 shown in
The solder mask layer 211 may be formed at a single step, by screening a wet film onto the substrate surface and then curing the wet film by oven baking. The thickness of the solder mask layer 211 may be about 30 to 40 microns (typically about 35 microns). The solder mask layer may comprise polymer material.
At step 223, a trench may be opened in the solder mask layer 211 to form a solder mask trench 210 to expose the trace 204, as shown in
A solder flux (not shown) may be applied to the trace. The flux serves primarily to aid the flow of the solder, such that the solder balls 203 make good contact with traces on the substrate. It may be applied in any of a variety of methods, including brushing or spraying. The flux generally has an acidic component, which removes oxide barriers from the solder surfaces, and an adhesive quality, which helps to prevent the chip from moving on the substrate surface during the assembly process.
At step 227, a chip 201 may be connected to the trace 204 by way of an interconnect of the chip, as shown in
The solder bump 203 of a chip 201 may be placed on the trace 204 exposed by the solder mask trench. The solder bump 203 may comprise a material such as tin, or other suitable materials, such as silver, lead-free tin, copper, combinations thereof, or the like. In an embodiment in which the solder bump 203 is a tin solder bump, the solder bump 203 may be formed by initially forming a layer of tin through methods such as evaporation, electroplating, printing, solder transfer, or ball placement, to a thickness of, e.g., about 15 μm, and then performing a reflow in order to shape the material into the desired bump shape. Any suitable method of producing the solder bump 203 may alternatively be utilized.
A chip such as the chip 201 shown in
The post 202 and solder bump 203 together form an interconnect of the chip. The post 202 and solder bump 203 may be formed in a plurality of shapes as appropriate to avoid nearby components, control the connection area between the chip 201 and the trace 204, or other suitable reasons. The interconnect may be in the shape of a circle, an octagon, a rectangle, an elongated hexagon with two trapezoids on opposite ends of the elongated hexagon, an oval, a diamond.
At step 231, a reflow process is performed. After the chip 201 is bond to the trace as shown in
At step 233, an underfill material, typically a thermo-set epoxy, may be dispensed into the gap between the chip 201 and the substrate 206. Beads of thermo-set epoxy may be applied along one edge of the chip where the epoxy is drawn under the chip by capillary action until it completely fills the gap between the chip and the substrate. It is important that the underfill material is uniformly dispersed in the gap.
A separate bead of epoxy may also be dispensed and bonded around the perimeter of the chip 201. Afterwards, both the underfill and perimeter bonding epoxy are cured by heating the substrate and chip to an appropriate curing temperature, which form an encapsulation body such as the encapsulation body 205 shown in
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
