Patent Application
20050070120
1. Field of the Invention
The present invention relates generally to semiconductor devices. More particularly, it concerns formation of a thin insulator dielectric interface between high-k material and silicon on a semiconductor device.
2. Description ofRelated Art
As research and development of dielectric materials advances, especially materials where the dielectric constant, k, is greater than 3.9, an insulator dielectric interface layer between a high-k film and a silicon substrate has proven beneficial. For example, the insulator dielectric interface layer may improve device electrical characteristics including leaking current density, mobility, transconductance and the saturated current.
Previous technologies have focused on using a chemical oxide grown by an ozonated water rinse process or a standard RCA type clean to create an insulator dielectric interface layer to fabricate an oxide film. However, the resultant film is too thick, approximately 1.0 nm, for practical implementation and thus, does not permit device scaling below 1 nm. In addition, the oxide continues to grow if subsequent heat treatment cycles are applied
These shortcoming of conventional methods are not intended to be exhaustive, but rather are among many that tend to impair the effectiveness of previously known techniques concerning fabrication and scaling of a dielectric layer; however, those mentioned here are sufficient to demonstrate that methodology appearing in the art have not been altogether satisfactory and that a significant need exists for the techniques described and claimed in this disclosure.
A thin insulator dielectric interface made and used according to the present disclosure may be designed to overcome limitations discussed above because the overall thickness of the layer may be controlled by etch back using wet chemical or dry etch processes.
According to aspects of the invention, a method for fabricating a semiconductor device on a silicon substrate, comprises forming an oxide layer using an in situ steam generation process on the silicon substrate, etching the oxide layer to form a reduced thickness oxide layer of approximately less than 10 Angstroms, and annealing the reduced thickness oxide layer in the presence of ammonia.
According to another aspect of the invention, a method comprises: forming an oxide layer on a silicon substrate using an in situ steam generation process, etching the oxide layer to form a reduce thickness oxide layer of approximately less than 10 Angstroms, annealing the reduced thickness oxide layer, and depositing a high-k dielectric material on the reduced thickness oxide layer.
According to yet another aspect of the invention, a semiconductor wafer is disclosed. The semiconductor wafer includes a silicon substrate, an oxide layer coupled to the silicon substrate, where the oxide layer is formed from an in situ steam generation process and etched back to a thickness of approximately 10 Angstroms, and a high-k dielectric material deposited on the oxide layer.
Further, the invention includes a semiconductor wafer which includes a silicon substrate, an oxide layer coupled to the silicon substrate, where the oxide layer is formed from an in situ steam generation process and etched back to a thickness of approximately 4 Angstroms, and a high-k dielectric material deposited on the oxide layer.
These, and other, embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating various embodiments of the invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many substitutions, modifications, additions and/or rearrangements may be made within the scope of the invention without departing from the spirit thereof, and the invention includes all such substitutions, modifications, additions and/or rearrangements.
The drawings accompanying and forming part of this specification are included to depict certain aspects of the invention. A clearer conception of the invention, and of the components and operation of systems provided with the invention, will become more readily apparent by referring to the exemplary, and therefore nonlimiting, embodiments illustrated in the drawings, wherein like reference numerals (if they occur in more than one view) designate the same or similar elements. The invention may be better understood by reference to one or more of these drawings in combination with the description presented herein. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale.
The invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be understood that the detailed description and the specific examples, while indicating specific embodiments of the invention, are given by way of illustration only and not by way of limitation. Various substitutions, modifications, additions, and/or rearrangements within the spirit and/or scope of the underlying inventive concept will become apparent to those of ordinary skill in the art from this disclosure.
The invention sets forth methods and devices for a thick insulator dielectric at an interface and reducing the thickness by a controlled etch back. In particular, the invention is directed toward scaling down the equivalent oxide thickness and applying a NH3 anneal process prior to the deposition of a high-k dielectric film, in which k may be greater than 3.9. This prevents further oxide growth in subsequent fabrication steps and reduces the equivalent oxide thickness. The equivalent oxide thickness (“EOT”), as described herein, relates to the performance of a metal on silicon (MOS) gate dielectric, where the dielectric constant, k, is about 3.9, and where the MOS gate may include a high-k material. The treated oxide layer has been found to be beneficial in improving device electrical characteristics, including leakage current density, mobility, transconductance and saturated current, Idsat.
The formation of an oxide layer on a silicon substrate is well known in the art. The exposure of silicon to oxygen forms a silicon dioxide layer that becomes an electrical insulator as well as a barrier material during impurity depositions. For example, thermal oxidation is a method for growing an oxide layer, in which the wafer is heated to a high temperature ranging from 900° to 1200° C. in an atmosphere containing pure oxygen or water vapor. Another method of forming an oxide layer is during a wet cleaning and rinsing operation, known in the art as chemical oxide. During the cleaning of a wafer, a chemical oxide layer may be formed when a formula, such as the HF/HCl—O3/HCl sequence with ozonated water, is dispensed onto the wafer. Yet another method of forming an oxide layer is known as steam oxidation. Water vapors of deionized water produced by vaporization is directed towards a wafer, causing oxidation on the silicon substrate.
In accordance to embodiments of the invention, a chemical oxide layer may be formed on a silicon wafer using the HF/HCl—O3/HCl sequence with ozonated water. The HF/HCl etch process portions may follow and may include using a DI:HF:HCl process. Upon forming the oxide layer, an etching process may follow, where the etch time may be determined equivalent to the time needed to remove a certain amount of oxide. Following the etching process, the wafer may be subjected to an O3 and an HCl rinse. For example, a 200:1:0.4 DI:HF:HCl formula at approximately 23° C. may be used to form a oxide layer upon a silicon wafer. An etch time can be determined such that the removal approximately 200 Å of oxide may be completed. Once the etching process is complete, O3 is dispensed onto the wafer for a predetermined time, temperature, and concentration, for example, 10 min at 23° C. with an O3 concentration of 20 parts per million (“ppm”) and an HCl concentration of 0.2%. The wafer may subsequently transferred to a low particulate dryer, LPD, where the wafer receives a 3-minute deionized water (DI) rinse and a low pressure isopropyl alcohol/hot N2 dry.
Alternatively, in other embodiments, a chemical oxide layer is formed on a silicon wafer using an RCA-type cleaning method which may include a HF/HCl—SCl—SC2 sequence. The HF/HCl etch portion such as a 200:1:0.4 DI:HF:HCl formula at 23° C. may be dispensed and targeted to remove a thickness of the oxide. SC1 may be dispensed onto the wafer at a particular temperature and duration, e.g., 23° C. for 7 minutes, with a H2O:H2O2:NH4OH mixture with the ratio of 100:2:1, respectively. Finally, SC2 may be dispensed onto the wafer at a predetermined temperature and duration, e.g., 23° C. for 7 minutes with a H2O:H2O2:HCl mixture of 50:1:1, respectively. After the SC2 rinse, the wafers may be transferred to the LPD where they received a 3-minute DI water rinse and a low pressure isopropyl alcohol/hot N2 dry.
According to embodiments of the invention, an in situ steam generation (ISSG) oxide layer may be formed. A plurality of transistor wafers may first be cleaned using a sequence such as an HF/HCl—O3/HCl sequence with ozonated water dispensed onto the wafer. Referring to
The ISSG oxide may undergo an alternative etching process. After the rapid thermal processing, the wafers may be exposed to an anhydrous HF vapor process. The rinse-etch-rinse process using the anhydrous HF and water vapor targets to reduce the thickness of the oxide. Prior to the vapor etch, a 5-second water rinse may be employed to leave a uniform, adsorbed layer of moisture for better etch uniformity. After the vapor etch, a 7 second water rinse can be employed to remove the etch residues. Such a method may be directed to an oxide thickness of less than 4 Å, and preferably a wafer with approximately 3.7 Å partially hydrophobic, partially fluorine-terminated film on the silicon substrate 12.
For each embodiment described above, the wafers undergo an ammonia (NH3) anneal process at 700° C. and 30 Torr for 15 seconds prior to the deposition of a high-k material. The anneal process, in conjunction with the scaling of the oxide interfaces, achieves thinner EOTs with acceptable electrical performances. Referring to
Referring to
Subsequent fabrication steps known in the art are subsequently performed to form a transistor as shown, for example, in
The following example is included to demonstrate specific embodiments of this disclosure. Particularly, the examples below summarizes testing done to evaluate oxide interfaces created from various pre-gate wafer cleans and to determine the impact of subsequent NH3 pre-high-k dielectric film deposition anneals on electrical performances. It should be appreciated by those of skill in the art that the techniques disclosed in the examples that follow represent techniques discovered by the inventors to function well in the practice of the invention, and thus can be considered to constitute specific modes for its practice. However, those of skill in the art should, in light of the present disclosure, appreciate that many changes can be made in the specific embodiments which are disclosed and still obtain a like or similar result without departing from the spirit and scope of the invention.
The example illustrates five different interfaces such as chemical oxides and ISSG thermal oxides and the effects of the respective oxide layer on electrical properties of the devices. Particularly, the example illustrates that an ISSG interface is more robust than a chemical oxide of equivalent thickness. Further, the example illustrates the results of a monolayer of partially fluorine-terminated ISSG oxide remaining after the anhydrous HF process.
Column 1 of Table 1 and 2 below includes the type of chemicals or process steps that a wafer is subjected to. Each step is done for an approximate period of time in seconds. For example, a process step includes subjecting a wafer to de-ionized water (DIW). Similarly, DIW-1 is subjecting a wafer to a high-flow of de-ionized water. H-DIW is subjecting a wafer to hot de-ionized water. Other process steps include moistening or showering (SH) the wafer, a quick dump rinse (QDR), and a dip time (DIP). Chemical process includes subjecting the wafer to different compound including ozone (O3), ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), hydrofluoric acid (HF), hydrochloric acid at a low rate (HCl-1), and/or hydrochloric acid at a high rate (HCl-2).
Further, Table 1 and 2 also include the time interval where a wafer is subjected to a megasonic power source (DSM). In some embodiments, a wafer may be subjected to a power setting (DSM-PW) corresponding to a level (e.g., 1-7). Each level has a predetermined power level. For example a “6” may indicate a power source of approximately 420 MHz.
A. Oxide Formation
1. A Chemical Oxide Formed by an IMEC-Type Clean Using an HF/HCl—O3/HCl Sequence with an Ozonated Water Dispense
The recipe, shown in Table 1, was run as a baseline since it was known to be the best process at the time. The HF/HCl etch portion in Step 2 had used a 200:1:0.4 DI:HF:HCl formula at 23° C. and was targeted to remove 200 Å of thermal oxide. The O3 was dispensed for 10 min at 23° C. with an O3 concentration of 20 ppm and an HCl concentration of 0.2% as shown in Step 5 of Table 1. Further, the O3 was dispensed at a power setting of “6” which corresponds to a megasonic power of approximately 420 MHz. The wafers were then transferred to the LPD where they received a 3-minute DI water rinse and a low pressure IPA/hot N2 dry. The process designated “STD O3” in
2. A Chemical Oxide Formed by an RCA-Type Clean Using an HF/HCl—SCl—SC2 Sequence with a Reduced SC1 Process Temperature and SC1 Reduced Concentration to 100:2:1
The recipe, as shown in Table 2, includes an HF/HCl etch portion with a 200:1:0.4 DI:HF:HCl formula at 23° C. and was targeted to remove 200 Å of thermal oxide. The SC1 dispense used a 100:2:1 (H2O:H2O2:NH4OH) formula and was run at 23° for 7 minutes, as shown in Steps 2-3. The temperature of the 23° C. process was reached by dispensing room temperature water into the tank. The SC2 dispense used a 50:1:1 (H2O:H2O2:HCl) formula and was run at 23° C. for 7 minutes, as shown in Steps 8-9. After the post-SC2 rinse, the wafers were transferred to the LPD where they received a 3-minute DI water rinse and a low pressure IPA/hot N2 dry. The process is designated “SC1-23C” in
3. Two Different ISSG Oxide Interfaces were Created by Performing Controlled Etches of 21 Å ISSG Oxides Using an HF/HCl Process
The wafers were initially cleaned with the recipe as shown in of Table 1. Next, each wafer received a 21 Å ISSG process on a RTP, which consisted of a 16-second exposure to 4950 sccm of O2 and 50 sccm of H2 at 950° C. and 5.8 Torr. The wafers were then processed again through the DNS using the LPD-XHF process to reduce the oxide thickness from 21 A. The HF/HCl etch portion of the process used a 200:1:0.4 DI:HF:HCl formula at 23° C; the etch times were varied to target ˜10 Å of remaining ISSG for one split and ˜7 Å for another. However, the resultant thicknesses were approximately 9 Å and 8 Å, respectively. The processes are designated “ISSG—9 Å” and “ISSG—8 Å” in
4. An ISSG Oxide Interface Created by Performing an Over Etch of a 21 Å ISSG Oxide Using an Anhydrous HF Process
The wafers were initially cleaned with the recipe illustrated in Step 1 of Table 1. The HF/HCl etch portion in Step 2 had used a 200:1:0.4 DI:HF:HCl formula at 23° C. and was targeted to remove 200 Å of thermal oxide. The O3 was dispensed for 10 min at 23° C. with an O3 concentration of 20 ppm and an HCl concentration of 0.2% as shown in Step 5 of Table 1. Further, the O3 was dispensed at a power setting of “6” which corresponds to a megasonic power of approximately 420 MHz. The wafers were then transferred to the LPD where they received a 3-minute DI water rinse and a low pressure IPA/hot N2 dry. The process designated “STD 03” in
Each wafer subsequently received a 21 Å ISSG process on a RTP, which consisted of a 16-second exposure to 4950 sccm of O2 and 50 sccm of H2 at 950° C. and 5.8 Torr. The wafers were then processed through an anhydrous HF vapor process, as shown by the recipe shown in Table 3 which includes a rinse-etch-rinse process using anhydrous HF and water vapor targeted to remove 60 Å of thermal oxide. Before the vapor etch, a 5-second water rinse was employed to leave a uniform, adsorbed layer of moisture for better etch uniformity; after the vapor etch, a 7-second water rinse was employed to remove the etch residues. The clean left the wafer with a 3.7 Å (as measured using ellipsometry technique) partially hydrophobic, partially fluorine-terminated film on the wafer surface. This process is designated “ISSG—Anhy —NH3” in
Some wafers from the above oxide formations received an ammonia (NH3) anneal at 700° C. and 30 Torr for 15 seconds and some did not. The pre-treated wafers are designated “NH3-PreDA.” Those wafers that were not pre-treated are designated “—None.”
B. Semiconductor Wafer Preparation
The semiconductor wafers were staged immediately before pre-gate clean several weeks before their use. To ensure that queue time would not affect the results, all of the wafers underwent an SPM process before the actual pre-gate clean. The SPM was a 6:1 SPM:H2O2 process for 400 seconds at 130° C. followed by a series of dump-rinse cycles. The wafers were then transferred to the LPD where they received a 3-minute DI water rinse and a low pressure IPA/hot N2 dry.
After the interfaces were formed, ellipsometer (AE) measurements were performed on an Optiprobe. The measurements consisted of a reliable single-wavelength HeNe laser source, polarizer, rotating compensator, and detector.
Next, a high-k deposition process consisted of an HfSixOy film was deposited on all the wafers at 4 Torr, 485° C., and 45 Å. The wafers were then treated with a post high-k dielectric deposition. This was an NH3 anneal at 700° C. and 30 Torr for 60 seconds. The deposition and post-treatment were completed as part of a sequenced recipe on a RTP.
A 100 Å TiSiN film was deposited in a chemical vapor deposition (CVD) system at 60 mTorr and 350° C. The gases used NH3 and tetrakis (diethylamino) titanium (TDEAT). The deposition was followed immediately by a 10-second silane (SiH4) soak to improve the integrity of the barrier layer.
A subsequent 1800 Å amorphous-silicon deposition process was performed in the RTP. The a-Si was deposited at 120 Torr and 620° C. using SiH4 and H2 for 128 seconds. For control and monitoring purposes, two wafers cleaned with the standard O3 clean underwent the baseline ISSG process. These wafers are designated “ISSG” in the
C. Semiconductor Device Tests
1. Methodology
The wafers were automatically tested to collect electrical parameters. Many parameters were tested, but only those that had a high sensitivity to the effects of cleaning were selected such as transconductance, saturation current, threshold voltage, and leakage current. The data were collected on 17 die per wafer. On each die, transistors with a 10 μm gate width at gate lengths between 0.15 μm and 1.00 μm were measured. An additional 20 μm×20 μm capacitance pad was measured. For Gm, Vt, and Idsat evaluation, the Vdd was set to 50 mV and Vt was obtained by linear extrapolation. For leakage current measurements, Vg was set equal to Vdd at a value of approximately 1.8 V. Further, constant voltage stress was measured with stress voltage set to 4.7 V. At the completion of the automated testing, C-V, I-V and Id-Vg were measured manually.
The data from the test lab was entered and modeled to calculate EOT and Vfb values. Tox was calculated from C-V data using quantum corrections to the simple relationship Tox=εoxA/C where εox is the permittivity of SiO2, A is the capacitor area, and C is the measured capacitance. The I-V data and the output from a model were then entered into a mobility model, which generated values for mobility, surface roughness, and interfacial state density.
Referring to
2. Electrical Results
The EOT and Vfb data extracted from the CVC model are shown in
3. EOT Data
The results of the experiment were plotted as EOT vs. the starting interface thickness before any PreDA is shown in
To further illustrate the effect of the starting interface, the thickness of the starting interface was plotted against the contribution of the high-k and subsequent processing effects, calculated for each split as interface thickness subtracted from the EOT, as shown in
4. EOT and Leakage
5. Vfb Results
A plot of Vfb vs. EOT is shown in
6. Transconductance, Saturation Current, and Threshold Voltage
A plot of linear transconductance from a 20 μm×20 μm device vs. the inverse of the EOT (shown as 1/EOT) is shown in
A plot of saturation current from a 20 μm×20 μm device vs. EOT is shown in
The Vt results in
7. Results from the Mobility Test
The thinner interfacial layer resulting from the NH3 process may have been one contributor to the deleterious effect on mobility. The NH3 also appears to have had a direct effect on mobility of O3 chemical oxide, as the mobility fell significantly on O3 wafers subjected to the NH3 PreDA.
For similar EOTs, the mobilities appeared to be higher on wafers with ISSG interfaces than on those with chemical oxides. This was similar to the behavior observed with the Idsat results. An additional graph showing the effect of the starting interface thickness vs. mobility is in
D. Results
Additional growth or changes in the interface composition seem to have occurred with thinner starting interfacial layers. The NH3 pre-treatment reduces EOTs where the thinner the initial interface, the greater the suppression or change. The SC1 chemical oxides behave differently than the O3 chemical and ISSG thermal oxides. In general, the SC1-SC2 interface resulted in fewer additional changes and was more suppressed by NH3. As the EOT decreased, leakage increased. The leakage current density trend suggested that the NH3 PreDA reduced leakage.
Transconductance increased or stayed constant when EOT decreased, corresponding to the use of the NH3. However, the NH3 PreDA degraded Gm on the O3 chemical oxide. The NH3 PreDA on O3 chemical oxide also appeared to significantly decrease Idsat with just a small change in EOT. Idsat was higher with the ISSG interfaces than on chemical oxides with similar or larger EOTs.
The NH3 PreDA leads to thinner interfacial layer and thinner EOTs, which appeared to contribute to lower mobility. The NH3 also appears to negatively impact the mobility of devices formed with O3 chemical oxides. For similar EOTs, the mobilities appeared to be higher on wafers with ISSG interfaces than those with chemical oxides. Finally, the data indicate that the SC1-SC2 chemical oxide has a deleterious effect on mobility.
A NH3 pre-treatment reduces EOTs by suppressing additional oxide growth or by changing the interface composition. The NH3 PreDA leads to thinner interfacial layers and thinner EOTs, which appeared to contribute to reduced leakage but lower mobility. The NH3 PreDA degraded Gm, Idsat, and mobility on the O3 chemical oxide compared to the scaled ISSG oxides. The SC1 chemical oxides appear to behave differently than the O3 and ISSG interfaces and had a largely negative impact on mobility. As such, the ISSG interfaces scaled appropriately and had better overall electrical performance compared to the chemical oxide interfaces.
With the benefit of the present disclosure, those having skill in the art will comprehend that techniques claimed herein may be modified and applied to a number of additional, different applications, achieving the same or a similar result. The claims attached hereto cover all such modifications that fall within the scope and spirit of this disclosure.
The terms a or an, as used herein, are defined as one or more than one. The term plurality, as used herein, is defined as two or more than two. The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically. The term approximately, as used herein, is defined as at least close to a given value (e.g., preferably within 10% of, more preferably within 1% of, and most preferably within 0.1% of).
This patent application claims priority to, and incorporates by reference in its entirety, U.S. provisional patent application Ser. No. 60/498,676 filed on Aug. 28, 2003, entitled, “A Method for Forming an Insulated Dielectric Interface Between High-K Material and Silicon.”
| Number | Date | Country | |
|---|---|---|---|
| 60498676 | Aug 2003 | US |
