Claims
- 1. A method of fabricating an integrated circuit device, the method comprising:forming a lattice-shaped isolation region in a semiconductor substrate, the lattice-shaped isolation region comprising an array of node regions linked by interconnecting regions; and forming an array of dummy conductive regions on the node regions of the lattice-shaped isolation region, the respective dummy conductive regions overlying respective ones of the node regions of the lattice-shaped isolation region.
- 2. A method according to claim 1, wherein said step of forming a lattice-shaped isolation region comprises the step of forming at least one of a trench isolation region and a field oxide isolation region.
- 3. A method according to claim 1:wherein said step of forming a lattice-shaped isolation region is preceded by the steps of forming a silicon on insulator (SOI) substrate comprising a first semiconductor layer, an insulation layer on the first semiconductor layer, and a second semiconductor layer on the insulation layer; and wherein said step of forming a lattice-shaped isolation region comprises forming the lattice-shaped isolation region on the second semiconductor layer.
- 4. A method of fabricating an integrated circuit device, the method comprising:forming an array of isolation regions defining a lattice-shaped dummy active region in a semiconductor substrate; and forming an array of dummy conductive regions on the array of isolation regions, respective ones of the dummy conductive regions constrained to overlie respective ones of the isolation regions.
- 5. A method according to claim 4, wherein said step of forming an array of dummy conductive regions comprises the step of forming a single dummy conductive region on each of the isolation regions of the array of isolation regions.
- 6. A method according to claim 4, wherein said step of forming an array of dummy conductive regions comprises the step of forming a respective plurality of dummy conductive regions on a respective one of the isolation regions of the array of isolation regions.
- 7. A method according to claim 4, wherein said step of forming an array of isolation regions comprises the step of forming at least one of a trench isolation region and a field oxide isolation region.
- 8. A method according to claim 4:wherein said step of forming an array of isolation regions is preceded by the steps of forming a silicon on insulator (SOI) substrate comprising a first semiconductor layer, an insulation layer on the first semiconductor layer, and a second semiconductor layer on the insulation layer; and wherein said step of forming an array of isolation regions comprises forming the array of isolation regions on the second semiconductor layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
98-25909 |
Jun 1998 |
KR |
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Parent Case Info
This application is a divisional of prior application Ser. No. 09/343,997, filed Jun. 30, 1999, U.S. Pat. No. 6,255,697, the disclosure of which is hereby incorporated herein by reference.
US Referenced Citations (10)