Patent Application
20180277426
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming various conductive structures, such as conductive lines/vias, that include a conductive liner layer without performing a CMP process to remove portions of the liner layer.
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements, such as transistors, capacitors, resistors, etc., to be formed on a given chip area according to a specified circuit layout. During the fabrication of complex integrated circuits using, for instance, MOS (Metal-Oxide-Semiconductor) technology, millions of transistors, e.g., N-channel transistors (NFETs) and/or P-channel transistors (PFETs), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically includes doped source and drain regions that are formed in a semiconducting substrate and separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
To improve the operating speed of field effect transistors (FETs), and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs and the overall functionality of the circuit. Further scaling (reduction in size) of the channel length of transistors is anticipated in the future. While this ongoing and continuing decrease in the channel length of transistor devices has improved the operating speed of the transistors and integrated circuits that are formed using such transistors, there are certain problems that arise with the ongoing shrinkage of feature sizes that may at least partially offset the advantages obtained by such feature size reduction. For example, as the channel length is decreased, the pitch between adjacent transistors likewise decreases, thereby increasing the density of transistors per unit area. This scaling also limits the size, i.e., the lateral width, of at least some of the conductive contact elements and structures, such as conductive lines and vias, which has the effect of increasing their electrical resistance. In general, the reduction in feature size and increased packing density makes everything more crowded on modern integrated circuit devices. Moreover, the physical size of these conductive structures is typically not uniform across an integrated circuit product, i.e., there may be regions that have very densely packed structures with very small lateral dimensions (such as device level contacts that actually contact the transistor devices) while there may be other regions (e.g., edge seal, crackstop) with conductive structures that have, in a relative sense, much larger lateral dimensions.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same level on which the circuit elements, such as transistors, are manufactured. Rather, modern integrated circuit products have multiple so-called metallization layer levels that, collectively, contain the “wiring” pattern for the product, i.e., the conductive structures that provide electrical connection to the transistors and the circuits, such as conductive vias and conductive metal lines. In general, the conductive metal lines are used to provide intra-level (same level) electrical connections, while inter-level (between levels) connections or vertical connections are referred to as vias. In short, the vertically oriented conductive via structures provide the electrical connection between the various stacked metallization layers. Accordingly, the electrical resistance of such conductive structures, e.g., lines and vias, becomes a significant issue in the overall design of an integrated circuit product, since the cross-sectional area of these elements is correspondingly decreased, which may have a significant influence on the effective electrical resistance and overall performance of the final product or circuit.
Copper (Cu) and tungsten (W) are currently the most common conductive materials used in conductive interconnect structures. But, as the critical dimension of such interconnects is reduced, e.g., to 20 nm and below, it may become more difficult to manufacture conductive structures comprised of copper or tungsten. Thus, there are ongoing investigations into the use of other conductive materials, such as ruthenium (Ru), to replace copper or tungsten, in whole or part, in such small scale conductive structures.
The formation of copper and tungsten metallization structures typically involves performing several process steps.
However, as everything becomes more crowded on an integrated circuit product, problems may arise when employing traditional metallization techniques. More specifically, it becomes more difficult to reliably fill very small trench/via patterns with copper or tungsten. To that end, semiconductor manufacturers have started to use other materials, such as ruthenium, to form such conductive structures. Ruthenium exhibits excellent (low) electrical resistance characteristics and low metal migration characteristics as the dimensions of the conductive structure is reduced (scaled). Ruthenium is a noble metal that may not be easily removed by performing a chemical mechanical polishing (CMP) process.
Additionally, ruthenium is a relatively expensive material, and, accordingly, it may not be economically viable to deposit ruthenium as the overfill material that would subsequently need to be removed by performing a CMP process.
The present disclosure is directed to various methods of forming various conductive structures that may solve or at least reduce some of the problems identified above.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various methods of forming conductive structures, such as conductive lines/vias. One illustrative method disclosed herein includes, among other things, forming a first trench/via and a wider second trench/via in a layer of insulating material, forming a conductive adhesion layer in the first trench/via and the second trench/via and performing a deposition process that results in the formation of a conductive liner layer in the second trench/via and such that the material of the conductive liner layer substantially fills the first trench/via. In this particular example, the method also includes performing an etching process to remove at least a portion of the conductive liner layer positioned within the second trench/via and above an upper surface of the conductive adhesion layer while leaving a portion of the conductive liner layer within the first trench/via, and removing portions of the conductive adhesion layer positioned above an upper surface of the layer of insulating material to define a conductive structure positioned in the first trench/via that comprises the material of the conductive adhesion layer and the material of the conductive liner layer.
Another illustrative method disclosed herein includes, among other things, forming a first trench/via and a wider second trench/via in a layer of insulating material, forming a conductive adhesion layer in the first and second trench/vias and above the upper surface of the layer of insulating material and performing a deposition process that results in the formation of a conductive liner layer in the second trench/via and such that the material of the conductive liner layer substantially fills the first trench/via. In this particular example, the method further includes performing a wet isotropic etching process to remove substantially all of the conductive liner layer positioned within the second trench/via and from above the upper surface of the layer of insulating material while leaving a portion of the conductive liner layer within the first trench/via, overfilling at least the second trench/via with a bulk conductive material and performing at least one process operation to remove portions of the bulk conductive material and the conductive adhesion layer from above the upper surface of the layer of insulating material to thereby result in the formation of a first conductive structure in the first trench/via and a second conductive structure in the second trench/via.
Yet another illustrative method disclosed herein includes, among other things, forming a first trench/via and a wider second trench/via in a layer of insulating material, forming a conductive adhesion layer in the first and second trench/vias and above the upper surface of the layer of insulating material and performing a deposition process that results in the formation of a conductive liner layer in the second trench/via and such that the material of the conductive liner layer substantially fills the first trench/via. In this particular example, the method also includes performing a dry anisotropic etching process on the conductive liner layer such that, after the dry anisotropic etching process is completed, a portion of the material of the conductive liner layer substantially fills the first trench/via and an internal sidewall spacer is defined within the second trench/via that is comprised of the material of the conductive liner layer, overfilling at least the second trench/via with a bulk conductive material and performing at least one process operation to remove portions of the bulk conductive material, the conductive adhesion layer and the conductive liner layer from above the upper surface of the layer of insulating material to thereby result in the formation of a first conductive structure in the first trench/via and a second conductive structure in the second trench/via.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase. To the extent the term “adjacent” is used herein and in the attached claims to described a positional relationship between two components or structures, that term should be understood and construed so as to cover situations where there is actual physical contact between the two components and to cover situations where such components are positioned near one another but there is no physical contact between the two components. Physical contact between two components will be specified within the specification and claims by use of the phrase “on and in contact with” or other similar language. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the methods disclosed herein may be employed in manufacturing a variety of different devices, including, but not limited to, logic devices, memory devices, etc., and the devices may be may be either NMOS or PMOS devices.
As will be appreciated by those skilled in the art after a complete reading of the present application, various doped regions, e.g., halo implant regions, well regions and the like, are not depicted in the attached drawings. Of course, the inventions disclosed herein should not be considered to be limited to the illustrative examples depicted and described herein. The various components and structures of the device 100 disclosed herein may be formed using a variety of different materials and by performing a variety of known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, spin-coating techniques, etc. The thicknesses of these various layers of material may also vary depending upon the particular application. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
The various components and structures of the device 100 may be initially formed using a variety of different materials and by performing a variety of known techniques. For example, the layer of insulating material 104 may be comprised of any type of insulating material, e.g., a low-k insulating material (k value less than 3.3), etc., it may be formed to any desired thickness and it may be formed by performing, for example, a chemical vapor deposition (CVD) process or spin-on deposition (SOD) process, etc.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
