Patent Application
20200098692
Integrated circuit (IC) dies are conventionally coupled to a package substrate for mechanical stability and to facilitate connection to other components, such as circuit boards. The interconnect pitch achievable by conventional substrates is constrained by manufacturing, materials, and thermal considerations, among others.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings.
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a microelectronic assembly may include a bridge structure having a surface; a first die coupled to the surface of the bridge structure by first interconnects, where the first die at least partially overlaps the bridge structure and is non-rectilinear to the bridge structure; and a second die coupled to the surface of the bridge structure by second interconnects, where the second die at least partially overlaps the bridge structure.
Communicating large numbers of signals between two or more dies in a multi-die IC package is challenging due to the increasingly small size of such dies, thermal constraints, and power delivery constraints, among others. Some conventional packages may include two or more active dies (i.e., two or more semiconductor devices, such as processors, controllers, logic devices, and memory devices) that are stacked, one on top of the other on a substrate. The package may include interconnections to provide power to the semiconductor dies within the package, as well as to enable transfer of data to and from the dies. Without the stacking of dies, data interconnections between active dies (i.e., in different packages) typically require long interlinks through conductive layers of a package substrate or a circuit board, such as a motherboard. These long interconnect distances increase inductance and may reduce signal performance. However, stacking of dies may increase the overall z-height of a package and may increase thermal and/or mechanical stress on bottom dies. Various ones of the embodiments disclosed herein may help achieve reliable attachment of multiple IC dies at a lower cost, with improved power efficiency, with higher bandwidth, and/or with greater design flexibility, relative to conventional approaches. Further, various ones of the microelectronic assemblies disclosed herein may exhibit better power delivery and signal speed while reducing the size of the package relative to conventional approaches, such as stacked dies. The microelectronic assemblies disclosed herein may be particularly advantageous for small and low-profile, compute-intensive applications in computers, tablets, industrial robots, and consumer electronics (e.g., wearable devices).
In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration, and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a “package” and an “IC package” are synonymous, as are a “die” and an “IC die.” The terms “top” and “bottom” may be used herein to explain various features of the drawings, but these terms are simply for ease of discussion, and do not imply a desired or required orientation. As used herein, the term “insulating” means “electrically insulating,” unless otherwise specified.
When used to describe a range of dimensions, the phrase “between X and Y” represents a range that includes X and Y. For convenience, the phrase “
As shown in
Although
The microelectronic assembly 100 may include a package substrate 102 coupled to a bridge structure 104 by PS interconnects 150-1. In particular, the top surface of the package substrate 102 may include a set of conductive contacts 146, and the bottom surface of the bridge structure 104 may include a set of conductive contacts 122; the conductive contacts 122 at the bottom surface of the bridge structure 104 may be electrically and mechanically coupled to the conductive contacts 146 at the top surface of the package substrate 102 by the PS interconnects 150-1. In the embodiment of
The bridge structure 104 may be a double-sided structure (in the sense that the bridge structure 104 has conductive contacts 122, 124 on two surfaces (e.g., a top surface and a bottom surface)). A bridge structure 104 that has interconnects of different pitches at a same surface (e.g., top surface DTB interconnects 130 or bottom surface interconnects 150-1) or at different surfaces (e.g., top surface DTB interconnects 130 and bottom surface interconnects 150-1) may be referred to as a mixed-pitch structure. In some embodiments, as shown in
The microelectronic assembly 100 of
Although
In the embodiment of
In some embodiments, the dies 114 in any of the microelectronic assemblies 100 disclosed herein may include on-package memory devices (e.g., random access memory (RAM)), I/O circuitry (e.g., I/O drivers), high bandwidth memory, accelerators, application-specific integrated circuits (e.g., artificial intelligence application-specific integrated circuits), a field programmable gate array, or any other suitable circuitry. In some embodiments, the microelectronic assembly 100 may be included in a server, and the dies 114 may be processing cores. In some such embodiments, it may be useful to have memory devices physically proximate to these processing cores, and thus some of the dies may be memory devices.
In some embodiments, the package substrate 102 may be a lower density medium and the bridge structure 104 and the dies 114-1, 114-2 may be a higher density medium. As used herein, the term “lower density” and “higher density” are relative terms indicating that the conductive pathways (e.g., including conductive lines and conductive vias) in a lower density medium are larger and/or have a greater pitch than the conductive pathways in a higher density medium. In some embodiments, a higher density medium may be manufactured using a modified semi-additive process or a semi-additive build-up process with advanced lithography (with small vertical interconnect features formed by advanced laser or lithography processes), while a lower density medium may be a printed circuit board (PCB) manufactured using a standard PCB process (e.g., a standard subtractive process using etch chemistry to remove areas of unwanted copper, and with coarse vertical interconnect features formed by a standard laser process). In some embodiments, the package substrate 102 may be a set of redistribution layers formed on a wafer or panel carrier by laminating or spinning on a dielectric material, and creating conductive vias and lines by laser drilling or lithography and plating. Any suitable technique may be used to form the recess 108. For example, in some embodiments, the recess 108 may be laser-drilled down to a planar metal stop in the package substrate 102; once the metal stop is reached, the metal stop may be removed to expose the conductive contacts 146 at the bottom of the recess 108. In some embodiments, the recess 108 may be formed by a mechanical drill. Any method known in the art for fabrication of the package substrate 102 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.
The package substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive pathways through the dielectric material (e.g., including conductive traces and/or conductive vias, as shown). In some embodiments, the insulating material of the package substrate 102 may be a dielectric material, such as an organic dielectric material, a fire retardant grade 4 material (FR-4), bismaleimide triazine (BT) resin, polyimide materials, glass reinforced epoxy matrix materials, or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). In particular, when the package substrate 102 is formed using standard PCB processes, the package substrate 102 may include FR-4, and the conductive pathways in the package substrate 102 may be formed by patterned sheets of copper separated by build-up layers of the FR-4. The conductive pathways in the package substrate 102 may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable.
In some embodiments, one or more of the conductive pathways in the package substrate 102 may extend between a conductive contact 146 at the top surface of the package substrate 102 and a conductive contact 140 at the bottom surface of the package substrate 102. In some embodiments, one or more of the conductive pathways in the package substrate 102 may extend between a conductive contact 146 at the bottom of the recess 108 and a conductive contact 140 at the bottom surface of the package substrate 102. In some embodiments, one or more of the conductive pathways in the package substrate 102 may extend between different conductive contacts 146 at the top surface of the package substrate 102 (e.g., between a conductive contact 146 at the bottom of the recess 108 and a different conductive contact 146 at the top surface of the package substrate 102). In some embodiments, one or more of the conductive pathways in the package substrate 102 may extend between different conductive contacts 140 at the bottom surface of the package substrate 102.
The dies 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and multiple conductive pathways formed through the insulating material. In some embodiments, the insulating material of a die 114 may include a dielectric material, such as silicon dioxide, silicon nitride, oxynitride, polyimide materials, glass reinforced epoxy matrix materials, or a low-k or ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymeric dielectrics, photo-imageable dielectrics, and/or benzocyclobutene-based polymers). In some embodiments, the insulating material of a die 114 may include a semiconductor material, such as silicon, germanium, or a III-V material (e.g., gallium nitride), and one or more additional materials. For example, an insulating material may include silicon oxide or silicon nitride. The conductive pathways in a die 114 may include conductive traces and/or conductive vias, and may connect any of the conductive contacts in the die 114 in any suitable manner (e.g., connecting multiple conductive contacts on a same surface or on different surfaces of the die 114). Example structures that may be included in the dies 114 disclosed herein are discussed below with reference to
Although
As discussed above, in the embodiment of
The microelectronic assembly 100 of
The microelectronic assembly 100 of
The microelectronic assembly 100 of
The microelectronic assembly 100 of
The PS interconnects 150 disclosed herein may take any suitable form. In some embodiments, a set of PS interconnects 150 may include solder (e.g., solder bumps or balls that are subject to a thermal reflow to form the PS interconnects 150). PS interconnects 150 that include solder may include any appropriate solder material, such as lead/tin, tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, tin/nickel/copper, tin/bismuth/copper, tin/indium/copper, tin/zinc/indium/bismuth, or other alloys. In some embodiments, a set of PS interconnects 150 may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. An anisotropic conductive material may include conductive materials dispersed in a non-conductive material. In some embodiments, an anisotropic conductive material may include microscopic conductive particles embedded in a binder or a thermoset adhesive film (e.g., a thermoset biphenyl-type epoxy resin, or an acrylic-based material). In some embodiments, the conductive particles may include a polymer and/or one or more metals (e.g., nickel or gold). For example, the conductive particles may include nickel-coated gold or silver-coated copper that is in turn coated with a polymer. In another example, the conductive particles may include nickel. When an anisotropic conductive material is uncompressed, there may be no conductive pathway from one side of the material to the other. However, when the anisotropic conductive material is adequately compressed (e.g., by conductive contacts on either side of the anisotropic conductive material), the conductive materials near the region of compression may contact each other so as to form a conductive pathway from one side of the film to the other in the region of compression.
The DTB interconnects 130 disclosed herein may take any suitable form. The DTB interconnects 130 may have a finer pitch than the PS interconnects 150 in a microelectronic assembly. In some embodiments, the dies 114 on either side of a set of DTB interconnects 130 may be unpackaged dies, and/or the DTB interconnects 130 may include small conductive bumps or pillars (e.g., copper bumps or pillars) attached to the conductive contacts by solder. In some embodiments, a set of DTB interconnects 130 may include solder. DTB interconnects 130 that include solder may include any appropriate solder material, such as any of the materials discussed above. In some embodiments, a set of DTB interconnects 130 may include an anisotropic conductive material, such as any of the materials discussed above. In some embodiments, the DTB interconnects 130 may be used as data transfer lanes, while the PS interconnects 150 may be used for power and ground lines, among others. In some embodiments, some or all of the DTB interconnects 130 in a microelectronic assembly 100 may be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or plated interconnects). In some embodiments, some or all of the DTB interconnects 130 in a microelectronic assembly 100 may be solder interconnects that include a solder with a higher melting point than a solder included in some or all of the PS interconnects 150. For example, when the DTB interconnects 130 in a microelectronic assembly 100 are formed before the PS interconnects 150 are formed (e.g., when the dies 114-1, 114-2 are coupled to the bridge structure and form a subassembly that is coupled to the package substrate 102), solder-based DTB interconnects 130 may use a higher-temperature solder (e.g., with a melting point above 200 degrees Celsius), while the PS interconnects 150 may use a lower-temperature solder (e.g., with a melting point below 200 degrees Celsius). In some embodiments, a higher-temperature solder may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, a lower-temperature solder may include tin and bismuth (e.g., eutectic tin bismuth) or tin, silver, and bismuth. In some embodiments, a lower-temperature solder may include indium, indium and tin, or gallium.
Any suitable technique may be used to form the DTB interconnects 130 and attach the dies 114 to the bridge structure 104, such as metal-to-metal attachment techniques, solder techniques, or anisotropic conductive material techniques. In some embodiments, the dies 114 may be coupled to the top surface of the bridge structure 104 via the DTB interconnects 130, and then the bridge structure 104 and the attached dies 114 may be coupled to the top surface of the package substrate 102 via the PS interconnects 150. In some embodiments, the bridge structure 104 may be coupled to the package substrate via PS interconnects 150, and then the dies 114 may be coupled to the bridge structure 104 via DTB interconnects 130 and to the package substrate 102 via PS interconnects 150. The PS interconnects 150 and DTB interconnects 130 may take any of the forms disclosed herein (e.g., solder interconnects, or anisotropic conductive material interconnects), and any suitable techniques may be used to form the PS interconnects 150 and DTB interconnects 130 (e.g., a mass reflow process or a thermal compression bonding process).
In some embodiments, the bridge structure 104 may be arranged as a bridge between multiple other dies 114, and may also have additional dies 114 disposed thereon (e.g., wholly above the bridge structure). For example,
As noted above, in some embodiments, the package substrate 102 may not include any recesses 108. For example,
Any of the non-rectilinear arrangements of dies 114 and bridge structures 104 illustrated in any of the accompanying figures may be part of a continuing arrangement in a microelectronic assembly 100. For example,
The microelectronic assemblies 100 disclosed herein may be included in any suitable electronic component.
The IC device 1600 may include one or more device layers 1604 disposed on the die substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in
Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1602 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1602 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1620 may be formed within the die substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S/D regions 1620 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1602 to form the S/D regions 1620. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1602 may follow the ion-implantation process. In the latter process, the die substrate 1602 may first be etched to form recesses at the locations of the S/D regions 1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1620. In some implementations, the S/D regions 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1620 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1620.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1640) of the device layer 1604 through one or more interconnect layers disposed on the device layer 1604 (illustrated in
The interconnect pathways 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect pathways 1628 depicted in
In some embodiments, the interconnect pathways 1628 may include lines 1628a and/or vias 1628b filled with an electrically conductive material such as a metal. The lines 1628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1602 upon which the device layer 1604 is formed. For example, the lines 1628a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between the interconnect pathways 1628, as shown in
A first interconnect layer 1606 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628a and/or vias 1628b, as shown. The lines 1628a of the first interconnect layer 1606 may be coupled with contacts (e.g., the S/D contacts 1624) of the device layer 1604.
A second interconnect layer 1608 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 with the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the lines 1628a and the vias 1628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual damascene process) in some embodiments.
A third interconnect layer 1610 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1619 in the IC device 1600 (i.e., farther away from the device layer 1604) may be thicker.
The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606-1610. In
In some embodiments in which the IC device 1600 is a double-sided die (e.g., like the die 114-1), the IC device 1600 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1604. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 1606-1610, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 1604 and additional conductive contacts (not shown) on the opposite side of the IC device 1600 from the conductive contacts 1636.
In other embodiments in which the IC device 1600 is a double-sided die (e.g., like the die 114-1), the IC device 1600 may include one or more TSVs through the die substrate 1602; these TSVs may make contact with the device layer(s) 1604, and may provide conductive pathways between the device layer(s) 1604 and additional conductive contacts (not shown) on the opposite side of the IC device 1600 from the conductive contacts 1636.
In some embodiments, the circuit board 1702 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate. In some embodiments the circuit board 1702 may be, for example, a circuit board.
The IC device assembly 1700 illustrated in
The package-on-interposer structure 1736 may include an IC package 1720 coupled to an interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in
In some embodiments, the interposer 1704 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to TSVs 1706. The interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.
The IC device assembly 1700 illustrated in
Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components illustrated in
The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic RAM (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic RAM (eDRAM) or spin transfer torque magnetic RAM (STT-MRAM).
In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMLS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1812 may include multiple communication chips. For instance, a first communication chip 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communications, and a second communication chip 1812 may be dedicated to wired communications.
The electrical device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).
The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the electrical device 1800, as known in the art.
The electrical device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1800 may have any desired form factor, such as a computing device or a mobile computing device (e.g., a hand-held, portable or mobile electrical device, such as a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server, or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 is a microelectronic assembly, including: a bridge structure having a surface; a first die coupled to the surface of the bridge structure by first interconnects, wherein the first die at least partially overlaps the bridge structure and is non-rectilinear to the bridge structure; and a second die coupled to the surface of the bridge structure by second interconnects, wherein the second die at least partially overlaps the bridge structure.
Example 2 may include the subject matter of Example 1, and may further specify that the second die is non-rectilinear to the bridge structure.
Example 3 may include the subject matter of Example 1, and may further specify that the second die is non-rectilinear to the first die.
Example 4 may include the subject matter of Example 1, and may further specify that the bridge structure is a double-sided die.
Example 5 may include the subject matter of Example 1, and may further specify that the bridge structure is an active interposer having first conductive contacts on a first surface and second conductive contacts on an opposing second surface.
Example 6 may include the subject matter of Example 1, and may further specify that the bridge structure is a passive interposer having a plurality of through silicon vias.
Example 7 may include the subject matter of Example 1, and may further specify that the bridge structure has n-number of sides and n-number of dies coupled to the bridge structure, and wherein at least one individual die of the n-number of dies is non-rectilinear to another individual die of the n-number of dies.
Example 8 may include the subject matter of Example 1, and may further specify that the bridge structure has n-number of sides and (n+1)-number of dies coupled to the bridge structure, and wherein at least one individual die of the (n+1)-number of dies is non-rectilinear to another individual die of the (n+1)-number of dies.
Example 9 may include the subject matter of Example 1, and may further specify that the first die is rectilinear to the second die.
Example 10 may include the subject matter of Example 1, and may further include: a third die coupled to the surface of the bridge structure by third interconnects, wherein a footprint of the third die is wholly within a footprint of the bridge structure.
Example 11 may include the subject matter of Example 10, and may further specify that the third die is a die stack.
Example 12 is a microelectronic assembly, including: a package substrate having a first surface and an opposing second surface; a bridge structure having a first surface and an opposing second surface on the second surface of the package substrate, wherein the first surface of the bridge structure is coupled to the second surface of the package substrate; and a first die on the second surface of the bridge structure and partially overlapping the bridge structure, wherein the first die is coupled to the second surface of the bridge structure by first interconnects and coupled to the second surface of the package substrate by second interconnects, and wherein the first die is non-rectilinear to the bridge structure.
Example 13 may include the subject matter of Example 12, and may further specify that the bridge structure is rectangular.
Example 14 may include the subject matter of Example 12, and may further specify that the bridge structure is non-rectangular.
Example 15 may include the subject matter of Example 12, and may further specify that the first die is rectangular.
Example 16 may include the subject matter of Example 12, and may further specify that the first die is non-rectangular.
Example 17 may include the subject matter of Example 12, and may further specify that the package substrate is rectangular.
Example 18 may include the subject matter of Example 12, and may further specify that the package substrate is non-rectangular.
Example 19 may include the subject matter of Example 12, and may further specify that the first die overlaps the bridge structure by a maximum distance of between Example 0.5 millimeters and 20 millimeters.
Example 20 may include the subject matter of Example 12, and may further specify that the bridge structure is at least partially in a recess in the package substrate.
Example 21 may include the subject matter of Example 12, and may further specify that the first interconnects or the second interconnects include solder.
Example 22 may include the subject matter of Example 12, and may further specify that the first interconnects or the second interconnects include an anisotropic conductive material.
Example 23 may include the subject matter of Example 12, and may further specify that the first interconnects or the second interconnects include plated interconnects.
Example 24 is a computing device, including: a microelectronic assembly, including: a package substrate having a first surface and an opposing second surface; a bridge structure having a first surface and an opposing second surface, wherein the bridge structure is embedded in a first dielectric layer, and wherein the first surface of the bridge structure is coupled to the second surface of the package substrate; a first die having a first surface and an opposing second surface, wherein the first die is embedded in a second dielectric layer on the first dielectric layer, wherein the first die at least partially overlaps the bridge structure, wherein the first surface of the first die is coupled to the second surface of the bridge structure by first interconnects, and wherein the first die is non-rectilinear to the bridge structure; and a second die having a first surface and an opposing second surface, wherein the second die is embedded in the second dielectric layer, and wherein the first surface of the second die is coupled to the second surface of the bridge structure by second interconnects.
Example 25 may include the subject matter of Example 24, and may further specify that the second die is non-rectilinear to the bridge structure.
Example 26 may include the subject matter of Example 24, and may further specify that the second die is non-rectilinear to the first die.
Example 27 may include the subject matter of Example 24, and may further specify that the first die or the second die is a central processing unit.
Example 28 may include the subject matter of Example 24, and may further specify that the first die or the second die includes a memory device.
Example 29 may include the subject matter of Example 24, and may further specify that the first die or the second die is a high bandwidth memory device.
Example 30 may include the subject matter of Example 24, and may further specify that the package substrate is a printed circuit board.
Example 31 may include the subject matter of Example 24, and may further specify that the computing device is a server.
Example 32 may include the subject matter of Example 24, and may further specify that the computing device is a mobile computing device.
Example 33 may include the subject matter of Example 24, and may further specify that the computing device is a wearable computing device.
Example 34 may include the subject matter of Example 24, and may further specify that the first surface of the first die is coupled to the second surface of the package substrate by third interconnects.
Example 35 may include the subject matter of Example 34, and may further specify that the third interconnects include a conductive pillar.
Example 36 may include the subject matter of Example 24, and may further specify that the first surface of the second die is coupled to the second surface of the package substrate by fourth interconnects.
Example 37 may include the subject matter of Example 36, and may further specify that the fourth interconnects include a conductive via.
Example 38 is a method of manufacturing a microelectronic assembly, including: forming first interconnects between a bridge structure and a first die, wherein the bridge structure has a first surface with first conductive contacts and an opposing second surface with second conductive contacts, wherein the first die has a surface with conductive contacts, wherein the first interconnects couple the second conductive contacts of the bridge structure to the conductive contacts of the first die, and wherein the first die at least partially overlaps the bridge structure and is non-rectilinear to the bridge structure; and forming second interconnects between the bridge structure and a second die, wherein the second die has a surface with conductive contacts, wherein the second interconnects couple the second conductive contacts of the bridge structure to the conductive contacts of the second die, and wherein the second die at least partially overlaps the bridge structure.
Example 39 may include the subject matter of Example 38, and may further specify that the second die is non-rectilinear to the bridge structure.
Example 40 may include the subject matter of Example 38, and may further specify that the second die is non-rectilinear to the first die.
Example 41 may include the subject matter of Example 38, and may further include: forming third interconnects between the bridge structure and a package substrate, wherein the package substrate has a surface with conductive contacts, wherein the third interconnects couple the first conductive contacts of the bridge structure to the conductive contacts of the package substrate.
Example 42 may include the subject matter of Example 41, and may further include: forming fourth interconnects between the first die and the package substrate, wherein the fourth interconnects couple the conductive contacts of the first die to the conductive contacts of the package substrate.
Example 43 may include the subject matter of Example 42, and may further include: forming fifth interconnects between the second die and the package substrate, wherein the fifth interconnects couple the conductive contacts of the second die to the conductive contacts of the package substrate.
