Patent Application
20250201732
For the past several decades, scaling of features in integrated circuits (ICs) has been a driving force behind an ever-growing semiconductor industry and emerging applications in fields such as big data, artificial intelligence, mobile communications, and autonomous driving. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize fabrication and performance of each component (e.g., of each transistor) is becoming increasingly significant.
Parallel to optimizations at the transistor level, advanced IC packaging landscape is rapidly evolving to accommodate performance expectations and requirements of shrinking transistor size. Multiple IC dies are now commonly coupled together in a multi-die IC package to integrate features or functionality and to facilitate connections to other components, such as package substrates. For example, IC packages may include an embedded multi-die interconnect bridge (EMIB) for coupling two or more IC dies.
Integration of multiple dies in a single IC package has tremendous benefits but adds additional complexities due to placing materials with different material properties in close proximity to one another. When an IC package undergoes multiple processing steps involving various temperatures and pressure loads, individual materials within the package may behave differently from one another, resulting in out of plane deformation of various layers, known as “package warpage.” One way to address package warpage is to use stiffer cores to which different IC dies are attached. Recently, glass cores have been explored as alternatives to organic resin-based cores (e.g., cores based on using Ajinomoto Build-up Film (ABF)). Glass is considered more rigid than organic resin-based materials and has several advantages such as excellent thermal properties, low coefficient of thermal expansion (CTE), high electrical insulation, chemical resistance, optical transparency, and compatibility with advances semiconductor properties. However, a major challenge for widespread adoption of glass cores is the fact that glass is highly susceptible to damage due to mechanical and/or thermal stresses.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings.
As mentioned above, a major challenge for widespread adoption of glass cores is the fact that glass is highly susceptible to damage due to mechanical and/or thermal stresses. One source of mechanical and thermal stresses in glass is singulation process (sometimes referred to as “dicing” or “cutting”) that takes place during manufacturing of glass cores. Singulation is a process in which a cutting tool (e.g., a glass cutter, a diamond blade, or a saw) applies mechanical force to the surface of a glass panel in order to separate (e.g., dice or cut) the panel into individual glass units having a smaller form factor than the panel. The mechanical force applied by the cutting tool may create a localized stress concentration (e.g., regions of higher stress) at or near the surfaces where the cutting tool contacts the glass, e.g., at or near the edges of the individual glass units, where, as used herein, the term “edge” refers to a side/sidewall that is between top and the bottom faces of a glass unit, a glass core, or glass panel. Because glass is a brittle material characterized by its lack of ductility (e.g., characterized by its limited ability to undergo significant plastic deformation before fracturing), localized stress concentration often leads to formation of cracks at the edges of singulated glass units. Besides imposing mechanical stress onto glass, singulation can also generate thermal stress due to friction between the cutting tool and glass, heating up the surface being cut. The heat can cause localized expansion and contraction of glass, further promoting crack formation and propagation.
Singulation is not the only source of stress and damage that may affect glass cores. Presence of materials with different CTEs on top and/or on the bottom of glass cores (e.g., metals of conductive pathways and/or dielectric materials of build-up layers) adds to the stresses in glass (such stresses referred to as “CTE mismatch-induced stresses”), further exacerbating the problem of crack formation. Even if cracks don't form immediately during singulation, cutting of brittle materials like glass often results in individual glass units with edges that are rough, jagged, or otherwise uneven. Repeated thermal cycling during operation of microelectronic assemblies that include glass cores with such edges can gradually weaken the glass surface due to CTE mismatch-induced stresses, leading to formation of cracks at that time. Furthermore, even before singulation, glass may have tiny surface flaws or defects, which can act as initiation points for crack formation, with additional mechanical and/or thermal stresses increasing the severity of crack growth.
Once cracks start to form, they tend to propagate through glass, with additional mechanical and/or thermal stresses increasing the severity of crack propagation. In particular, the stress concentration at the edges of the glass units encourages the cracks to extend further into glass, and the inherent brittleness of glass makes it particularly susceptible to crack propagation. Propagation of cracks may even cause a glass volume to split into two halves around a plane parallel to the top/bottom surfaces of the glass volume and being about in the middle of the glass volume, one half being the bottom half and the other half being the top half of what is supposed to be a single structure.
As the foregoing illustrates, crack formation and propagation in glass compromises the structural integrity of glass, making microelectronic assemblies with glass cores particularly prone to failure over time. Embodiments of the present disclosure relate to various techniques, as well as to related devices and methods, for alleviating (e.g., mitigating or reducing) the negative effects of crack formation and propagation in glass. In particular, embodiments of the present disclosure are based on implementing various features utilizing crack-healing materials for glass cores, e.g., utilizing crack-healing materials around and/or in glass cores. For example, in one aspect of the present disclosure, a microelectronic assembly includes a glass core having a structure of a crack-healing material on its edge, where the crack-healing material includes carbon, e.g., as a part of an organic monomer, oligomer, or a polymer, or as a part of a carbide of an inorganic material such as boron, titanium, or silicon. In another aspect of the present disclosure, a microelectronic assembly includes a glass core in which particles that include an inorganic crack-healing material are dispersed, where the material includes carbon or boron, and a volume occupied by the particles is between about 5% and about 55% of the volume of the glass core. Formation of a crack somewhere in the glass core (e.g., at the edge of the glass core or when an opening is formed in the glass core for a future through-glass via (TGV) may activate the crack-healing material, causing the material to at least partially fill the crack (which may be described as “healing” the crack) and, therefore, reduce or eliminate growth and/or propagation of the crack.
Integration of layers of different materials (e.g., multiple dies, redistribution layers, package substrates) in a single IC package or a microelectronic assembly is challenging due to package warpage, among others. Providing IC packages or microelectronic assemblies with crack-healing materials for glass cores as described herein may help. Various ones of the embodiments disclosed herein may help achieve reliable integration of multiple layers of different materials within a single microelectronic assembly at a lower cost and/or with greater design flexibility, relative to conventional approaches. Various ones of the microelectronic assemblies disclosed herein may exhibit reduced warpage, relative to microelectronic assemblies without glass cores. The microelectronic assemblies disclosed herein may be particularly advantageous for small and low-profile applications in computers, tablets, industrial robots, and consumer electronics (e.g., wearable devices).
In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.
Any of the features discussed with reference to any of accompanying drawings herein may be combined with any other features to form a microelectronic assembly 100, a glass core 110, an IC device 1600, an IC device assembly 1700, or a communication device 1800, as appropriate. For convenience, the phrase “dies 114” may be used to refer to a collection of dies 114-1, 114-2, and so on, etc. A collection of drawings labeled with different letters may be referred to without the letters, e.g., a collection of
The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration and may not reflect real-life process limitations which may cause various features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers. There may be other defects not listed here but that are common within the field of semiconductor device fabrication and packaging. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of a glass core with one or more crack-healing materials around and/or in the glass core as described herein.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used to describe a range of dimensions, the phrase “between X and Y” represents a range that includes X and Y. When used to describe a location of an element, the phrase “between X and Y” represents a region that is spatially between element X and element Y. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−10%, e.g., within +/−5% or within +/−2%, of the exact orientation.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die.” Furthermore, the terms “chip,” “chiplet,” “die,” and “IC die” may be used interchangeably herein.
Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “a dielectric material” may include one or more dielectric materials or “an insulator material” may include one or more insulator materials. The terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. The term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide, while the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide. The term “insulating” and variations thereof (e.g., “insulative” or “insulator”) means “electrically insulating,” the term “conducting” and variations thereof (e.g., “conductive” or “conductor”) means “electrically conducting,” unless otherwise specified. With reference to optical signals and/or devices, components and elements that operate on or using optical signals, the term “conducting” can also mean “optically conducting.” The term “insulating material” refers to solid materials (and/or liquid materials that solidify after processing as described herein) that are substantially electrically nonconducting. They may include, as examples and not as limitations, organic polymers and plastics, and inorganic materials such as ionic crystals, porcelain, glass, silicon and alumina or a combination thereof. They may include dielectric materials, high polarizability materials, and/or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Further examples of insulating materials are underfills and molds or mold-like materials used in packaging applications, including for example, materials used in organic interposers, package supports and other such components.
As used herein, a “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components (e.g., part of a conductive interconnect); conductive contacts may be recessed in, flush with, or extending away (e.g., having a pillar shape) from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket, or portion of a conductive line or via). In a general sense, an “interconnect” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, facilitating communication of electrical signals between them; an optical interconnect provides optical connectivity between two optical components, facilitating communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are comprised in the term “interconnect.” The nature of the interconnect being described is to be understood herein with reference to the signal medium associated therewith. Thus, when used with reference to an electronic device, such as an IC that operates using electrical signals, the term “interconnect” describes any element formed of a conductive material for providing electrical connectivity to one or more elements associated with the IC or/and between various such elements. In such cases, the term “interconnect” may refer to both conductive traces (also sometimes referred to as “metal traces,” “lines,” “metal lines,” “wires,” “metal wires,” “trenches,” or “metal trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”). Sometimes, conductive traces and vias may be referred to as “metal traces” and “metal vias”, respectively, to highlight the fact that these elements include conductive materials such as metals. Likewise, when used with reference to a device that operates on optical signals as well, such as a photonic IC (PIC), “interconnect” may also describe any element formed of a material that is optically conductive for providing optical connectivity to one or more elements associated with the PIC. In such cases, the term “interconnect” may refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fiber, optical splitters, optical combiners, optical couplers, and optical vias.
The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and multiple conductive pathways formed through the insulating material. In some embodiments, the insulating material of a die 114 may include a dielectric material, such as silicon dioxide, silicon nitride, oxynitride, polyimide materials, glass reinforced epoxy matrix materials, or a low-k or ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymeric dielectrics, photo-imageable dielectrics, and/or benzocyclobutene-based polymers). In some embodiments, the insulating material of a die 114 may include a semiconductor material, such as silicon, germanium, or a III-V material (e.g., gallium nitride), and one or more additional materials. For example, an insulating material may include silicon oxide or silicon nitride. The conductive pathways in a die 114 may include conductive traces and/or conductive vias, and may connect any of the conductive contacts in the die 114 in any suitable manner (e.g., connecting multiple conductive contacts on a same surface or on different surfaces of the die 114). Example structures that may be included in the dies 114 disclosed herein are discussed below with reference to the IC device 1600. The conductive pathways in the dies 114 may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable. In some embodiments, the die 114 is a wafer. In some embodiments, the die 114 is a monolithic silicon, a fan-out or fan-in package die, or a die stack (e.g., wafer stacked, die stacked, or multi-layer die stacked).
In some embodiments, the die 114 may include conductive pathways to route power, ground, and/or signals to/from other dies 114 included in the microelectronic assembly 100. For example, the die 114-1 may include TSVs 125, including a conductive via, such as a metal via, isolated from the surrounding silicon or other semiconductor material by a barrier oxide), or other conductive pathways through which power, ground, and/or signals may be transmitted between the package substrate 102 and one or more dies 114 “on top” of the die 114-1 (e.g., in the embodiment of
The dielectric material 112 of the substrate 107 may be formed in layers (e.g., at least a first dielectric material layer 112A and a second dielectric material layer 112B). In some embodiments, the dielectric material 112 may include an organic material, such as an organic build-up film. In some embodiments, the dielectric material 112 may include a ceramic, an epoxy film having filler particles therein, glass, an inorganic material, or combinations of organic and inorganic materials, for example. In some embodiments, the conductive material 108 may include a metal (e.g., copper). In some embodiments, the substrate 107 may include layers of dielectric material 112/conductive material 108, with lines/traces/pads/contacts (e.g., conductive traces 108A) of conductive material 108 in one layer electrically coupled to lines/traces/pads/contacts (e.g., conductive traces 108A) of conductive material 108 in an adjacent layer by vias (e.g., 108B) of the conductive material 108 extending through the dielectric material 112. Conductive traces 108A may be referred to herein as “conductive lines,” “conductive elements,” “conductive pads,” or “conductive contacts.” A substrate 107 including such layers may be formed using a printed circuit board (PCB) fabrication technique, for example.
An individual layer of dielectric material 112 (e.g., a first dielectric material layer 112A) may include a cavity 119 and the bridge die 114-1 may be at least partially nested in the cavity 119. The bridge die 114-1 may be surrounded by (e.g., embedded in) a next individual layer of dielectric material 112 (e.g., a second dielectric material layer 112B). In some embodiments, a cavity 119 is tapered, narrowing towards a bottom face of the cavity 119 (e.g., the surface towards the first surface 120-1 of the substrate 107). A cavity 119 may be indicated by a seam between the dielectric material 112A and the dielectric material 112B. As shown in
A substrate 107 may include N layers of conductive material 108, where N is an integer greater than or equal to one. In
Although a particular number and arrangement of layers of dielectric material 112/conductive material 108 are shown in various ones of the accompanying figures, these particular numbers and arrangements are simply illustrative, and any desired number and arrangement of dielectric material 112/conductive material 108 may be used. Further, although a particular number of layers are shown in the substrate 107 (e.g., four layers), these layers may represent only a portion of the substrate 107, for example, further layers may be present (e.g., layers N−4, N−5, N−6, etc.).
As shown in
In some implementations, together, the substrate 107, including the glass core 110, and the dies 114 may be referred to as a “a multi-layer die subassembly 104.” The glass core 110 may provide mechanical stability to the multi-layer die subassembly 104, the substrate 107, and/or the microelectronic assembly 100. The glass core 110 may reduce warpage and may provide a more robust surface for attachment of the multi-layer die subassembly 104 to a package substrate 102 or other substrate (e.g., an interposer or a circuit board).
In some implementations, together, the dielectric material 112 of the substrate 107 and the glass core 110 may be referred to as a “multi-layer glass substrate.” In some such embodiments, the multi-layer glass substrate may be a coreless substrate. In some such embodiments, the glass core 110 may be a glass layer having a thickness in a range of about 25 microns to 50 microns. In some embodiments, the further layers 111 may also be part of the multi-layer glass substrate.
The TGVs 115 may be vias extending between a first side and a second side of the glass core 110 (e.g., between the bottom face and the top face of the glass core 110), the vias including any appropriate conductive material, e.g., a metal such as copper, silver, nickel, gold, aluminum, or other metals or alloys, for example. The TGVs 115 may be formed using any suitable process, including, for example, a direct laser drilling or laser induced deep etching process. In some embodiments, the TGVs 115 disclosed herein may have a pitch between 50 microns and 500 microns, e.g., as measured from a center of one TGV 115 to a center of an adjacent TGV 115. The TGVs 115 may have any suitable size and shape. In some embodiments, the TGVs 115 may have a circular, rectangular, or other shaped cross-section. In some embodiments, at least some of the TGVs 115 may have an hourglass shape, e.g., as shown in
The substrate 107 (e.g., further layers 111) may be coupled to a package substrate 102 by STPS interconnects 150. In particular, the top face of the package substrate 102 may include a set of conductive contacts 146. Conductive contacts 144 on the bottom face of the substrate 107 may be electrically and mechanically coupled to the conductive contacts 146 on the top face of the package substrate 102 by the STPS interconnects 150. The package substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive pathways to route power, ground, and signals through the dielectric material (e.g., including conductive traces and/or conductive vias, as shown). In some embodiments, the insulating material of the package substrate 102 may be a dielectric material, such as an organic dielectric material, a fire retardant grade 4 material (FR-4), bismaleimide triazine (BT) resin, polyimide materials, glass reinforced epoxy matrix materials, organic dielectrics with inorganic fillers or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). In particular, when the package substrate 102 is formed using standard PCB processes, the package substrate 102 may include FR-4, and the conductive pathways in the package substrate 102 may be formed by patterned sheets of copper separated by build-up layers of the FR-4. The conductive pathways in the package substrate 102 may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable. In some embodiments, the package substrate 102 may be formed using a lithographically defined via packaging process. In some embodiments, the package substrate 102 may be manufactured using standard organic package manufacturing processes, and thus the package substrate 102 may take the form of an organic package. In some embodiments, the package substrate 102 may be a set of redistribution layers formed on a panel carrier by laminating or spinning on a dielectric material, and creating conductive vias and lines by laser drilling and plating. In some embodiments, the package substrate 102 may be formed on a removable carrier using any suitable technique, such as a redistribution layer technique. Any method known in the art for fabrication of the package substrate 102 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.
In some embodiments, the package substrate 102 may be a lower density medium and the die 114 may be a higher density medium or have an area with a higher density medium. As used herein, the term “lower density” and “higher density” are relative terms indicating that the conductive pathways (e.g., including conductive interconnects, conductive lines, and conductive vias) in a lower density medium are larger and/or have a greater pitch than the conductive pathways in a higher density medium. In some embodiments, a higher density medium may be manufactured using a modified semi-additive process or a semi-additive build-up process with advanced lithography (with small vertical interconnect features formed by advanced laser or lithography processes), while a lower density medium may be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process using etch chemistry to remove areas of unwanted copper, and with coarse vertical interconnect features formed by a standard laser process). In other embodiments, the higher density medium may be manufactured using semiconductor fabrication process, such as a single damascene process or a dual-damascene process. In some embodiments, additional dies may be disposed on the top face of the dies 114-2, 114-3. In some embodiments, additional components may be disposed on the top face of the dies 114-2, 114-3. Additional passive components, such as surface-mount resistors, capacitors, and/or inductors, may be disposed on the top face or the bottom face of the package substrate 102, or embedded in the package substrate 102.
The microelectronic assembly 100 of
The STPS interconnects 150 disclosed herein may take any suitable form. In some embodiments, a set of STPS interconnects 150 may include solder (e.g., solder bumps or balls that are subject to a thermal reflow to form the STPS interconnects 150), for example, as shown in
The DTD interconnects 130 disclosed herein may take any suitable form. The DTD interconnects 130 may have a finer pitch than the STPS interconnects 150 in a microelectronic assembly. In some embodiments, the dies 114 on either side of a set of DTD interconnects 130 may be unpackaged dies, and/or the DTD interconnects 130 may include small conductive bumps (e.g., copper bumps). The DTD interconnects 130 may have too fine a pitch to couple to the package substrate 102 directly (e.g., too fine to serve as DTS interconnects 140 or STPS interconnects 150). In some embodiments, a set of DTD interconnects 130 may include solder. In some embodiments, a set of DTD interconnects 130 may include an anisotropic conductive material, such as any of the materials discussed above. In some embodiments, the DTD interconnects 130 may be used as data transfer lanes, while the STPS interconnects 150 may be used for power and ground lines, among others. In some embodiments, some or all of the DTD interconnects 130 in a microelectronic assembly 100 may be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or plated interconnects). In such embodiments, the DTD interconnect 130 may be bonded together (e.g., under elevated pressure and/or temperature) without the use of intervening solder or an anisotropic conductive material. Any of the conductive contacts disclosed herein (e.g., the conductive contacts 122, 124, 144, and/or 146) may include bond pads, solder bumps, conductive posts, or any other suitable conductive contact, for example. In some embodiments, some or all of the DTD interconnects 130 and/or the DTS interconnects 140 in a microelectronic assembly 100 may be solder interconnects that include a solder with a higher melting point than a solder included in some or all of the STPS interconnects 150. For example, when the DTD interconnects 130 and the DTS interconnects 140 in a microelectronic assembly 100 are formed before the STPS interconnects 150 are formed, solder-based DTD interconnects 130 and DTS interconnects 140 may use a higher-temperature solder (e.g., with a melting point above 200 degrees Celsius), while the STPS interconnects 150 may use a lower-temperature solder (e.g., with a melting point below 200 degrees Celsius). In some embodiments, a higher-temperature solder may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, a lower-temperature solder may include tin and bismuth (e.g., eutectic tin bismuth) or tin, silver, and bismuth. In some embodiments, a lower-temperature solder may include indium, indium and tin, or gallium.
In the microelectronic assemblies 100 disclosed herein, some or all of the DTS interconnects 140 and the STPS interconnects 150 may have a larger pitch than some or all of the DTD interconnects 130. DTD interconnects 130 may have a smaller pitch than STPS interconnects 150 due to the greater similarity of materials in the different dies 114 on either side of a set of DTD interconnects 130 than between the substrate 107 and the top level dies 114-2, 114-3 on either side of a set of DTS interconnects 140, and between the substrate 107 and the package substrate 102 on either side of a set of STPS interconnects 150. In particular, the differences in the material composition of a substrate 107 and a die 114 or a package substrate 102 may result in differential expansion and contraction due to heat generated during operation (as well as the heat applied during various manufacturing operations). To mitigate damage caused by this differential expansion and contraction (e.g., cracking, solder bridging, etc.), the DTS interconnects 140 and the STPS interconnects 150 may be formed larger and farther apart than DTD interconnects 130, which may experience less thermal stress due to the greater material similarity of the pair of dies 114 on either side of the DTD interconnects. In some embodiments, the DTS interconnects 140 disclosed herein may have a pitch between 25 microns and 250 microns. In some embodiments, the STPS interconnects 150 disclosed herein may have a pitch between 55 microns and 1000 microns, while the DTD interconnects 130 disclosed herein may have a pitch between 25 microns and 100 microns.
The microelectronic assembly 100 of
Although
Many of the elements of the microelectronic assembly 100 of
The glass core 110 may include a cavity 129 with an opening facing the second surface 160-2 and the die 114-1 may be nested, fully or at least partially, in the cavity 129. As shown in
The die 114-1 may be coupled to the dies 114-2, 114-3 in a layer above the die 114-1 through the DTD interconnects 130. The DTD interconnects 130 may be disposed between some of the conductive contacts 122 at the bottom of the dies 114-2, 114-3 and some of the conductive contacts 124 at the top of the die 114-1. Some other conductive contacts 122 at the bottom of the dies 114-2 and/or 114-3 may further couple one or more of the dies 114-2, 114-3 to the glass core 110 by glass core-to-die (GCTD) interconnects 142. The GCTD interconnects 142 may be disposed between some of the conductive contacts 122 at the bottom of the dies 114-2, 114-3 and some of the conductive contacts 128 at the top of the glass core 110. The GCTD interconnects 142 may be similar to the DTS interconnects 140, described above. In some embodiments, the underfill material 127 may extend between different ones of the dies 114 around the associated DTD interconnects 130 and/or GCTD interconnects 142. In some embodiments, a die 114-2 and/or a die 114-3 may be embedded in an insulating material 133. In some embodiments, an overall thickness (e.g., a z-height) of the insulating material 133 may be between 200 microns and 800 microns (e.g., substantially equal to a thickness of die 114-2 or 114-3 and the underfill material 127). In some embodiments, the insulating material 133 may form multiple layers (e.g., a dielectric material formed in multiple layers, as known in the art) and may embed one or more dies 114 in a layer. In some embodiments, the insulating material 133 may be a dielectric material, such as an organic dielectric material, a fire retardant grade 4 material (FR-4), BT resin, polyimide materials, glass reinforced epoxy matrix materials, or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). In some embodiments, the insulating material 133 may be a mold material, such as an organic polymer with inorganic silica particles.
As shown in
The dies 114-2, 114-3 may be electrically coupled to the package substrate 102 through the TGVs 115 and glass core-to-package substrate (GCTPS) interconnects 152, which may be power delivery interconnects or high-speed signal interconnects. The GCTPS interconnects 152 may be similar to the STPS interconnects 150, described above. The top face of the package substrate 102 may include a set of conductive contacts 146, the multi-layer die subassembly 104 may include a set of conductive contacts 126 on the first surface 160-1, and the GCTPS interconnects 152 may be between, and couple the conductive contacts 146 with corresponding ones of the conductive contacts 126. In some embodiments, the underfill material 127 may extend between the glass core 110 and the package substrate 102 around the associated GCTPS interconnects 152.
The glass core 110 included in a microelectronic assembly 100 as described with reference to
After singulation, any of the glass units 186 may serve as a glass core 110. However, as a result of cutting, the surfaces of the glass units 186 along the saw streets 184 (i.e., at least some edges of the glass units 186) may be subject to edge stress and, as a result, may have cracks or fractures, have high surface roughness or jagged edges, or may be otherwise uneven. Furthermore, a glass core 110 may be subject to edge stress and, as a result, cracks may be formed when TGVs are formed in the glass core 110, e.g., when the TGVs 115 as shown in
One or more features utilizing crack-healing materials as described herein may be implemented either before or after the singulation process to alleviate the negative effects of crack formation and propagation in the glass core 110. At a high level, features utilizing crack-healing materials, described herein, may be categorized as features based on providing crack-healing materials on the edges 194 of glass cores 110 (e.g., features illustrated in
Turning to features based on providing crack-healing materials on the edges 194 of glass cores 110 after singulation,
As shown in
In some embodiments, the edge structure 202 may include a crack-healing material that includes carbon, e.g., as a part of an organic monomer, oligomer, or polymer, or as a part of a carbide of an inorganic material such as boron, titanium, or silicon. Formation of a crack at the edge 194 of the glass core 110 may activate the crack-healing material, causing the material to at least partially fill the crack, as illustrated in
The material 208 may be similar to the crack-healing material of the edge structure 202 before activation, but not have exactly the same material composition/structure the activation changes that. Some examples of the crack-healing material of the edge structure 202 and of the material 208 are described below.
In one embodiment, the edge structure 202 may include an organic polymer where carbon may be part of the polymer, and, in some such examples, the polymer may be a relatively low molecular weight polymer, e.g., having a molecular weight below about 50 kilodaltons (kDa). Activation of such polymer may cause it to polymerize further, increasing its molecular weight, so that the material 208 may include polymers having a higher molecular weight than those of the original edge structure 202.
In another embodiment, the edge structure 202 may include an amide, e.g., the edge structure 202 may include monomers or oligomers containing imide groups or may include a polymer containing repeating units of imide groups in the polymer chain. In such an embodiment, before the crack-healing material of the edge structure 202 is activated, the crack-healing material may be in the form of an amide and may include monomers or oligomers containing imide groups, while the material 208 in the cracks 206 may be in the form of a polymer comprising repeating units of the amide (e.g., a polyamide).
In a further embodiment, the edge structure 202 may include a carbonate, e.g., the edge structure 202 may include monomers or oligomers containing carbonate groups or may include a polymer containing repeating units of carbonate groups in the polymer chain). In such an embodiment, before the crack-healing material of the edge structure 202 is activated, the crack-healing material may be in the form of a carbonate and may include monomers or oligomers containing carbonate groups, while the material 208 in the cracks 206 may be in the form of a polymer comprising repeating units of the carbonate (e.g., a polycarbonate).
In yet another embodiment, the edge structure 202 may include a styrene, e.g., the edge structure 202 may include monomers or oligomers containing styrene groups or may include a polymer containing repeating units of styrene groups in the polymer chain. In such an embodiment, before the crack-healing material of the edge structure 202 is activated, the crack-healing material may be in the form of a styrene and may include monomers or oligomers containing styrene groups, while the material 208 in the cracks 206 may be in the form of a polymer comprising repeating units of the styrene (e.g., a polystyrene).
In another example embodiment, the edge structure 202 may include an ethylene, e.g., the edge structure 202 may include monomers or oligomers containing ethylene groups or may include a polymer containing repeating units of ethylene groups in the polymer chain. In such an embodiment, before the crack-healing material of the edge structure 202 is activated, the crack-healing material may be in the form of an ethylene and may include monomers or oligomers containing ethylene groups, while the material 208 in the cracks 206 may be in the form of a polymer comprising repeating units of the ethylene (e.g., a polyethylene).
Embodiments described above are examples of the crack-healing materials of the edge structure 202 that include carbon as a part of an organic monomer, oligomer, or polymer. In further embodiments, the crack-healing materials of the edge structure 202 may include carbon as a part of a carbide of an inorganic material such as boron, titanium, or silicon. In such embodiments, the material 208 in the cracks 206 may include not only carbon but also oxygen, e.g., the material 208 may include a carbonate or an oxidized carbide (e.g., carbonate nitride or carbon oxynitride). In some embodiments, the crack-healing materials of the edge structure 202 may include an inorganic material that includes carbon and a metal (e.g., titanium, aluminum, or vanadium). In such embodiments, the material 208 in the cracks 206 may include not only the metal of the edge structure 202 and carbon but also oxygen, e.g., the material 208 may include a metal carbonate or an oxidized metal carbide. In some embodiments, the crack-healing materials of the edge structure 202 may include an inorganic material that includes carbon and a metalloid (also referred to as a “semimetal,” e.g., boron, silicon, germanium, arsenic, antimony, or tellurium). In such embodiments, the material 208 in the cracks 206 may include not only the metalloid of the edge structure 202 and carbon but also oxygen, e.g., the material 208 may include a metalloid carbonate or an oxidized metalloid carbide.
Edge structures 202 are examples of provided crack-healing materials around the glass core 110 after singulation in order to alleviate the negative effects of crack formation and propagation. In other embodiments, crack-healing materials may be provided in a glass panel 182 before singulation, as illustrated in
Turning to features based on providing crack-healing materials dispersed within the glass cores 110,
Descriptions of the glass panel 182, saw streets 184, and glass units 186 provided with reference to
Formation of a crack at the edge or within a glass core 110 may rupture some of the particles 222, activating the crack-healing material 224 within those particles, and causing the crack-healing material 224 to spill into the crack. An example of this is illustrated in
The activated material 228 may include any of the crack-healing materials described above, e.g., those of the material 208, and, for the sake of brevity, those descriptions are not repeated. Furthermore, in some embodiments, the crack-healing material 224 may include both carbon and boron (e.g., in the form of boron carbide), in which case the activated material 228 may include boron, carbon, and oxygen (e.g., boron carbonate).
As described above, one way to activate the crack-healing materials of the edge structures 202, the openings 212, or the particles 222, may be to expose the crack-healing materials to oxygen, e.g., as a result of crack formation in the glass core 110. When exposed to the open air upon defect formation and, optionally, heated to a certain temperature, the crack-healing materials may form oxides with expanded volumes relative to the unactivated materials, which may be particularly advantageous for filling the volumes of the cracks. For example, some carbides such as silicon carbide may undergo more than 100% in volume expansion upon oxidation. When the crack-healing materials are selected as materials that, when oxidized, transform into materials with relatively low viscosities (e.g., some of the example materials described above), the oxidized materials may easily fill the cracks. When the crack-healing materials are included in the particles 222, additional measures may be implemented to help carefully control activation of these materials, as described with reference to
Various features utilizing crack-healing materials, described above may, advantageously, be easily fabricated in parallel with conventional manufacturing techniques for glass core substrates. Various arrangements of the microelectronic assemblies 100 and glass cores 110 as shown in
The microelectronic assemblies 100 and/or the glass cores 110 disclosed herein, in particular the glass cores 110 with one or more crack-healing materials around and/or in the glass cores 110 as described herein, may be included in any suitable electronic component.
The IC device 1600 may include one or more device layers 1604 disposed on the substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in
Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top face of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top face of the substrate and does not include sidewall portions substantially perpendicular to the top face of the substrate. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1620 may be formed within the substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S/D regions 1620 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 1602 to form the S/D regions 1620. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 1602 may follow the ion-implantation process. In the latter process, the substrate 1602 may first be etched to form recesses at the locations of the S/D regions 1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1620. In some implementations, the S/D regions 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1620 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1620.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., the transistors 1640) of the device layer 1604 through one or more interconnect layers disposed on the device layer 1604 (illustrated in
The interconnect structures 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1628 depicted in
In some embodiments, the interconnect structures 1628 may include lines 1628a and/or vias 1628b filled with an electrically conductive material such as a metal. The lines 1628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 1602 upon which the device layer 1604 is formed. For example, the lines 1628a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 1606, 1608, and 1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in
A first interconnect layer 1606 may be formed above the device layer 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628a and/or vias 1628b, as shown. The lines 1628a of the first interconnect layer 1606 may be coupled with contacts (e.g., the S/D contacts 1624) of the device layer 1604.
A second interconnect layer 1608 may be formed above the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 with the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the lines 1628a and the vias 1628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
A third interconnect layer 1610 (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1619 in the IC device 1600 (i.e., farther away from the device layer 1604) may be thicker.
The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606, 1608, and 1610. In
In some embodiments, the circuit board 1702 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate.
The IC device assembly 1700 illustrated in
The package-on-interposer structure 1736 may include an IC package 1720 coupled to a package interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in
In some embodiments, the package interposer 1704 may be formed as a glass core with one or more crack-healing materials around and/or in the glass core as described herein, e.g., as any embodiment of the glass core 110, described herein. In some embodiments, the package interposer 1704 may be formed as a PCB. In some embodiments, the package interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the package interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. In any of these embodiments, the package interposer 1704 may include multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The package interposer 1704 may include metal lines 1710 and vias 1708, including but not limited to conductive vias 1706. If the package interposer 1704 is a glass core, e.g., the glass core 110 as described herein, then the conductive vias 1706 may be TGVs 115 as described herein. The package interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.
The IC device assembly 1700 illustrated in
Additionally, in various embodiments, the communication device 1800 may not include one or more of the components illustrated in
The communication device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The communication device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic RAM (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin transfer torque magnetic RAM (STT-MRAM).
In some embodiments, the communication device 1800 may include a communication module 1812 (e.g., one or more communication modules). For example, the communication module 1812 may be configured for managing wireless communications for the transfer of data to and from the communication device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication module 1812 may be, or may include, any of the microelectronic assemblies 100 disclosed herein.
The communication module 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication module 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication module 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication module 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication module 1812 may operate in accordance with other wireless protocols in other embodiments. The communication device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions). The antenna 1822 may include one or more microelectronic assemblies 100 and/or one or more glass cores 110 as described herein, e.g., as a part of a microelectronic assembly 100 as described herein.
In some embodiments, the communication module 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication module 1812 may include multiple communication modules. For instance, a first communication module 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication module 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication module 1812 may be dedicated to wireless communications, and a second communication module 1812 may be dedicated to wired communications. In some embodiments, the communication module 1812 may support millimeter wave communication.
The communication device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the communication device 1800 to an energy source separate from the communication device 1800 (e.g., AC line power).
The communication device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The communication device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The communication device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The communication device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the communication device 1800, as known in the art.
The communication device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The communication device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The communication device 1800 may have any desired form factor, such as a handheld or mobile communication device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop communication device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable communication device. In some embodiments, the communication device 1800 may be any other electronic device that processes data.
The following paragraphs provide examples of various ones of the embodiments disclosed herein.
Example 1 provides a microelectronic assembly that includes a glass core (e.g., a layer of glass including a rectangular prism volume) having a first face, a second face opposite the first face, and an edge between an end of the first face and an end of the second face; and an edge structure on the edge of the glass core, the edge structure including carbon.
Example 2 provides the microelectronic assembly according to example 1, where the edge structure includes a polymer where carbon may be part of an organic polymer.
Example 3 provides the microelectronic assembly according to example 2, where a molecular weight of the polymer is below about 50 kilodaltons.
Example 4 provides the microelectronic assembly according to any one of the preceding examples, where the edge structure includes an amide.
Example 5 provides the microelectronic assembly according to example 4, where the amide in the edge structure is a part of a monomer or an oligomer in the edge structure, and where the glass core further includes a crack starting at the edge, where the crack is at least partially filled with a polymer including repeating units of the amide.
Example 6 provides the microelectronic assembly according to any one of the preceding examples, where the edge structure includes a carbonate (e.g., the edge structure may include monomers or oligomers containing carbonate groups or may include a polymer containing repeating units of carbonate groups in the polymer chain).
Example 7 provides the microelectronic assembly according to example 6, where the carbonate in the edge structure is a part of a monomer or an oligomer in the edge structure, and where the glass core further includes a crack starting at the edge, where the crack is at least partially filled with a polymer including repeating units of the carbonate.
Example 8 provides the microelectronic assembly according to any one of the preceding examples, where the edge structure includes a styrene (e.g., the edge structure may include monomers or oligomers containing styrene groups or may include a polymer containing repeating units of styrene groups in the polymer chain).
Example 9 provides the microelectronic assembly according to example 8, where the styrene in the edge structure is a part of a monomer or an oligomer in the edge structure, and where the glass core further includes a crack starting at the edge, where the crack is at least partially filled with a polymer including repeating units of the styrene.
Example 10 provides the microelectronic assembly according to any one of the preceding examples, where the edge structure includes an ethylene (e.g., the edge structure may include monomers or oligomers containing ethylene groups or may include a polymer containing repeating units of ethylene groups in the polymer chain).
Example 11 provides the microelectronic assembly according to example 10, where the ethylene in the edge structure is a part of a monomer or an oligomer in the edge structure, and where the glass core further includes a crack starting at the edge, where the crack is at least partially filled with a polymer including repeating units of the ethylene.
Example 12 provides the microelectronic assembly according to any one of the preceding examples, where the edge structure includes a carbide.
Example 13 provides the microelectronic assembly according to example 12, where the glass core further includes a crack starting at the edge, where the crack includes carbon and oxygen (e.g., the crack is at least partially filled with a carbonate or an oxidized carbide such as carbonate nitride).
Example 14 provides the microelectronic assembly according to any one of the preceding examples, where the edge structure includes an inorganic material, carbon is part of the inorganic material, and the inorganic material further includes a metal (e.g., titanium, aluminum, or vanadium).
Example 15 provides the microelectronic assembly according to example 14, where the glass core further includes a crack starting at the edge, where the crack includes the metal, carbon, and oxygen (e.g., the crack is at least partially filled with a metal carbonate or oxidized metal carbide).
Example 16 provides the microelectronic assembly according to any one of the preceding examples, where the edge structure includes an inorganic material, carbon is part of the inorganic material, and the inorganic material further includes a metalloid (also referred to as a semimetal; e.g., boron, silicon, germanium, arsenic, antimony, or tellurium).
Example 17 provides the microelectronic assembly according to example 16, where the glass core further includes a crack starting at the edge, where the crack includes the metalloid, carbon, and oxygen (e.g., the crack is at least partially filled with a metalloid carbonate or oxidized metalloid carbide).
Example 18 provides the microelectronic assembly according to any one of the preceding examples, where: the edge structure is part of a clamp structure around the edge of the glass core, the clamp structure has a first portion at the first face, a second portion at the second face, and a third portion on the edge, where the third portion is attached to the first portion and the second portion.
Example 19 provides the microelectronic assembly according to example 18, where the third portion is materially continuous with the first portion and the second portion.
Example 20 provides the microelectronic assembly according to examples 18 or 19, where the first portion extends over the first face to a distance from the edge that is less than about 10% (e.g., less than about 5% or less than about 1%) of a width of the glass core.
Example 21 provides the microelectronic assembly according to any one of examples 18-20, where the clamp structure extends along at least 50% of a length of the edge.
Example 22 provides the microelectronic assembly according to any one of examples 18-21, where the clamp structure extends along an entire length of the edge.
Example 23 provides the microelectronic assembly according to any one of examples 18-22, where: the clamp structure is one of a plurality of clamp structures, the edge is one of a plurality of edges of the glass core, the clamp structures are connected in a ring along the plurality of edges of the glass core.
Example 24 provides the microelectronic assembly according to any one of examples 18-22, where the clamp structure is one of a plurality of clamp structures around the edge.
Example 25 provides the microelectronic assembly according to example 24, where the clam structures of the plurality of clamp structures are materially discontinuous from one another.
Example 26 provides the microelectronic assembly according to any one of the preceding examples, where: the microelectronic assembly includes a glass panel including a plurality of glass cores, and the glass core is one of the plurality of glass cores.
Example 27 provides a microelectronic assembly that includes a glass panel including a first glass core, a second glass core, and a saw street between the first glass core and the second glass core, where: the glass panel has a first face, a second face opposite the first face, and a plurality of openings along the saw street, and an individual opening of the plurality of openings is an opening extending from the first face towards the second face of the glass core and including a polymer (e.g., an organic polymer) or an inorganic material including carbon or boron.
Example 28 provides the microelectronic assembly according to example 27, where the opening is a via.
Example 29 provides the microelectronic assembly according to example 27, where the opening is a trench.
Example 30 provides the microelectronic assembly according to any one of examples 27-29, where either the opening reaches the second face, or the opening is a blind opening that does not reach the second face. In various embodiments, the polymer may include any materials of the edge structure according to any one of examples 2-11 and/or the inorganic material including carbon may include any materials of the edge structure according to any one of examples 12-17.
Example 31 provides a microelectronic assembly that includes a glass core (e.g., a layer of glass including a rectangular prism volume) having a first face and a second face opposite the first face; and particles including an inorganic material dispersed in the glass core, between the first face and the second face of the glass core, where the inorganic material includes carbon or boron, and where a volume occupied by the particles is between about 5% and about 55% of a volume of the glass core.
Example 32 provides the microelectronic assembly according to example 31, where the inorganic material includes a carbide.
Example 33 provides the microelectronic assembly according to example 32, where the glass core further includes a crack including a carbonate.
Example 34 provides the microelectronic assembly according to any one of examples 31-33, where the inorganic material includes carbon and further includes a metal (e.g., titanium, aluminum, or vanadium).
Example 35 provides the microelectronic assembly according to example 34, where the glass core further includes a crack, and where the crack includes the metal, carbon, and oxygen (e.g., the crack is at least partially filled with a metal carbonate or oxidized metal carbide).
Example 36 provides the microelectronic assembly according to any one of examples 31-35, where the inorganic material includes carbon and further includes a metalloid (also referred to as a semimetal; e.g., boron, silicon, germanium, arsenic, antimony, or tellurium).
Example 37 provides the microelectronic assembly according to example 36, where the glass core further includes a crack, and where the crack includes the metalloid, carbon, and oxygen (e.g., the crack is at least partially filled with a metalloid carbonate or oxidized metalloid carbide).
Example 38 provides the microelectronic assembly according to example 31, where the inorganic material includes both carbon and boron.
Example 39 provides the microelectronic assembly according to example 38, where the glass core further includes a crack including boron, carbon, and oxygen (e.g., boron carbonate).
Example 40 provides the microelectronic assembly according to any one of examples 31-39, where the inorganic material includes a boride.
Example 41 provides the microelectronic assembly according to any one of examples 31-40, where the inorganic material includes boron and further includes a metal (e.g., titanium, aluminum, or vanadium).
Example 42 provides the microelectronic assembly according to any one of examples 31-41, where an average dimension across centers of particles (e.g., a diameter) is between about 5 nanometers and about 10 micron.
Example 43 provides the microelectronic assembly according to any one of examples 31-42, where the particles are at least partially enclosed by a layer including a high-density polymer, e.g., a polymer having a molecular weight from about 0.5 kilodalton (kDa) to about 200 kDa (e.g., polystyrene, alkylene, imide, or vinyl pyrrolidone).
Example 44 provides the microelectronic assembly according to any one of examples 31-43, where the particles are at least partially enclosed by a layer including polystyrene, alkylene, imide, or vinyl pyrrolidone.
Example 45 provides the microelectronic assembly according to any one of examples 31-42, where the particles are at least partially enclosed by a layer including nitrogen.
Example 46 provides the microelectronic assembly according to example 45, where the layer further includes a metal (e.g., aluminum) or a metalloid (e.g., silicon).
Example 47 provides the microelectronic assembly according to examples 45 or 46, where the layer further includes aluminum or silicon.
Example 48 provides the microelectronic assembly according to any one of examples 31-42, where the particles are at least partially enclosed by a layer including silicon and carbon.
Example 49 provides the microelectronic assembly according to any one of examples 43-48, where a thickness of the layer is less than about 250 nanometers, e.g., less than about 50 nanometers or less than about 10 nanometers.
Example 50 provides the microelectronic assembly according to any one of examples 31-49, where: the particles are first particles, the microelectronic assembly further includes second particles including one or more of ruthenium, platinum, vanadium, palladium, cobalt, titanium, or nickel.
Example 51 provides the microelectronic assembly according to example 50, where a volume occupied by the second particles is between about 0.5% and about 30% of the volume of the glass core.
Example 52 provides the microelectronic assembly according to any one of the preceding examples, where a cross-section of the glass core in a plane perpendicular to a surface of the component is substantially rectangular.
Example 53 provides the microelectronic assembly according to any one of the preceding examples, where a cross-section of the glass core in a plane parallel to a surface of the component is substantially rectangular.
Example 54 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including at least 23% silicon by weight.
Example 55 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including at least 26% oxygen by weight.
Example 56 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including at least 23% silicon by weight and at least 26% oxygen by weight.
Example 57 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including at least 5% aluminum by weight.
Example 58 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass that does not include an organic adhesive or an organic material.
Example 59 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass having a thickness in a range of 50 micron (um) to 1.4 millimeters (mm), a first length in a range of 10 mm to 250 mm, and a second length in a range of 10 mm to 250 mm, the first length perpendicular to the second length.
Example 60 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass having a thickness in a range of 50 μm to 1.4 mm.
Example 61 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass having a first length in a range of 10 mm to 250 mm, and a second length in a range of 10 mm to 250 mm, the first length perpendicular to the second length.
Example 62 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including a rectangular prism volume.
Example 63 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including a rectangular prism volume having a first side and a second side perpendicular to the first side, the first side having a length in a range of 10 mm to 250 mm and the second side having a length in a range of 10 mm to 250 mm.
Example 64 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including a rectangular prism volume and a via extending from a first side of the rectangular prism volume to a second side of the rectangular prism volume, the via including a metal.
Example 65 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a solid layer of glass.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.
