Patent Application
20240383745
The present invention relates to a micromechanical component. The present invention also relates to a method for producing a micromechanical component.
In the related art, it is conventional to separate wiring levels in a layer system from one another by electrical insulation layers.
It is an object of the present invention to provide an improved micromechanical component.
According to a first aspect of the present invention, the object may be achieved with a micromechanical component comprising:
In this way, electrical conductive paths, which are provided for an electrical connection to electrical parts and/or electrical components, such as electrodes, in a cavern region, can, for example, be guided below the etch stop layer. Advantageously, for example, slight etching of electrical insulation layers along conductive paths from the cavern region can thereby be avoided, or slight etching of electrical insulation layers of sacrificial layer material along conductive paths below the etch stop layer can thereby be avoided during the necessary etching of sacrificial layers of oxide material in a cavern region.
According to a second aspect of the present invention, the object may be achieved by a method for producing a micromechanical component, comprising the steps of:
Preferred embodiments and developments of the micromechanical component are disclosed herein.
In an advantageous development of the micromechanical component of the present invention, the further wiring level is used to electrically contact electrical parts and/or electrical components in a cavern region. Versatile usability of the further wiring level is thereby advantageously supported.
In a further advantageous development of the micromechanical component of the present invention, at least one element of the further wiring level is arranged in a lateral etch channel. In this way, a parasitic capacitance of a conductive path of the further wiring level can advantageously be reduced, for example.
By means of the lateral etch channel, it is, for example, advantageously not necessary to provide an etch channel in a membrane in order to remove sacrificial layer material from a cavern region.
In a further advantageous development of the micromechanical component of the present invention, at least one element of the further wiring level is formed directly on a bottom side of the etch stop layer or at a distance from the etch stop layer in a self-supporting manner in a lateral etch channel.
Advantageously, various realizations of the further wiring level are thereby provided. For example, a conductive path of the further wiring level is held only by electrical contact structures, whereby a parasitic stray capacitance between the conductive path and a functional layer system arranged thereabove can be reduced.
In a further advantageous development of the micromechanical component of the present invention, a reference capacitance is formed by means of the further wiring level in combination with the etch stop layer. The reference capacitance provided thereby can advantageously be used for functionalities of the micromechanical component.
In a further advantageous development of the micromechanical component of the present invention, the further wiring level forms a reference capacitance in combination with a partially removed etch stop layer. In this way, a further alternative for providing a reference capacitance is provided by means of the further wiring level.
In a further advantageous development of the micromechanical component of the present invention, the further wiring level is formed at least partially in a planar manner within a lateral etch channel. By means of the planar further wiring level, an even better formation of a defined reference capacitance is advantageously supported.
In further advantageous developments of the micromechanical component of the present invention, the reference capacitance is arranged in an anchoring region of a cavern region and/or outside of the cavern region and/or within the cavern region. In this way, a variety of possible circuitries for using the reference capacitance formed by means of the further wiring level result for the micromechanical component.
In further advantageous developments of the micromechanical component of the present invention, the wiring level extends into a region below the cavern region. In this way, a reference capacitance produced in a defined manner can advantageously be produced from a combination of the counter electrode, the additional wiring level and the etch stop layer, wherein conductive paths for the electrical connection of the reference capacitance can also be realized by means of the wiring level.
In an advantageous development of the micromechanical component of the present invention, a thickness of the etch stop layer is formed in a defined manner in the region of the reference capacitances. In this way, the etch stop layer can be formed locally thinner or thicker as needed, whereby a size of the reference capacitance can advantageously be dimensioned.
In a further advantageous developments of the micromechanical component of the present invention, the micromechanical component is a capacitive pressure sensor and/or an acceleration sensor and/or a rotation rate sensor. Using the proposed further wiring level below the etch stop layer results in a plurality of advantageous embodiments/wiring options for the micromechanical component.
In an advantageous development of the provided method of the present invention, that depressions in the surface of the at least one first oxide layer are used by means of a CMP process to form, for example, conductive paths of the further wiring level on the top side of the at least one first oxide layer, which conductive paths are electrically insulated from one another and which, together with the at least one first oxide layer, form a flat surface.
In an advantageous development of the provided method of the present invention, the further wiring level is deposited directly on the first oxide layer, then structured, and a further oxide layer is deposited over it, wherein the further wiring level is exposed superficially by means of a planarization step.
Advantageously, no additional work for forming the further wiring level is incurred thereby. As a result, standard process sequences can advantageously be used largely unchanged to produce the proposed micromechanical component.
The present invention is described in detail below with further features and advantages with reference to a plurality of figures. Identical or functionally identical elements have the same reference signs. The figures are in particular intended to illustrate the principles essential to the present invention and are not necessarily to scale. For better clarity, it may be Substitute Specification provided that not all of the reference signs are shown in all of the figures.
Conventionally, during a SiO2 sacrificial layer process, etching or slight etching of SiO2 can occur in the region or along electrical conductive paths which are guided out of the cavern region. Since they must be guided, electrically insulated, e.g., with SiO2, within the functional layer system, e.g., in the first poly-Si layer/level, through the lateral etch boundaries of the cavern region, e.g., of poly-Si, lateral paths are produced here along conductive paths along which an etch attack on SiO2 insulation layers can also take place during the removal of oxide sacrificial layers. The length along which SiO2 layers are removed around conductive paths is in this case dependent on the etching duration of the sacrificial layer etching process and the position of the etch channels or etch accesses in relation to conductive path passages in lateral etch boundaries of the cavern region. The closer the etch accesses and conductive path passages are to one another and the longer the sacrificial layer etching process takes, the longer slight SiO2 etchings along electrical conductive paths may be.
In principle, the insulation layers and the lateral etch boundaries of the cavern region could consist of an electrically insulating material (e.g., silicon-rich silicon nitride, SiRiN) that is etch-resistant to, for example, HF (hydrofluoric acid) in liquid or gaseous form. However, this would disadvantageously mean additional costs and more complex processing of the functional layer region.
A core concept of the present invention consists in particular in providing a further electrical wiring level, for example of doped poly-Si, which can reach into a cavern region and whose surrounding electrical insulation cannot be etch-attacked or removed during the removal of sacrificial layers from a cavern region of the component, directly on a bottom side or below a passivation or etch stop layer in a micromechanical component (e.g., an inertial sensor, a pressure sensor, a microphone, a rotation rate sensor, etc.).
In contrast, providing a further electrical wiring level under a passivation layer which is etch-resistant to a medium with which sacrificial layers are removed from a cavern region has the advantage that electrical rewirings, which allow a more complex electrical wiring of the sensor, can also be formed within the cavern region, without the electrical insulation of the further wiring level under the passivation layer being undesirably attacked or even completely removed during the sacrificial layer etching process. In this way, design and process engineering continues to support that parasitic capacitances, created by the further wiring level, to the silicon substrate can be kept small or even eliminated.
Since the etch stop layer 3 is, for example, etch-resistant to an etching medium (e.g., HF vapor), forming a further wiring level 10 of the functional layer system from, for example, doped poly-Si directly on a bottom side of the etch stop layer 3 can avoid that, during removal of, for example, a second oxide layer 5 of, for example, SiO2 and/or a third oxide layer 7 of, for example, SiO2 from a cavern region 9, underetchings of poly-Si conductive paths in the first functional layer 4 occur and said poly-Si conductive paths lose their adhesion to the underlying surface, and etching or slight etching of electrical insulation layers of, for example, SiO2 occurs in the region of or along poly-Si conductive paths which are guided out of the cavern region 9.
Furthermore, the etch stop layer 3 protects the substructure with the at least one first oxide layer 2 of, for example, SiO2 in the cavern region 9 from an etch attack by, for example, HF vapor. In this way, underetchings in the substructure of sensor components within the cavern region 9 can advantageously be avoided by providing an etch stop layer 3.
Ultimately, the proposed micromechanical component 100 of
The production of the proposed further wiring level 10 can be carried out by means of convention semiconductor technology methods, as indicated in
Subsequently, the full-surface deposition of a further poly-Si layer takes place directly on the structured surface of the at least one first oxide layer 2 and then a CMP (chemical mechanical polishing) process takes place, by means of which the further poly-Si is removed from the surface of the first oxide layer 2 such that the further poly-Si remains only in depressions of the first oxide layer, as indicated in
Alternatively, it is also conceivable to first deposit the at least one first oxide layer 2, to arrange the further wiring level 10 directly thereon, to completely cover said further wiring level with an additional oxide layer 2a and to planarize the surface by means of a CMP process. During planarization, the additional oxide layer 2a is removed such that the structures of the further wiring level 10 are exposed superficially, as indicated in
In both variants, the thickness of the first oxide layer 2 below the further wiring level 10 is smaller than the thickness of the oxide layer surrounding it. This can result in greater parasitic capacitances Cp toward the substrate 1 in the region of the further wiring level 10 than in other electrically conductive structures of the rest of the functional layer system of the micromechanical component 100.
In order to be able to minimize the parasitic capacitances Cp to the substrate 1, which capacitances are created during the addition of the further wiring level 10, the production of the further wiring level 10 can be carried out as follows:
Before producing or depositing the first oxide layer 2, structures that correspond to structures in the further wiring level 10 are etched into the substrate 1 by means of a mask level. Directly onto the thus prepared surface of the substrate 1, the first oxide layer 2 is subsequently deposited, in the surface of which depressions 10a corresponding to the substrate surface form, as indicated in
If a further doped poly-Si layer is now deposited directly onto the at least one first oxide layer 2 and the surface is planarized by means of a CMP process such that the further doped poly-Si layer on the at least one first oxide layer 2 is removed superficially and poly-Si is retained only in depressions of the first oxide layer 2, electrically conductive silicon regions that are electrically insulated from one another by the at least one first oxide layer 2 can thus be produced. In this way, it can be achieved that the thickness of the at least one first oxide layer 2 under the structures (e.g., conductive path) of the further wiring level 10 can be equal to or even greater than the thickness of the at least one first oxide layer 2 surrounding it. In this way, it can be achieved that parasitic capacitances Cp between structures of the further wiring level 10 and the substrate 1 can be comparable or even smaller than between electrically conductive structures of the functional layer system and the substrate 1, as shown in
Alternatively, it is also conceivable to create further recesses 13a in the oxide layer 2 or, alternatively, in the oxide layer 2 and the oxide layer 2a after planarizing the surface and immediately before depositing the etch stop layer 3. During the deposition of the etch stop layer 3 of, for example, SiRiN, the further recesses 13a are filled up with material of the etch stop layer 3 and can in this way be used to produce electrically insulating lateral etch stop boundaries.
As shown in
If a layer of poly-Si is then deposited, the structures 13 in the at least one first oxide layer 2 can be used to realize lateral etch stop structures and/or to electrically contact the substrate 1, and the recessed structures of the further wiring level 10 in the first oxide layer 2 can be filled up with silicon. If a polishing step is then carried out and the poly-Si layer is removed superficially on the at least one second oxide layer 2, a planar surface on which the mentioned Si structures are freely accessible and are separated from one another by material of the at least one first oxide layer 2 is obtained. In the variant in which no depressions for the further wiring level 10 are created in the at least one first oxide layer 2, after producing the at least one first oxide layer 2, lateral etch stop structures 13a and/or structures for electrically contacting the substrate 1 are first created in the at least one first oxide layer 2 and filled in with doped poly-Si.
The poly-Si on the surface of the at least one first oxide layer 2 can now be removed by means of a CMP method in order to subsequently be able to produce the further wiring level 10 on the planar surface thus obtained, as already described above. Optionally, however, the poly-Si can also remain on the surface of the at least one first oxide layer 2 and can be used to realize the structures for the further wiring level 10. The structures of the further wiring level 10 are then covered with an additional oxide layer 2a and exposed superficially again by means of a CMP method.
In all variants described, the deposition and structuring of the electrical insulation and etch stop layer 3 of, for example, SiRiN would now be carried out. In so doing, contact hole structures are formed by the electrical insulation and etch stop layer 3, which contact hole structures are needed for the later contacting of the further wiring level 10 and/or the contact structures 13 by the at least one first oxide layer 2 to the substrate 1, as indicated in
In addition, openings can be formed in the etch stop layer 3, which openings serve for the targeted conduction of an etching medium from the top side of the functional layer system into a lateral etch channel 12a . . . 12n and from there into the cavern region 9.
In this case, it is also possible to integrate one or more conductive paths of the further wiring level 10 within a lateral etch channel 12a . . . 12n originating from a vertical etch channel 11. By removing the at least one first oxide layer 2 between the conductive paths and the substrate 1, parasitic capacitances Cp can be reduced, and regions to be provided separately for guiding conductive paths out of the cavern region 9 can be saved, as shown in
In order to be able to reduce parasitic capacitances Cp between the further wiring level 10 and the first functional layer 4 of the functional layer system of, for example, doped poly-Si, an additional fourth oxide layer 14 (e.g., SiO2) can be inserted after carrying out the CMP step for producing the further wiring level 10 and before depositing the etch stop layer 3. By means of this additional fourth oxide layer 14, the distance between the further wiring level 10 and the first functional layer 4 of the functional layer system can be increased, and parasitic capacitances Cp can be reduced.
If thus buried conductive paths of the further wiring level 10 are integrated into lateral etch channels 12a . . . 12n in the substructure of the sensor element, after removing the oxide layers 2, 14 in the lateral etch channels 12a . . . 12n in the wiring level 10, released or self-supporting conductive path structures of the further wiring level 10 are produced, which advantageously can have even lower parasitic capacitances Cp between the further wiring level 10 and the functional layer system, as indicated in
While, as explained above, parasitic capacitances between conductive paths of the further wiring level 10 and the substrate 1 and/or electrically conductive layers/conductive paths of the functional layer system can be adapted or minimized, the further wiring level 10 can also be used to, for example, produce reference capacitances Cr in a targeted manner. For example, starting from the arrangement shown in
In a further variant, it is also conceivable to also form one or more reference capacitances Cr1 . . . Crn below the counter electrode region, wherein the counter electrode can in this case serve both as an electrode for the useful capacitance and as an electrode for a reference capacitor structure. In this way, the reference capacitances Cr1 . . . Crn can be provided below the counter electrode, as indicated in the cross-sectional view of
In
Furthermore, by providing a thicker etch stop layer 3 and/or a further dielectric layer, e.g., in the form of a fourth oxide layer 14 between the electrode surface in the further wiring level 10 and the etch stop layer 3, a smaller reference capacitance Cr can be created, as indicated in principle in
Optionally, it is also conceivable that the dielectric of the reference capacitance Cr that is used in this case is formed from other electrically insulating layers of the functional layer system.
In
The basic production process for implementing reference capacitances Cr under a counter electrode structure is, in principle, as follows:
First, in an SiO2 layer, substrate contact and conductive path structures are created, filled up or filled in with poly-Si and optionally electrically separated from one another by means of a CMP step, for example. In this way, a planar wafer surface is obtained, onto which the further layers of the micromechanical component 100 can be deposited. Next, the deposition and structuring of the insulation or etch stop layer 3 follows, followed by the deposition and structuring of the first functional layer 4 for producing the counter electrode structure.
Subsequently, the first sacrificial oxide layer is deposited and structured, the movable electrode is created by depositing and structuring a poly-Si layer, a further second sacrificial oxide layer is deposited and structured, and finally the membrane layer is produced by depositing and structuring a poly-Si layer.
As an alternative to what was explained above, reference capacitances Cr can also be provided in a targeted manner in lateral etch channel structures 12a . . . 12n, as indicated in
In principle, a plurality of reference capacitances Cr1 . . . Crn can also be realized in this way at any locations outside of and/or within the cavern region 9 and/or in the region of the membrane clamping or the anchoring region of the membrane.
The proposed micromechanical component 100 produced by means of the proposed method can, for example, be a capacitive pressure sensor, as explained above. Other forms of realization (not shown in figures) of the proposed micromechanical component 100, such as a microphone, piezoresistive pressure sensor, acceleration sensor, rotation rate sensor, etc., are also conceivable.
In a step 200, a substrate 1 is provided.
In a step 210, a first oxide layer 2 is provided on the substrate 1.
In a step 220, a wiring level is provided on the surface of the first oxide layer 2 that faces away from the substrate.
In a step 230, a flat surface is provided from regions of the wiring level and regions of the first oxide layer and/or a further oxide layer.
In a step 240, an etch stop layer is provided on the flat surface from regions of the wiring level and regions of the first oxide layer and/or a further oxide layer.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2021 210 383.9 | Sep 2021 | DE | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2022/072246 | 8/8/2022 | WO |
