The present disclosure relates to a module and a method of manufacturing the same.
WO2006/027888 (PTL 1) describes obtaining a ceramic multilayer substrate by layering ceramic green sheets each having an interconnection pattern layer formed thereon and performing such treatment as press-bonding, binder removal treatment, firing, and the like. PTL 1 describes forming a film of Ni/Sn or Ni/Au on an electrode on the ceramic multilayer substrate with wet plating.
A land electrode and an interconnection for connecting land electrodes may be provided as an electrode on a ceramic multilayer substrate. Similar to the land electrode, the interconnection may also be provided on an outer surface. In this case, the land electrode and the interconnection can be formed from an integrated conductor pattern. A component is normally mounted on a land electrode with solder being interposed. Since a heating step is performed for reflow after the component is placed with solder being interposed, solder becomes fluid. In an example in which the land electrode and the interconnection are integrally formed on the outer surface of the ceramic multilayer substrate, a phenomenon may occur wherein fluid solder comes in contact with a material for the interconnection and is alloyed therewith, which results in flow of solder away from a position where it should properly be located.
When solder flows away, a component to be mounted may disadvantageously be displaced from a proper position due to flow of solder. In addition, “solder dissolution” may occur wherein a material for an interconnection is taken away due to alloying of solder with the material for the interconnection.
An object of the present disclosure is to provide a module in which solder is prevented from coming in contact with a material for an interconnection and being alloyed therewith at the time of mounting a component.
In order to achieve the object, a module based on the present disclosure includes a ceramic multilayer substrate including a main surface; a surface-layer conductor pattern arranged on the main surface and integrally formed to include a land portion and an interconnection portion extending from the land portion; a first layer arranged to cover the land portion while exposing at least a part of the interconnection portion, the first layer having conductivity, the first layer being composed of a material that is lower in affinity to solder than a material for the surface-layer conductor pattern; and a component mounted on the first layer with the solder being interposed. The solder is not in direct contact with the surface-layer conductor pattern.
Since solder is not in direct contact with the surface-layer conductor pattern, solder can be prevented from flowing to the interconnection portion at the time of mounting the component. Therefore, a module in which solder is prevented from coming in contact with a material for an interconnection and being alloyed therewith can be realized.
A dimensional ratio shown in the drawings does not necessarily faithfully represent an actual dimensional ratio and a dimensional ratio may be exaggerated for the sake of convenience of description. The terms up or upper or down or lower mentioned in the description below do not mean absolute up or upper or down or lower but may mean relative up or upper or down or lower in terms of a shown position.
A module 101 will be described with reference to
The module 101 includes a ceramic multilayer substrate 1 including a main surface 1u; a surface-layer conductor pattern 6 arranged on the main surface 1u and integrally formed to include a land portion 11 and an interconnection portion 12 extending from the land portion 11; a first layer 8; and a component 3. The first layer 8 is arranged to cover the land portion 11 while exposing at least a part of the interconnection portion 12. The first layer 8 has conductivity and includes a material that is lower in affinity (i.e., attraction) to the solder 4 than a material for the surface-layer conductor pattern 6. In other words, the material for the first layer 8 is relatively lower in affinity to the solder 4, while the material for the surface-layer conductor pattern 6 is relatively higher in affinity to the solder 4.
The component 3 is mounted with the solder 4 being interposed so as to electrically be connected to the first layer 8. The solder 4 is not in direct contact with the surface-layer conductor pattern 6. The component 3 “being mounted on the first layer 8 with the solder 4 being interposed” means a construction in which only the solder 4 is present between the component 3 and the first layer 8. Without being limited as such, a layer composed of a material other than the solder 4 may be interposed.
Though a ceramic multilayer substrate is employed as the substrate in the present embodiment, a single-layer substrate instead of the multilayer substrate may be employed. The substrate may be a resin substrate. When the resin substrate is employed, it may be a multilayer substrate or a single-layer substrate.
The surface-layer conductor pattern 6 is, for example, mainly composed of copper. The surface-layer conductor pattern 6 is in a two-dimensional shape, for example, as shown in
The component 3 is sealed with the molding resin 5, which is formed to cover the main surface 1u. Though
In the present embodiment, the first layer 8 is arranged to cover the land portion 11 of the surface-layer conductor pattern 6, and the solder 4 is not in direct contact with the surface-layer conductor pattern 6. Therefore, the solder 4 can be prevented from flowing to the interconnection portion 12 when mounting the component 3, and displacement of the component 3 can be suppressed. In addition, contact of the solder 4 with the material for the interconnection portion 12 and resultant alloying thereof can be avoided.
The solder 4 is preferably not in direct contact with the surface-layer conductor pattern 6 around the entire perimeter of the land portion 11. Preferably, around the perimeter of the land portion 11, the solder 4 is not in direct contact with the surface-layer conductor pattern 6, in particular on a side where the interconnection portion 12 extends.
As shown in the present embodiment, preferably, the molding resin 5 with which at least the component 3 is sealed is provided. Along the interconnection portion 12, the molding resin 5 covers the surface-layer conductor pattern 6 and is in direct contact with the surface-layer conductor pattern 6.
As shown in the present embodiment, preferably, the surface-layer conductor pattern 6 is mainly composed of copper. By adopting this construction, a surface interconnection low in electrical resistance value can be realized.
As shown in the present embodiment, the first layer 8 is preferably mainly composed of nickel. By adopting this construction, the solder 4 can be prevented from flowing to a portion where copper is exposed.
The first layer 8 has a lower end in contact with the land portion 11 and an upper end in contact with the solder 4. Preferably, the upper end projects toward interconnection portion 12 relative to the lower end. By adopting this construction, the solder 4 can efficiently be prevented from flowing away to the interconnection portion 12.
A method of manufacturing the module 101 will be described with reference to
The method of manufacturing the module 101 includes a step S1 of preparing a substrate including a surface-layer conductor pattern integrally formed to include a land portion and an interconnection portion extending from the land portion on a main surface which is an outermost surface, a step S2 of forming a resist film to cover the interconnection portion without covering the land portion, a step S3 of plating growth of a first layer including a material that is lower in affinity to solder than a material for the surface-layer conductor pattern on a surface of the land portion, a step S4 of growing a second layer including a material that is higher in affinity to solder than the material for the first layer on a surface of the first layer, a step S5 of removing the resist film, a step S6 of arranging a solder paste on the second layer, and a step S7 of placing a component on the solder paste and then performing heating. In the example shown here, the method further includes a step S8 of forming a molding resin to seal at least the component. Each step will be described in further detail below with reference to the drawings.
Initially, in the step S1, as shown in
Then, in step S2, a resist film 15 is formed as shown in
A central portion of interconnection portion 12 is covered with the resist film 15. A portion of the interconnection portion 12 connected to the land portion 11 on the left in
In step S3, as shown in
In step S4, as shown in
In step S5, the resist film 15 is removed. The resist film 15 can be removed by a strong alkali solution. For example, an NaOH solution may be adopted as the strong alkali solution. By performing step S5, a structure shown in
In step S6, as shown in
In step S8, the molding resin 5 is formed to seal at least the component 3. The module 101 shown in
In the present embodiment, the resist film 15 is formed in step S2, and thereafter steps S3 and S4 are performed to form the first layer 8 and second layer 9. Thereafter, the resist film 15 is removed in step S5. Therefore, the second layer 9 can be spaced apart from the interconnection portion 12. Thereafter, the component 3 is mounted by performing steps S6 and S7. Therefore, the module 101 can be manufactured while solder is not in direct contact with the interconnection portion 12. The module in which solder is prevented from coming in contact with the material for the interconnection portion 12 and being alloyed therewith can thus be obtained.
The step S2 of forming the resist film 15 is preferably performed by the ink-jet method. By adopting this method, the resist film 15 can be formed in a desired region with high precision.
Although the surface-layer conductor pattern 6 as shown in
Some features in embodiments above may be adopted as being combined as appropriate.
It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present disclosure is defined by the terms of the claims and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
Number | Date | Country | Kind |
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2018-229177 | Dec 2018 | JP | national |
This is a continuation of International Application No. PCT/JP2019/046180 filed on Nov. 26, 2019 which claims priority from Japanese Patent Application No. 2018-229177 filed on Dec. 6, 2018. The contents of these applications are incorporated herein by reference in their entireties.
Number | Date | Country | |
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Parent | PCT/JP2019/046180 | Nov 2019 | US |
Child | 17336470 | US |