The disclosure relates to a circuit board, particularly to a multi-layer printed circuit board which may reduce the cooling speed of a pad to improve the soldering efficiency.
With the advance of printed circuit boards (PCB) and the manufacturing process of electronic components, the design of PCBs also progressively tends to high speed and compactness to satisfy the requirements of high performance and lightweight of electronic products. To reduce the size of a PCB, a layout design of multi-layer PCB is proposed to add the wiring area.
Generally speaking, to avoid the crosstalk interference between high-speed signals, a multi-layer PCB is usually disposed with via holes to isolate signals to reduce the influence. However, holing a pad may make the cooling speed of the pad excessively fast to cause an insufficient soldering temperature in the subsequent soldering process, so as to affect the processing efficiency and the yield rate of soldering.
In view of this, the inventors have devoted themselves to the above-mentioned related art, researched intensively and cooperated with the application of science to try to solve the above-mentioned problems. Finally, the invention which is reasonable and effective to overcome the above drawbacks is provided.
An object of the disclosure is to make the multi-layer printed circuit board reduce the cooling speed of the through holes to avoid an excessively low temperature of a pad to affect the soldering efficiency with keeping the high-frequency transmission and the signal isolation.
To accomplish the above object, the disclosure provides a multi-layer printed circuit board, which includes a base-layer metal, multiple middle metal layers and a top-layer metal. The middle metal layers are stacked on the base-layer metal in order. The top-layer metal is disposed on the middle metal layers. The base-layer metal, each of the middle metal layers and the top-layer metal are formed with multiple through holes respectively. Part of the middle metal layers are separately formed with multiple hole groups corresponding to the through holes. Each hole group includes multiple passing holes. The passing holes jointly surround a corresponding one of the through holes to form multiple connecting channels.
The disclosure further has the following functions. The base-layer metal, each middle metal layer and the top-layer metal are formed with multiple through holes to generate signal isolation to reduce the crosstalk interference between high-frequency signals. The passing holes around the through hole may decrease the conductive area around the through hole to reduce the cooling speed to avoid an excessively low temperature of a pad and to be advantageous to the subsequent soldering process. By adjusting the numbers of the passing holes and the connecting channels of the hole group, the cooling speed around the through holes may be increased or decreased.
The technical contents of this disclosure will become apparent with the detailed description of embodiments accompanied with the illustration of related drawings as follows. It is intended that the embodiments and drawings disclosed herein are to be considered illustrative rather than restrictive.
Please refer to
The base-layer metal 10, each middle metal layer 20 and the top-layer metal 30 are made of, but not limited to, one of aluminum, steel, copper, and iron. In some embodiments, a metal layer made of aluminum, steel or iron may be further coated with copper foil to increase the conductive efficiency. A surface of the base-layer metal 10 and a surface of the top-layer metal 30 are respectively disposed with multiple metal pins 11, 31 for facilitating plugging/unplugging of a connector (not shown in figures).
In the embodiment, the middle metal layers 20 are, but not limited to, four in number. However, the number of the middle metal layers 20 may also be two, six, eight or more than ten in other embodiments. In detail, the middle metal layers 20 in the embodiment include a first middle metal layer L1, a second middle metal layer L2, a third middle metal layer L3 and a fourth middle metal layer L4. The middle metal layer 20 are stacked on the base-layer metal from top to bottom in order. The top-layer metal 30 is disposed on the middle metal layers 20. That is, the top-layer metal 30 and the base-layer metal 10 are located on the top side and the bottom side of the middle metal layers 20, respectively.
The base-layer metal 10, each middle metal layers 20 and the top-layer metal 30 are respectively formed with multiple through holes 12, 22, 32 to generate signal isolation to reduce the crosstalk interference between high-frequency signals. In the embodiment, at least two adjacent middle metal layers 20 are formed with multiple hole groups 21. That is, the middle metal layers 20, which are partially connected, are respectively formed with multiple hole groups 21 corresponding to the through holes 22, but not limited to this. Please refer to the second embodiment shown in
Each hole group 21 includes multiple passing holes 211. The passing holes 211 jointly surround a corresponding one of the through holes 22 and multiple connecting channels 212 are disposed between the passing holes 211. In the embodiment, the passing holes 211 of each hole group 21 jointly surround a corresponding one of the through holes 22 to be arranged annularly, but not limited to this. The passing holes 211 may decrease the conductive area around the through holes 22 to reduce the cooling speed to avoid an excessively low temperature of a pad and to be advantageous to the subsequent soldering process. In the first embodiment of the disclosure, each passing hole 211 is of, but not limited, a substantially meniscoid shape. For example, each passing hole 211 may be of a substantially rectangular, triangular, oval, fan, or irregular shape. Each passing hole 211 with a rectangular shape is shown in
Furthermore, the number of the connecting channels 212 depends upon the number of the passing holes 211. Please refer to
Please refer to
While this disclosure has been described by means of specific embodiments, numerous modifications and variations could be made thereto by those skilled in the art without departing from the scope and spirit of this disclosure set forth in the claims.
Number | Name | Date | Kind |
---|---|---|---|
6646886 | Popovich | Nov 2003 | B1 |
7544899 | Kamada | Jun 2009 | B2 |
8106303 | Ishida | Jan 2012 | B2 |
9860975 | Kapoor | Jan 2018 | B2 |
20190200450 | Mellitz et al. | Jun 2019 | A1 |
20190208630 | Mandelboum et al. | Jul 2019 | A1 |
Number | Date | Country |
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M611951 | May 2021 | TW |
Entry |
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Office Action dated Feb. 10, 2023 of the corresponding Taiwan patent application No. 111109159. |
Number | Date | Country | |
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20230292437 A1 | Sep 2023 | US |