Patent Application
20250006788
The present disclosure generally relates to fabrication methods and structures for semiconductor devices, and more specifically, to techniques for forming nanosheet devices having multiple device regions separated by a shallow trench isolation (STI) area.
As integrated circuits (ICs) continue to move to smaller technology nodes, the ability to meet transistor performance demands with smaller dimensions (i.e., larger drive currents for a given footprint) becomes increasingly challenging, especially when forming nanosheet transistor devices having multiple device regions separated by a shallow trench isolation (STI) area. One particular challenge is the ability to maintain a uniform nanosheet height between the nanosheet transistor devices formed in the different device regions, both during and post nanosheet processing.
According to one embodiment of the present invention, a semiconductor device having improved nanosheet height control is provided. The semiconductor device includes a plurality of first nanosheet fin structures located in a dense array region of a substrate. The semiconductor device further includes a plurality of first isolation trenches between adjacent first nanosheet fin structures of the plurality of first nanosheet fin structures. The plurality of first isolation trenches include a first trench isolation layer, a protective layer formed on top of the first trench isolation layer, and a second trench isolation layer located above the protective liner. The first trench isolation layer is more dense than the second trench isolation layer. The protective liner separates the first trench isolation layer from the second trench isolation layer.
According to another aspect of the present invention, a semiconductor device having improved nanosheet height control is provided. The semiconductor device includes a plurality of first nanosheet fin structures located in a dense array region of a substrate. The semiconductor device further includes a plurality of first isolation trenches between adjacent first nanosheet fin structures of the plurality of first nanosheet fin structures. The plurality of first isolation trenches include a first trench isolation layer, a protective layer formed on top of the first trench isolation layer, and a second trench isolation layer located above the protective liner. The second trench isolation layer is more dense than the first trench isolation layer. The protective liner separates the first trench isolation layer from the second trench isolation layer.
According to another embodiment of the present invention, a method of forming a semiconductor device is provided. The method includes arranging a nanosheet stack on top of a substrate. The method further includes patterning the nanosheet stack and the substrate to form a plurality of first nanosheet fin structures in a dense array region of the substrate and at least one second nanosheet fin structure in an isolated region of the substrate. Patterning the nanosheet stack and the substrate further results in the formation of a plurality of first isolation trenches between adjacent first nanosheet fin structures of the plurality of nanosheet fin structures, and a second isolation trench separating the plurality of first fin structures in the dense array region of the substrate from the at least one second nanosheet fin in the isolated region of the substrate. The plurality of first isolation trenches are narrower than the second isolation trench.
The method further includes simultaneously depositing a first oxide material within the plurality of first isolation trenches and the second isolation trench to form a first trench isolation layer. The deposition rate is higher in the second isolation trench than in the plurality of first isolation trenches due to a deposition-loading effect. The method further includes stopping simultaneously depositing the first oxide in the plurality of first isolation trenches and the second isolation trench when a first height of the first trench isolation layer in the second isolation trench is substantially coplanar with a bottom surface of a nanosheet portion of the at least one second nanosheet fin structure, at which point a second height of the first trench isolation layer in the plurality of first isolation trenches is below the bottom surface of the nanosheet portion of the plurality of first nanosheet fin structures. The method further includes conformally depositing a protective liner material to form a protective liner over the first trench isolation layer, the plurality of first nanosheet fin structures in the dense array region, and the at least one second nanosheet fin structure in the isolated region. The method further includes simultaneously depositing a second oxide material within the plurality of first isolation trenches and the second isolation trench to form a second trench isolation layer. The second trench isolation layer is less dense than the first trench isolation layer. The method further includes simultaneously performing a dry etching process in the dense array region and the isolated region that is selective to the second trench isolation layer over the protective liner. The etch rate of the second trench isolation layer is faster in the isolated region than in the dense array region due to a dry etch-loading effect. The method further includes stopping simultaneously performing the dry etching process in the dense array region and the isolated region when a third height of the second trench isolation layer in the dense array region is substantially coplanar with the bottom surface of the nanosheet stack portion of the plurality of first nanosheet fin structures, at which point all of the second trench isolation layer has been removed from the isolated region.
According to another embodiment of the present invention, a method of forming a semiconductor device is provided. The method includes arranging a nanosheet stack on top of a substrate. The method further includes patterning the nanosheet stack and the substrate to form a plurality of first nanosheet fin structures in a dense array region of the substrate and at least one second nanosheet fin structure in an isolated region of the substrate. Patterning the nanosheet stack and the substrate further results in the formation of a plurality of first isolation trenches between adjacent first nanosheet fin structures of the plurality of nanosheet fin structures, and a second isolation trench separating the plurality of first nanosheet fin structures in the dense array region of the substrate from the at least one second nanosheet fin structure in the isolated region of the substrate. The plurality of first isolation trenches are narrower than the second isolation trench.
The method further includes conformally depositing a protective liner material to form a first protective liner over the plurality of first nanosheet fin structures in the dense array region of the substrate and the at least one second nanosheet fin structure in the isolated region of the substrate. The method further includes simultaneously depositing a first oxide material within the plurality of first isolation trenches and the second isolation trench to form a first trench isolation layer. The method further includes simultaneously performing one or more etching processes in the dense array region and the isolated region to recess the first trench isolation layer below a bottom surface of a nanosheet portion of the plurality of first nanosheet fin structures and the at least one second nanosheet fin structure. The method further includes depositing the protective liner material to form a second protective liner over the first trench isolation layer. The method further includes simultaneously depositing a second oxide material within the plurality of first isolation trenches and the second isolation trench to form a second trench isolation layer. The second trench isolation layer is denser than the first trench isolation layer. The method further includes simultaneously performing an etching process in the dense array region and the isolated region to recess the second trench isolation layer until the second trench isolation layer is substantially coplanar with the bottom surface of the nanosheet stack portion of the plurality of first nanosheet fin structures and the at least one second nanosheet fin structure.
The drawings included in the present disclosure are incorporated into, and form part of, the specification. They illustrate embodiments of the present disclosure and, along with the description, serve to explain the principles of the disclosure. The drawings are only illustrative of typical embodiments and do not limit the disclosure.
While the embodiments described herein are amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the particular embodiments described are not to be taken in a limiting sense. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure.
Embodiments of the present invention recognize that when forming semiconductor devices having multiple active nanosheet device regions (i.e., nanosheet devices formed on a substrate including a dense array region and an isolated region), there are various reasons that can contribute to active height (i.e., reveal height) variations between the nanosheet devices of the dense array and isolated regions. One possible reason for the nanosheet active height variation is during nanosheet processing, in which differences in the trench width between the shallow trench isolation (STI) regions in the dense array region and the isolated region can affect the recess rate of an STI oxide, such as silicon dioxide (SiO2), formed within the respective STI regions. In order to circumvent this problem, a multistep nanosheet reveal process may be used when different trench widths exist. For example, a wet etching process may be followed by a dry etching process (or vice versa) since the etch rate using the wet etching process alone will be higher in the dense array region than the isolated region, while the etch rate using the dry etching process alone will be higher in the isolated region than the dense array region. However, it is difficult to control the nanosheet height using this multistep process, which often results in variations in nanosheet height between the dense array and isolated regions.
Another possible reason for the nanosheet active height variation is due to the quality of the STI oxide (e.g., SiO2) used in the STI regions in the dense array and isolated regions. Current practices typically form an STI layer by performing flowable chemical vapor deposition (FCVD) of silicon dioxide (SiO2) (also known as “flowable oxide”). However, although FCVD of silicon dioxide is often used for its gap fill capabilities in the narrower, STI regions of the dense array region, it also results in a less dense/poorer quality oxide. The less dense STI oxide (e.g., SiO2) may be vulnerable to an increased recess rate during pre-nanosheet processes, such as pre epitaxial cleaning of the silicon substrate (e.g., using a buffered oxide etch (BOE)) for subsequent nanosheet formation, as well as during post nanosheet processes, such as gate spacer and P-N junction formation, both of which can result in gate flop-over caused by undercutting of the STI silicon dioxide under the gate, especially in the isolated region.
Embodiments of the present invention provide for nanosheet devices formed in multiple device regions (i.e., dense array and isolated regions) that have improved active nanosheet height control during nanosheet processing, as well as during pre-nanosheet and post-nanosheet processes. According to one aspect of the present invention, a method of forming a semiconductor device having improved nanosheet height control is provided. The method includes arranging a nanosheet stack on top of a substrate. The method further includes patterning the nanosheet stack and the substrate to form a plurality of first nanosheet fin structures in a dense array region of the substrate and at least one second nanosheet fin structure in an isolated region of the substrate. Patterning the nanosheet stack and the substrate further results in the formation of a plurality of first isolation trenches between adjacent first nanosheet fin structures of the plurality of nanosheet fin structures, and a second isolation trench separating the plurality of first nanosheet fin structures in the dense array region of the substrate from the at least one second nanosheet fin structure in the isolated region of the substrate. The plurality of first isolation trenches are narrower than the second isolation trench.
The method further includes simultaneously depositing a first oxide material within the plurality of first isolation trenches and the second isolation trench to form a first trench isolation layer. The deposition rate is higher in the second isolation trench than in the plurality of first isolation trenches due to a deposition-loading effect. This results in a technical effect of the plurality of first isolation trenches being filled with the first oxide material faster than the second isolation trench. The method further includes stopping simultaneously depositing the first oxide within the plurality of first isolation trenches and the second isolation trench when a first height of the first trench isolation layer in the second isolation trench is substantially coplanar with a bottom surface of a nanosheet portion of the at least one second nanosheet fin structure, at which point a second height of the first trench isolation layer in the plurality of first isolation trenches is below the bottom surface of the nanosheet portion of the plurality of first nanosheet fin structures due to the deposition-loading effect. This results in a technical effect of the height of the first trench isolation layer in the second isolation trench being higher than the height of first trench isolation layer in the plurality of first isolation trenches. This also results in a technical advantage of the final nanosheet height of the second nanosheet fin structure in the isolated region being completed during the deposition of the first oxide material, without the need for any etching processes. This also results in a technical advantage of being able to target the deposition of the first oxide material to the isolated region in order to obtain the final nanosheet height of the second nanosheet fin structure.
The method further includes conformally depositing a protective liner material to form a protective liner over the first trench isolation layer, the plurality of first nanosheet fin structures in the dense array region, and the at least one second nanosheet fin structure in the isolated region. The protective liner results in a technical effect of preventing oxidation of the patterned nanoshect stack during any subsequent annealing processes for densification of the less dense, second trench isolation layer. The method further includes simultaneously depositing a second oxide material within the plurality of first isolation trenches and the second isolation trench to form a second trench isolation layer. The second trench isolation layer is less dense than the first trench isolation layer. The more dense, first trench isolation layer located in the second isolation trench of the isolated region has the technical effect of being less vulnerable to etching during pre-nanosheet processes, such as pre epitaxial cleaning of the silicon substrate (e.g., using a buffered oxide etch (BOE)) for subsequent nanosheet formation, which ultimately reduces the potential for gate flop-over caused by undercutting the oxide under the gate, especially in the isolated region. The more dense, first trench isolation layer located in the second isolation trench of the isolated region also has the technical effect of being less vulnerable to etching during post-nanosheet processes, such as gate spacer and P-N junction formation, which ultimately reduces the potential for gate flop-over caused by undercutting of the oxide under the gate, especially in the isolated region.
The method further includes simultaneously performing a dry etching process in the dense array region and the isolated region that is selective to the second trench isolation layer over the protective liner. The etch rate of the second trench isolation layer is faster in the isolated region than in the dense array region due to a dry etch-loading effect. This results in a technical effect of the second trench isolation layer being removed faster from the isolated region than from the dense array region. The use of a dry etching process that is selective to the second trench isolation layer over the protective liner results in the technical advantage of being able to continue to remove the second trench isolation layer from the plurality of first isolation trenches of the dense array region until the nanosheet height of the first nanosheet fin structures in the dense array region equals the nanosheet height of the second nanosheet fin structure in the isolated region, without concern of altering the nanosheet height of the second nanosheet fin structure in the isolated region during the process. In other words, the use of a dry etching process that is selective to the second trench isolation layer over the protective liner results in the technical advantage of being able to target the dry etch process to the dense array region to obtain the final nanosheet height of the plurality of first nanosheet fin structures. The method further includes stopping simultaneously performing the dry etching process in the dense array region and the isolated region when a third height of the second trench isolation layer in the dense array region is substantially coplanar with the bottom surface of the nanosheet stack portion of the plurality of first nanosheet fin structures, at which point all of the second trench isolation layer has been removed from the isolated region.
In an embodiment, a first height of the first trench isolation layer is greater than a second height of the second trench isolation layer.
In an embodiment, the first oxide material used to form the first trench isolation layer and the second oxide material used to form the second trench isolation layer are silicon dioxide.
In an embodiment, simultaneously depositing the first oxide material within the plurality of first isolation trenches and the second isolation trench to form the first trench isolation layer includes performing high density plasma chemical vapor deposition of silicon dioxide, and simultaneously depositing the second oxide material within the plurality of first isolation trenches and the second isolation trench to form the second trench isolation layer includes performing flowable chemical vapor deposition of silicon dioxide. This results in a technical effect of the first trench isolation layer being more dense then the second trench isolation layer.
In an embodiment, simultaneously depositing the first oxide material within the plurality of first isolation trenches and the second isolation trench to form the first trench isolation layer includes performing flowable chemical vapor deposition of silicon dioxide, and simultaneously depositing the second oxide material within the plurality of first isolation trenches and the second isolation trench to form the second trench isolation layer includes performing high density plasma chemical vapor deposition of silicon dioxide. This results in a technical effect of the second trench isolation layer being more dense then the first trench isolation layer.
According to another aspect of the present invention, a method of forming a semiconductor device having improved nanosheet height control is provided. The method includes arranging a nanosheet stack on top of a substrate. The method further includes patterning the nanosheet stack and the substrate to form a plurality of first nanosheet fin structures in a dense array region of the substrate and at least one second nanosheet fin structure in an isolated region of the substrate. Patterning the nanosheet stack and the substrate further results in the formation of a plurality of first isolation trench regions between adjacent first nanosheet fin structures of the plurality of nanosheet fin structures, and a second isolation trench separating the plurality of first nanosheet fin structures in the dense array region of the substrate from the at least one second nanosheet fin structure in the isolated region of the substrate. The plurality of first isolation trenches are narrower than the second isolation trench.
The method further includes conformally depositing a protective liner material to form a first protective liner over the plurality of first nanosheet fin structures in the dense array region of the substrate and the at least one second nanosheet fin structure in the isolated region of the substrate. The method further includes simultaneously depositing a first oxide material within the plurality of first isolation trenches and the second isolation trench to form a first trench isolation layer. The protective liner results in a technical effect of preventing oxidation of the patterned nanosheet stack during any subsequent annealing processes for densification of the first trench isolation layer.
The method further includes simultaneously performing one or more etching processes in the dense array region and the isolated region to recess the first trench isolation layer below a bottom surface of a nanosheet portion of the plurality of first nanosheet fin structures, and the at least one second nanosheet fin structure. This results in a technical effect of providing a uniform height of the first trench isolation layer in the first trench isolation region of the dense array region and the second trench isolation region of the isolated region.
The method further includes depositing the protective liner material to form a second protective liner over the first trench isolation layer. The method further includes simultaneously depositing a second oxide material within the plurality of first isolation trenches and the second isolation trench to form a second trench isolation layer. The second trench isolation layer is denser than the first trench isolation layer. The more dense, second trench isolation layer in the dense array region and isolated region has the technical effect of being less vulnerable to etching during pre-nanosheet processes, such as pre epitaxial cleaning of the silicon substrate (e.g., using a buffered oxide etch (BOE)) for subsequent nanosheet formation, which ultimately reduces the potential for gate flop-over caused by undercutting of the oxide under the gate, especially in the isolated region. The more dense, second trench isolation layer in the dense array region and isolated region also has the technical effect of being less vulnerable to etching during post-nanosheet processes, such as gate spacer and P-N junction formation, which ultimately reduces the potential for gate flop-over caused by undercutting of the oxide under the gate, especially in the isolated region. The method further include simultaneously performing an etching process in the dense array region and the isolated region to recess the second trench isolation layer until the second trench isolation layer is substantially coplanar with the bottom surface of the nanosheet stack portion of the plurality of first nanosheet fin structures and the at least one second nanosheet fin structure. This results in a technical effect of the plurality of first nanosheet fin structures and the second nanosheet fin structure being uniform in height.
In an embodiment, the first trench isolation layer formed in the dense array region has a same first height as the first trench isolation layer formed in the isolated region, and the second trench isolation layer formed in the dense array region has a same second height as the second trench isolation layer formed in the isolated region.
In an embodiment, the first oxide material used to form first trench isolation layer, and the second oxide material used to form the second trench isolation layer are both silicon dioxide.
According to another aspect of the present invention, a semiconductor device having improved nanosheet height control is provided. The semiconductor device includes a plurality of first nanosheet fin structures located in a dense array region of a substrate. The semiconductor device further includes a plurality of first isolation trenches between adjacent first nanosheet fin structures of the plurality of first nanosheet fin structures. The plurality of first isolation trenches include a first trench isolation layer, a protective layer formed on top of the first trench isolation layer, and a second trench isolation layer located above the protective liner. The first trench isolation layer is more dense than the second trench isolation layer. The protective liner separates the first trench isolation layer from the second trench isolation layer. Thus, illustrative embodiments provide for a technical effect of improved active height control during nanosheet processing, as well as during pre-nanosheet and post-nanosheet processes.
In an embodiment, a first height of the first trench isolation layer in the plurality of first isolation trenches is greater than a second height of the second trench isolation layer in the plurality of first isolation trenches.
In an embodiment, the first trench isolation layer is formed from a first oxide and the second trench isolation layer is formed from a second oxide.
In an embodiment, the first oxide used to form the first trench isolation layer and the second oxide used to form the second trench isolation layer are silicon dioxide.
In an embodiment, the first trench isolation layer is formed from high density plasma chemical vapor deposition of silicon dioxide, and the second trench isolation layer is formed from flowable chemical vapor deposition of silicon dioxide. This results in a technical effect of the first trench isolation layer being more dense then the second trench isolation layer.
In an embodiment, the second trench isolation layer in the plurality of first isolation trenches is substantially coplanar with a bottom surface of a nanosheet portion of the plurality of first nanosheet fin structures.
In an embodiment, the protective liner is further formed along respective sidewall portions the plurality of first isolation trenches extending between a top surface of the first trench isolation layer to a bottom surface of a nanosheet portion of the plurality of first nanosheet fin structures. This results in a technical effect of the second trench isolation layer in the dense array region being less vulnerable to etching during pre-nanosheet processes, such as pre epitaxial cleaning of the silicon substrate (e.g., using a buffered oxide etch (BOE)) for subsequent nanosheet formation, which ultimately reduces the potential for gate flop-over caused by undercutting the oxide under the gate. This also results in a technical effect of the second trench isolation layer in the dense array region being less vulnerable to etching during post-nanosheet processes, such as gate spacer and P-N junction formation, which ultimately reduces the potential for gate flop-over caused by undercutting of the oxide under the gate.
In an embodiment, the semiconductor device further includes a second isolation trench separating the plurality of first fin structures in the dense array region of the substrate from at least one second nanosheet fin in an isolated region of the substrate. The plurality of first isolation trenches are narrower than the second isolation trench. The second isolation trench includes the first isolation layer. The more dense, first trench isolation layer in the second isolation trench has a technical effect of being less vulnerable to etching during pre-nanosheet processes, such as pre epitaxial cleaning of the silicon substrate (e.g., using a buffered oxide etch (BOE)) for subsequent nanosheet formation, which ultimately reduces the potential for gate flop-over caused by undercutting of the oxide under the gate in the isolated region. The more dense, first trench isolation layer in the second isolated trench also has the technical effect of being less vulnerable to etching during post-nanosheet processes, such as gate spacer and P-N junction formation, which ultimately reduces the potential for gate flop-over caused by undercutting of the oxide under the gate in the isolated region.
In an embodiment, a third height of the first trench isolation layer in the second isolation trench is equal to a first height of the first trench isolation layer in the plurality of first isolation trenches plus a second height of the second trench isolation layer in the plurality of first isolation trenches.
In an embodiment, the first trench isolation layer in the second isolation trench is substantially coplanar with a bottom surface of a nanosheet portion of the at least one second nanosheet fin structure.
According to another aspect of the present invention, a semiconductor device having improved nanosheet height control is provided. The semiconductor device includes a plurality of first nanosheet fin structures located in a dense array region of a substrate. The semiconductor device further includes a plurality of first isolation trenches between adjacent first nanosheet fin structures of the plurality of first nanosheet fin structures. The plurality of first isolation trenches include a first trench isolation layer, a protective layer formed on top of the first trench isolation layer, and a second trench isolation layer located above the protective liner. The second trench isolation layer is more dense than the first trench isolation layer. The protective liner separates the first trench isolation layer from the second trench isolation layer. Thus, illustrative embodiments provide for a technical effect of improved active height control during nanosheet processing, as well as during pre-nanosheet and post-nanosheet processes.
In an embodiment, a first height of the first trench isolation layer in the plurality of first isolation trenches is greater than a second height of the second trench isolation layer in the plurality of first isolation trenches.
In an embodiment, the first trench isolation layer is formed from a first oxide and the second trench isolation layer is formed from a second oxide.
In an embodiment, the first oxide used to form the first trench isolation layer and the second oxide used to form the second trench isolation layer are silicon dioxide.
In an embodiment, the first trench isolation layer in the plurality of first isolation trenches is below with a bottom surface of a nanosheet portion of the plurality of first nanosheet fin structures.
In an embodiment, the second trench isolation layer in the plurality of first isolation trenches is substantially coplanar with the bottom surface of the nanosheet portion of the plurality of first nanosheet fin structures.
In an embodiment, the first trench isolation layer is formed from flowable chemical vapor deposition of silicon dioxide, and the second trench isolation layer is formed from high density plasma chemical vapor deposition of silicon dioxide. This results in a technical effect of the second trench isolation layer being more dense then the first trench isolation layer.
In an embodiment, the semiconductor device further includes a second isolation trench separating the plurality of first fin structures in the dense array region of the substrate from at least one second nanosheet fin in an isolated region of the substrate. The plurality of first isolation trenches are narrower than the second isolation trench. The second isolation trench includes the first trench isolation layer, the protective layer formed on top of the first trench isolation layer, and the second trench isolation layer located above the protective liner. The more dense, second trench isolation layer in the second isolation trench has a technical effect of being less vulnerable to etching during pre-nanosheet processes, such as pre epitaxial cleaning of the silicon substrate (e.g., using a buffered oxide etch (BOE)) for subsequent nanosheet formation, which ultimately reduces the potential for gate flop-over caused by undercutting of the oxide under the gate in the isolated region. The more dense, first trench isolation layer in the second isolated trench also has the technical effect of being less vulnerable to etching during post-nanosheet processes, such as gate spacer and P-N junction formation, which ultimately reduces the potential for gate flop-over caused by undercutting of the oxide under the gate in the isolated region.
In an embodiment, the first trench isolation layer in the plurality of first isolation trenches and the first trench isolation layer in the second isolation trench have a same first height, and the second trench isolation layer in the plurality of first isolation trenches and the second trench isolation layer in the second isolation trench have a same second height.
In an embodiment, the first trench isolation layer in the second isolation trench is below with a bottom surface of a nanosheet portion of the plurality of first nanosheet fin structures.
In an embodiment, the second trench isolation layer in second isolation trench is substantially coplanar with the bottom surface of the nanosheet portion of the plurality of first nanosheet fin structures.
In an embodiment, the protective liner is further formed along respective sidewall portions the plurality of first isolation trenches and the second isolation trench extending between a top surface of the first trench isolation layer to a bottom surface of a nanosheet portion of the plurality of first nanosheet fin structures and the second nanosheet fin structure. This results in a technical effect of the second trench isolation layer in the dense array region and the isolated region being less vulnerable to etching during pre-nanosheet processes, such as pre epitaxial cleaning of the silicon substrate (e.g., using a buffered oxide etch (BOE)) for subsequent nanosheet formation, which ultimately reduces the potential for gate flop-over caused by undercutting the oxide under the gate. This also results in a technical effect of the second trench isolation layer in the dense array region and the isolated region being less vulnerable to etching during post-nanosheet processes, such as gate spacer and P-N junction formation, which ultimately reduces the potential for gate flop-over caused by undercutting of the oxide under the gate.
In an embodiment, the protective liner completely surrounds the first trench isolation layer formed in the plurality of first isolation trenches and the second isolation trench.
The aforementioned advantages, as well as any subsequently mentioned advantages are example advantages, and not all advantages are discussed. Furthermore, embodiments of the present disclosure can exist that contain all, some, or none of the aforementioned advantages and subsequently mentioned advantages while remaining within the spirit and scope of the present disclosure.
Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments of the invention. However, it is to be understood that embodiments of the invention may be practiced without these specific details. As such, this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
For purposes of the description hereinafter, terms such as “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. Terms such as “above”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is focused on the distinctive features or elements of various embodiments of the present invention.
As used herein, terms such as “depositing,” “forming,” and the like may refer to the disposition of layers, or portions of materials, in accordance with a given embodiment. Such processes may or may not be different than those used in the standard practice of the art of semiconductor device fabrication. Such processes include, but are not limited to, atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), limited reaction processing CVD (LRPCVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), metalorganic chemical vapor deposition (MOCVD), physical vapor deposition, sputtering, plating, electroplating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, chemical solution deposition, or any combination of those methods.
As used herein, terms, such as “forming,” and the like, may refer to processes that alter the structure and/or composition of one or more layers of material or portions of materials in accordance with a given embodiment. For example, such formation processes may include, but are not limited to, exposure to a specific frequency or range of frequencies of electromagnetic radiation, ion implantation techniques, and/or chemical/mechanical polishing (CMP). As used herein, terms, such as “forming,” and the like, may refer to processes that alter the structure of one or more layers of material, or portions of material(s), by removal of a quantity of material, in accordance with a given embodiment. For example, such formation processes may include, but are not limited to, micromachining, microetching, wet and/or dry etching processes, plasma etching processes, or any of the known etching processes in which material is removed.
As used herein, the term “deposition-loading effect” shall mean a change in the deposition rate of a material based on trench width. According to the term “deposition-loading effect” as used herein, a positive correlation exists between deposition rate and trench width. For example, the deposition rate of a material within a trench increases as the trench width increases. Similarly, the deposition rate of a material within a trench decreases as the trench width decreases.
As used herein, the term “dry etch-loading effect” shall mean a change in the dry etch rate of a material based on trench width. According to the term “dry etch-loading effect” as used herein, a positive correlation exists between dry etch rate and trench width. For example, the dry etch rate of a material within a trench increases as the trench width increases. Similarly, the dry etch rate of a material within a trench decreases as the trench width decreases.
As used herein, the term “wet etch-loading effect” shall mean a change in the wet etch rate of a material based on trench width. According to the term “wet etch-loading effect” as used herein, a negative correlation exists between wet etch rate and trench width. For example, the wet etch rate of a material within a trench decreases as the trench width increases. Similarly, the wet etch rate of a material within a trench increases as the trench width decreases.
Those skilled in the art understand that many different techniques may be used to add, remove, and/or alter various materials, and portions thereof, and that embodiments of the present invention may leverage combinations of such processes to produce the structures disclosed herein without deviating from the scope of the present invention.
The present invention will now be described in detail with reference to the Figures.
In some embodiments, and as depicted in
In assembly of semiconductor structure 100, a nanosheet stack 120 is arranged above a sacrificial isolation layer 150. The nanosheet stack comprises an alternating arrangement of Si layers 140-1, 140-2, 140-3 and SiGe layers 130-1, 130-2, 130-3. Although three (3) Si layers and three (3) SiGe layers are shown, other numbers of Si layers and SiGe layers are contemplated. The nanosheet stack 120 may be further processed to define NFET region(s) and PFET region(s) of the semiconductor device.
The Si layers 140-1, 140-2, 140-3 and SiGe layers 130-1, 130-2, 130-3 may be epitaxially grown above the sacrificial isolation layer 150 (or above the BOX layer (not depicted)). As used herein, the term “epitaxially grown” means the growth of a semiconductor (crystalline) material on a deposition surface of another semiconductor (crystalline) material, in which the semiconductor material being grown (crystalline overlayer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial growth process, chemical reactants provided by source gases, as well as system parameters, are controlled to cause the depositing atoms to arrive at the deposition surface with sufficient energy to move about on the surface such that the depositing atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxially grown semiconductor material has substantially the same crystalline characteristics as the deposition surface. For example, an epitaxially grown semiconductor material deposited on a {100} orientated crystalline surface will take on a {100} orientation. In some embodiments, epitaxial growth processes are selective to forming on semiconductor surfaces, and generally do not deposit material on exposed surfaces such as silicon dioxide or silicon nitride surfaces.
The SiGe layers 130-1, 130-2, 130-3 may have any suitable atomic percentage of Ge. For convenience and ease of understanding, SiGe layers having a relatively lesser atomic percentage of Ge (such as the SiGe layers 130-1, 130-2, 130-3) will be referred as SiGe(x). In some embodiments, the SiGe(x) layers have a Ge concentration (x) from 5 atomic percent to 50atomic percent. In some embodiments, the SiGe(x) layers have a Ge concentration from 10 atomic percent to 40 atomic percent. In some embodiments, the SiGe(x) layers have a Ge concentration from 20 atomic percent to 30 atomic percent.
In some embodiments, the layers of the nanosheet stack 120 have a thickness less than or comparable to that of the sacrificial isolation layer 150. In some embodiments, the Si layers 140-1, 140-2, 140-3 have a thickness of 4 to 10 nm, and the SiGe(x) layers 130-1, 130-2, 130-3 have a thickness of 8 to 15 nm. In one non-limiting example, the sacrificial isolation layer 150 has a thickness of about 10 nm, the Si layers 140-1, 140-2, 140-3 have a thickness of about 6 nm, and the SiGe(x) layers 130-1, 130-2, 130-3 have a thickness of about 10 nm.
The sacrificial isolation layer 150 may be an SiGe layer with a relatively greater Ge concentration than the SiGe(x) layers 130-1, 130-2, 130-3. In some embodiments, the sacrificial isolation layer 150 may be a SiGe(x+25) layer having a Ge concentration that is at least 25 atomic percent greater than the SiGe(x) layers. In some embodiments, the nanosheet stack 120 may include one or more SiGe(x+25) layers in addition to the SiGe(x) layers. The greater Ge concentration in the SiGe(x+25) layers provides an etch selectivity greater than or equal to 30:1 relative to the lesser Ge concentration SiGe(x) layers. For example, the SiGe(x+25) layers may be selectively removed using HCl vapor etch chemistry.
In some embodiments in which the substrate 110 is formed from a bulk semiconductor material, the nanosheet stack 120 is formed by growing epitaxy layers above the substrate 110 as follows: a first SiGe layer having a high Ge concentration (e.g., greater than 50%) as a sacrificial isolation layer, and subsequent alternating layers of SiGe (e.g., 20-35% Ge) and Si above the sacrificial isolation layer.
In other embodiments in which the substrate 110 is formed from a SOI wafer, the nanosheet stack 120 may be formed as follows. The surface layer of the SOI wafer is thinned to have a thickness of approximately 5 to 10 nm. A layer of SiGe (30-60% Ge) is grown above the thinned surface layer. One example thickness of the SiGe layer is approximately 10 nm. An oxidation process is performed to intermix the Si of the surface layer with the SiGe layer to form a lower-concentration SiGe layer (20-40% Ge) with SiO2 formed above. The SiO2 may be removed using dilute hydrofluoric acid (DHF), and subsequent alternating layers of Si and SiGe (e.g., 20-35% Ge) may be grown above the lower-concentration SiGe layer.
After forming the nanosheet stack 120, a hard mask 160 is formed on top of the nanosheet stack 120. The hard mask 160, which is used for patterning the nanosheet stack 120, may be formed by depositing an inorganic hard mask material onto the top surface of the nanosheet stack 120. The hard mask 160 can be formed utilizing a deposition process including, but not limited to, CVD, PECVD, ALD, physical vapor deposition (PVD) or sputtering. In some embodiments, and as depicted, the hard mask 160 is formed from silicon nitride. However, other hard mask materials (e.g., titanium nitride, tantalum nitride, or any suitable inorganic metal-containing material) are contemplated.
For example, patterning the nanosheet stack 120 and substrate 110 includes depositing a photoresist material (not depicted) onto the surface of the hard mask 160. The photoresist material can be applied by any suitable techniques, including, but not limited to, coating or spin-on techniques. A photomask (not depicted) patterned with shapes defining fin structures 210-1, 210-2, 210-3, 210-4, 210-5, 210-6, 210-7 to be formed is placed over the photoresist material, and the photomask pattern is transferred to the photoresist material using a lithographic process, which creates recesses in the uncovered regions of the photoresist material. The resulting patterned photoresist material is subsequently used to create the same pattern in the hard mask 160. One or more etch processes may be employed to selectively remove portions of the hard mask 160 to pattern the hard mask 160. After formation of the patterned hard mask 160, the photoresist material may be stripped from the patterned hard mask 160 by ashing or other suitable processes. The resulting structure may be subjected to a wet clean.
During patterning of the nanosheet stack 120 and the substrate 110 using the patterned hard mask 160, the physically exposed portions of the nanosheet stack 120 and substrate 110 are removed by an anisotropic etching process such as, for example, reactive ion etching (RIE), ion beam etching (IBE), chemical wet etching, or a combination of IBE and chemical wet etching. The etch removes the exposed portions of the nanosheet stack 120 and substrate 110 that are not protected by the patterned hard mask 160 to form fin structures 210-1, 210-2, 210-3, 210-4, 210-5, 210-6, 210-7 in the dense array region 10 and isolated region 20 of the substrate 110.
As depicted, the resulting nanosheet fin structures 210-1, 210-2, 210-3, 210-4, 210-5, 210-6, 210-7 are formed having a single, uniform pitch. The “pitch” is the center to center distance between adjacent nanosheet fin structures. Each of the nanosheet fin structures 210-1-210-7 include a nanosheet portion 220 formed from the sacrificial isolation layer 150 and the nanosheet stack 120, and a fin portion 230 formed from the substrate 110. Each nanosheet portion 220 of the nanosheet fin structures 210-1-210-7 has a uniform height H1, and extends from the surface 112 of the substrate 110 that is in direct contact with the sacrificial isolation layer 150 to the top surface 122 of nanosheet stack 120. Each fin portion 230 of the nanosheet fin structures 210-1-210-7 has a uniform height H2, and extends from the surface 114 of the substrate 110 to the surface 112 of the substrate 110 that is in direct contact with the sacrificial isolation layer 150.
The block masks 310, 320 may be composed of an inorganic hard mask material (e.g., silicon nitride, titanium nitride, tantalum nitride, or any suitable inorganic metal-containing material) or an organic soft mask material (e.g., carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon). The block masks 320, 330 may be formed using the same processes and materials as described above with reference to patterning the hard mask 160 of
During patterning of the semiconductor structure 200 of
After the removal of the block masks 310, 320, first nanosheet fin structures (i.e., nanosheet fin structures 210-1. 210-2, 210-3, 210-4) are located in the dense array region 10, while second nanosheet fin structure (i.e., nanosheet fin structure 210-7) is located in the isolated region. The resulting semicondutor structure 400 further includes isolation trenches 330-1. 330-2, 330-3 (collectively referred to herein as a plurality of first isolation trenches) formed between adjacent nanosheet fin structures 210-1, 210-2, 210-3, 210-4 in the dense array region 10, and isolation trenches 340-1, 340-2 (collectively referred to herein as second isolation trenches) formed adjacent to the nanosheet fin structure 210-7 in the isolated region 20. As depicted, the trench width W1 of isolation trenches 330-1, 330-2, 330-3 in the dense array region 10 is significantly narrower than the trench widths W2. W3 of isolation trenches 340-1, 340-2 of the isolated region 20.
In some embodiments, and as depicted, the first trench isolation layer 410 is formed by performing high density plasma chemical vapor deposition (HDPCVD) of an oxide material, such as silicon dioxide (SiO2). HDPCVD is a special form of plasma enhanced chemical vapor deposition (PECVD) that uses an inductively coupled plasms (ICP) source that provides a higher plasma density than a standard parallel-place PECVD system. High plasma density using ICP makes it possible to form more dense films at even lower temperatures (e.g., under 150° C.). However, in other embodiments, the first trench isolation layer 410 may be formed using alternative deposition techniques, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, chemical solution deposition, or any other suitable deposition techniques.
In some embodiments, and as depicted in
One or more anisotropic etching processes, such as, for example, reactive ion etching (RIE), ion beam etching (IBE), chemical wet etching, or a combination of IBE and chemical wet etching may be subsequently employed to remove any of the first trench isolation material formed onto the sidewalls of the hard mask 160 and the nanosheet fin structures 210-1, 210-2, 210-3, 210-4, 210-above the bottom surface 152 of the sacrificial isolation layer 150.
Deposition of the first trench isolation layer may terminate when the first trench isolation layer 410 is substantially coplanar with a bottom surface 152 of the sacrificial isolation layer 150 of the nanosheet portion 220 of the nanosheet fin structure 210-7 in the isolated region 20. Due to a deposition-loading effect caused by a difference in the trench width W1 of the isolation trenches 330-1, 330-2, 330-3330 formed between adjacent nanosheet fin structures 210-1, 210-2, 210-3, 210-4 in the dense array region 10, and the trench widths W2, W3 of the isolation trenches 340-1, 340-2 formed adjacent to the nanosheet fin structure 210-7 in the isolated region 20, the deposition rate of the first trench isolation material is higher in the isolation trenches 340-1, 340-2 in the isolated region 20 than in the isolation trenches 330-1, 330-2, 330-3 in the dense array region 10. This results in the height H1 of the first trench isolation layer 410 in the isolated region 20 being greater than the height H2 of the first trench isolation layer 410 in the dense array region 10. By advantageously using the deposition-loading effect, the reveal height of the nanosheet fin structure 210-7 in the isolated region 20 is completed during the deposition of the first trench isolation material, and without the need for any subsequent etching processes.
The protective liner 510 may be formed by conformally depositing a protective liner material onto the exposed surfaces semiconductor structure 400A. Is some embodiments, and as depicted, the protective liner 510 is composed of silicon nitride (SiN). However, in other embodiments, the protective liner 510 may be composed of one or more thin layers of a metal liner material such as, for example, tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), hafnium nitride (HfN), cobalt (Co), ruthenium (Ru), tungsten (W), tungsten nitride (WN), titanium-tungsten (TiW), tungsten nitride (WN) manganese (Mn), manganese nitride (MnN) or other barrier materials (or combinations of barrier materials) such as RuTaN, Ta/TaN, CoWP, NiMoP, or NiMoB which are suitable for the given application. A conformal layer of a protective liner material may be deposited using known techniques including, but not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, chemical solution deposition or plating. The thickness of the protective layer 510 may vary depending on the deposition process used, as well as the material employed. In some embodiments, the protective liner 510 may have a thickness from 2 nm to 50 nm. However, other thicknesses that are less than 2 nm, or greater than 50 nm can also be employed in embodiments of the present invention.
Following the formation of the protective liner 510, the second trench isolation layer 520 is formed on top of the protective liner 520. In some embodiments, and as depicted in
In some embodiments, the semiconductor structure 600A is further subjected to an annealing process (e.g., steam anneal, furnace anneal, rapid thermal anneal, flash anneal, or laser anneal) for densification of the second trench isolation layer 520. It should be appreciated that the protective liner 510 prevents any oxidation of the nanosheet fin structures 210-1, 210-2, 210-3, 210-4, 210-7 during the annealing process.
In some embodiments, and as depicted, the first trench isolation layer 410 and the second trench isolation layer 520 are composed of the same trench isolation materials, but have different densities. For example, the first trench isolation layer 410 is formed by high density plasma chemical vapor deposition (HDPCVD) of silicon dioxide (SiO2), and the second trench isolation layer 520 is formed by flowable chemical vapor deposition (FCVD) of silicon dioxide (SiO2), which will result in the first trench isolation layer 410 being more dense than the second trench isolation layer 520.
The planarization process, such as, for example, chemical mechanical planarization or polishing (CMP) and/or grinding, may be performed to remove any of the protective liner 510 and second trench isolation layer 520 present above the top surface 162. The planarization stops when the second trench isolation layer 520 is substantially coplanar with top surface 162 of the hard mask 160.
In a following process step, a single etching process (e.g., a dry etch that is selective to the second trench isolation layer 520 over the protective liner 510) is performed. Recessing of the second trench isolation layer 520 may terminate when the second trench isolation layer 520 is substantially coplanar with the bottom surface 152 of the sacrificial isolation layer 150 of the nanosheet portion 220 of the nanosheet fin structures 210-2, 210-2, 210-3, 210-4 in the dense array region 10. Due to a dry etch-loading effect caused by a difference in the trench width W1 of the isolation trenches 330-1, 330-2, 330-3330 formed between adjacent nanosheet fin structures 210-1. 210-2, 210-3, 210-4 in the dense array region 10, and the trench widths W2, W3 of the isolation trenches 340-1. 340-2 formed adjacent to the nanosheet fin structure 210-7 in the isolated region 20, the etch rate of the second trench isolation layer 520 is higher in the isolated region 20 than in the dense array region 10. This results in a portion of the second trench isolation layer 520 left remaining in the dense array region 10 after all of the second trench isolation layer 520 has been removed from the isolated region 20.
Furthermore, by using an etchant that is selective to the second trench isolation layer 520 over the protective liner 510, the second trench isolation layer 520 can continue to be recessed in the dense array region 10 without concern of altering the reveal height of the nanosheet fin structure 210-7 in the isolated region 10, even after all of the second trench isolation layer 520 has been removed from the isolated region 10. Accordingly, by advantageously using the dry etch-loading effect, recessing of the second isolation trench layer 520 can be targeted to the dense array region 10 to achieve the same reveal height for the nanosheet fin structures 210-1, 210-2, 210-3, 210-4 in the dense array region 10 as the reveal height of the nanosheet fin structure 210-7 in the isolated region 20.
For example, if the protective liner 510 and the patterned hard mask layer 160 are composed of a nitride, such as silicon nitride (SiN), and the first and second trench isolation layers 410, 520 are composed of an oxide, such as silicon dioxide (SiO2), then a wet etchant such as hot phosphoric acid may be used to remove the nitride material of the first and second trench isolation layers 410, 520 and the hard mask 160 selectively to the oxide material of the first and second trench isolation layers 410, 520. Similarly, since the patterned nanosheet stack 120 is not composed of a nitride, the hot phosphoric acid also will not etch the alternating layers of SiGe and Si of the patterned nanosheet stack 120.
As depicted, the protective liner 510 is completely removed from the isolated region 20, such that only the first trench isolation layer 410 remains in the trench isolation areas 340-1, 340-2 adjacent to the nanosheet fin structure 210-7 in the isolated region 20. It should be appreciated that since only the first trench isolation layer 410 (which is more dense/of higher quality than the second trench isolation layer 520) exists with the isolation trenches 340-1, 340-2 in the isolated region 20, the isolated nanosheet fin structure 210-7 is less vulnerable to gate flop-over caused by undercutting of the first trench isolation layer 410 during downstream processes, such as gate spacer and P-N junction formation.
As further depicted, a “U-shaped” portion of the protective liner 510 remains embedded within the isolation trenches 330-1, 330-2, 330-3 in the dense array region 10. In particular, the “U-shaped” portion of the protective liner is arranged on top of the first trench isolation layer 410 and along the sidewall portions of the fin structures 230 of the nanosheet fin structures 210-1, 210-2, 210-3, 210-4 extending between the top surface of the first trench isolation layer 410 and the bottom surface 152 of the sacrificial isolation layer 150. The denser, first trench isolation layer 410 is located below the protective liner 510, while the less dense, second trench isolation layer 520 is located above the protective liner 510.
Referring now to
In some embodiments, the protective liner 450 may be formed by conformally depositing a protective liner material, such as silicon nitride (SiN), onto the exposed surfaces semiconductor structure 400A. However, the protective liner 450 may also be formed using any of the materials and processes as discussed above with reference to the protective liner 510 of
Following the formation of the protective liner 450, a first trench isolation layer 460 is formed on top of the protective liner 450. In some embodiments, and as depicted in
In some embodiments, the semiconductor structure 500B is further subjected to an annealing process (e.g., steam anneal, furnace anneal, rapid thermal anneal, flash anneal, or laser anneal) for densification of the first trench isolation layer 460. It should be appreciated that the protective liner 450 prevents any oxidation of the nanosheet fin structures 210-1, 210-2, 210-3, 210-4, 210-7 during the annealing process. A planarization process such as, for example, chemical mechanical planarization or polishing (CMP) and/or grinding, may subsequently be performed to remove any of the first trench isolation layer 460 located above the top surface 452 of the protective liner 450. The planarization stops when the first trench isolation layer 460 is substantially coplanar with the top surface 452 of the protective liner 450.
The multistep etching process, which may include a wet etching process, followed by a dry etching process (or vice versa), is required to counterbalance one loading effect (e.g., a dry etch-loading effect) with another loading effect (e.g., a wet etch-loading effect) in order to obtain a uniform height H4 of the first trench isolation layer within isolation trenches 330-1, 330-2, 330-330 in the dense array region 10, and isolation trenches 340-1, 340-2 in the isolated region 20. For example, the use of a wet etching process will result in a wet-loading effect, in which the etch rate of the first trench isolation layer 460 a trench width W3 that is significantly narrower than. Conversely, the use of a dry etching process will result in the etch rate of the first trench isolation layer 460 being higher in the isolated region 20 than in the dese array region 10. Thus, in order to obtain a uniform height for the first trench isolation layer 460 in the dense array and isolated regions 10, 20, a combination of wet etching and drying etching may be employed.
Recessing of the first trench isolation layer 460 may terminate when the top surface 462 of first trench isolation layer 460 is below the bottom surface 152 of the sacrificial isolation layer 150 of the nanosheet portion 220 of the nanosheet fin structures 210-2, 210-2, 210-3, 210-4, 210-7. In various embodiments, the height H4 of the first trench isolation layer 460 may be higher than or lower than as depicted, so long as the top surface 462 of the first trench isolation layer is below the top surface 152 of the sacrificial isolation layer 150.
In some embodiments, the second protective liner 650 may be formed by directionally depositing a protective liner material, such as silicon nitride (SiN), onto the top surface 462 of the first trench isolation layer 460. As depicted, the directional deposition may also result in the formation of the second protective liner 650 on top of the first protective liner 450 located above the hard mask 160. However, in other embodiments, the second protective liner 650 may also be formed using any of the materials and processes as discussed above with reference to forming the first protective liner 510 of
Following the formation of the second protective liner 650, a second trench isolation layer 660 is formed on top of the second protective liner 650. In some embodiments, and as depicted in
In some embodiments, the one or more etching processes includes using an etchant that is selective to the material(s) of the first protective liner 450, the second protective liner 650, and the patterned hard mask 160. For example, if the first protective liner 450, the second protective liner 650, and the patterned hard mask layer 160 are all composed of a nitride, such as silicon nitride (SiN), and the second trench isolation layer is composed of an oxide, such as silicon dioxide (SiO2), then a wet etchant such as hot phosphoric acid may be used to remove the nitride material of the first and second protective liners 450, 650 and the hard mask 160 selectively to the oxide material of the second trench isolation layer 660. Similarly, since the patterned nanosheet stack 120 is not composed of a nitride, the hot phosphoric acid also will also etch the first and second protective liners 450, 650 and the hard mask 160 selectively to the alternating layers of SiGe and Si of the patterned nanosheet stack 120.
As depicted, a combination of the first protective liner 450 and the second protective liner 650 completely surround the first trench isolation layer 460 in both isolation trenches 350-1, 350-2, 350 of the dense array region 10 and isolation trenches 360-1, 360-2 of the isolated region, while the second trench isolation layer 660 is located on top of the second protective liner 650. As further depicted, a portion of the first protective liner 450 is also located along the sidewall portions of the fin structures 230 of the nanosheet fin structures 210-1, 210-2, 210-3, 210-4, 210-7 extending between the top surface of the first trench isolation layer 460 and the bottom surface 152 of the sacrificial isolation layer 150. The less dense, first trench isolation layer 460 is located below the protective liner 650, while the denser, second trench isolation layer 660 is located above the protective liner 650.
It should be appreciated that since the second trench isolation layer 660 (which is more dense/of higher quality than the second trench isolation layer 520) exists at the top of the isolation trenches 350-1, 350-2, 350-3, 360-1, 360-2, the nanosheet fin structures in both the dense array region 10 and isolated region are less vulnerable to gate flop-over caused by undercutting of the second trench isolation layer 660 during post nanosheet processing, such as gate spacer and P-N junction formation. It should further be appreciated that the protective liner formed between the first and second trench isolation layers has the technical effect of reducing and/or eliminating any gate flop-over caused by the potential removal of the second trench isolation layer 660 during additional post nanosheet processes, such as performing a buffered oxide etch (BOE), also known as HF or BHF, for pre epitaxial cleaning of the silicon substrate for subsequent nanosheet formation.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
In the preceding, reference is made to embodiments presented in this disclosure. However, the scope of the present disclosure is not limited to specific described embodiments. Instead, any combination of the features and elements, whether related to different embodiments or not, is contemplated to implement and practice contemplated embodiments. Furthermore, although embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the scope of the present disclosure. Thus, the aspects, features, embodiments and advantages discussed herein are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the invention” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).
