Patent Application
20160111380
High coefficient of thermal expansion (CTE) organic materials (e.g., silicon) are currently the most used materials for electronic packages, but have reached their limitations in meeting emerging mobile and high-end systems performance and reliability targets. Although they are widely available, readily processable and inexpensive, they can have (1) poor dimensional stability, which can lead to coarse lithography rules and bump pitch; and (2) large CTE mismatch with the silicon chips, which can result in excessive stresses in the interconnections and in ultra-low K dielectric layers, and warpage during fabrication and assembly, which can limit assembly yield and reliability at the chip- and package-levels.
Hence, microelectronic packages made with glass materials instead of high-CTE organic materials are now being used in many applications. Microelectronic packages with glass substrates can have silicon-matched CTE and outstanding dimensional stability, which can allow for large-size packages (˜60 mm) with high-density interconnections and lithographic rules below 5 μm, and low stress on the ultra-low K dielectrics. However, glass can be more fragile and more prone to cracking during processing than the traditional high-CTE organic materials. Accordingly, improved microelectronic packages with glass substrates and improved methods of processing them are desired.
Disclosed herein are coated microelectronic packages comprising: a microelectronic package having a top, a bottom, and an exposed edge; and a coating comprising a polymer, wherein the microelectronic package comprises a glass substrate, and wherein the coating covers at least a portion of the top, at least a portion of the bottom, and at least a portion of the exposed edge of the microelectronic package.
In some embodiments, the microelectronic package further comprises a metalized or filled through package via; a blind via connecting any two conductor layers on either side of the glass substrate; a dielectric layer; a stress relief barrier layer; a metallization seed layer; a passivation layer; a conductor; or a combination thereof. In some embodiments, the glass substrate has a thickness of from 30 microns to 500 microns.
In some embodiments, the coating covers all of the exposed edge of the microelectronic package. In some embodiments, the coating has an average thickness of from 1 micron to 25 microns. In some embodiments, the coating comprises epoxy, siloxane, benzocyclobutene, polyimide, polyenzoxazole, silicone, cyanate ester, polyolefin, hydrocarbons, polyurethanes, cyanoacrylates, or a combination thereof.
In some embodiments, the coating comprises a polyepoxide and can further comprise a polyfunctional amine, acid anhydride, phenol, alcohol, thiol, or combination thereof. In some embodiments, the polyepoxide has a mean epoxide functionality of from 1 to 10.
In some embodiments, the polymer has a viscosity of 180,000 centipoises or less at 25° C. In some embodiments, the polymer has a weight average molecular weight of 400 or less. In some embodiments, the polymer has a Young's modulus of 35 GN/m2 or less at 25° C. In some embodiments, the polymer has a coefficient of thermal expansion of 70×10−6 m/(m*K) or less at 25° C. In some embodiments, the coating is substantially free of fillers.
Also disclosed herein are methods of edge-coating a microelectronic package, the methods comprising: providing a microelectronic package comprising a glass substrate, wherein the microelectronic package has a top, a bottom, and an exposed edge; and coating at least a portion of the top, at least a portion of the bottom, and substantially all of the exposed edge of the microelectronic package with a coating comprising a polymer. In some embodiments, the methods further comprise curing the coating. In some embodiments, the curing comprises ultraviolet curing or thermosetting. In some embodiments, the coating covers all of the exposed edge of the microelectronic package.
Other embodiments, features, and aspects of the disclosed technology are described in detail herein and are considered a part of the claimed disclosed technology. Other embodiments, features, and aspects can be understood with reference to the following detailed description, accompanying drawings, and claims.
Reference will now be made to the accompanying figures and diagrams, which are not necessarily drawn to scale, and wherein:
Disclosed herein are methods, systems, and apparatuses related to coated microelectronic packages. Microelectronic packages with glass substrates, for instance, can have micro-defects that occur during processing (e.g., during dicing/singulation) that impact performance. For instance, before assembly, a microelectronic panel has to be singulated (singulation and dicing are used interchangeably herein) into individual functional structures. Various dicing methods exist that can be applied such as mechanical or laser dicing. The dicing processes can be adapted from wafer-level processes to minimize the damage created on the glass edges during singulation. Nonetheless, micro-defects can originate at the dicing interface from the physical dicing operation itself, or from release of the stress accumulated in the glass core during the various fabrication steps. Micro-cracks, for instance, can be created on the singulated interface and evolve into full-length cracks, propagating within the bulk of the glass core during later processing steps, such as chip-level and board-level assembly or reliability testing where heat treatments are applied to the glass structure. This phenomenon, known as SeWaRe, can considerably affect the fabrication yield of glass packages.
There are two sources of glass failure—dicing/singulation defects and stress from RDL). The occurrence of this failure mechanism can be limited by, for instance, improving glass handling during fabrication steps, optimizing of the dicing parameters, and/or optimizing the stack-up design rules to reduce residual stress in the glass core arising from copper and polymer coverage. These solutions can be highly beneficial and can improve the yield, but their application can limited by fabrication and equipment capability, as well as the needs to meet the requirements of emerging systems in terms of number of metal layers and copper coverage.
Coating the edges of the microelectronic package is a new, more systematic approach to preventing the development of SeWaRe failures from unavoidable micro-defects present in the structure. The coated microelectronic packages described herein can, in some embodiments, can address the technical challenges by coating the exposed edges of the package with a coating (which can comprise a polymer). This technology can include applying a layer of coating material on all exposed edges of glass panels, interposers or packages. The coating can be dispensed by classic underfilling dispense methods, dipping or overmolding to, for instance, coat uniformly all exposed edges of the glass in a few microns thin layer. The coating material, in some embodiments, does not contain any filler and can have a low enough viscosity to flow and fill all surface defects, even micron-size ones. Shrinkage during curing of the polymer introduces compressive stress in the structure to reduce the width of micro-cracks, and thus, in some embodiments, the shrinking of the coating during drying or curing can be minimized. After curing, the polymer can act as a stress buffer, reducing stress concentration on the singularity points where the defects were previously located, thus eliminating the risk of SeWaRe failure during post-process steps such as chip-level and board-level assembly.
Disclosed herein are microelectronic packages that are coated. The microelectronic package can be any microelectronic package known in the art. For instance, the microelectronic package can comprise an interposer/substrate; a through package via (TPV), which in some embodiments can be metalized or filled; a dielectric layer; a stress relief barrier layer; a metallization seed layer; a passivation layer; a conductor; or a combination thereof. Substrates used in semiconductor package circuits can provide a microelectronic package with a mechanical base support and an electrical interface for external communication access to the devices housed within the package.
The microelectronic package can comprise an interposer, which is an intermediate layer often used for interconnection routing between packages or integrated circuits (ICs) as a ground/power plane. Sometimes the terms “substrate” and “interposer” are used to refer to the same thing. In some embodiments, the interposer comprises glass. In some embodiments, the interposer comprises silicon. High-CTE organic materials (e.g., silicon) are currently the most used substrate materials for electronic packages, but have reached their limitations in meeting emerging mobile and high-end systems performance and reliability targets. Although they are widely available, readily processable and inexpensive, they have: (1) poor dimensional stability, leading to coarse lithography rules and bump pitch; and (2) large CTE mismatch with the silicon chips, resulting in excessive stresses in the interconnections and in ultra-low K dielectric layers, warpage during fabrication and assembly limiting assembly yield and reliability at chip- and package-levels. Interposers can include, in some embodiments, (1) good dimensional stability at ultra fine pitch; (2) good coefficient of thermal expansion (CTE) match with substrate and die, (3) good thermal path from the IC to the board; and (4) enabling of integration of embedded passive components with high quality factors.
In some embodiments, the glass substrate has silicon-matched coefficient of thermal expansion. In some embodiments, the glass substrate has outstanding dimensional stability, which allows for large-size packages (˜60 mm) with high-density interconnections and lithographic rules below 5 μm, and low stress on the ultra-low K dielectrics. In some embodiments, the glass substrate and package has ultra-fine line and space (L/S) redistribution layers and metalized trough package vias using ultra-thin glass (e.g., 30-500 μm in thickness). In some embodiments, the interposer is 30 μm in thickness or greater (e.g., 50 μm or greater, 70 μm or greater, 90 μm or greater, 110 μm or greater, 130 μm or greater, 150 μm or greater, 170 μm or greater, 190 μm or greater, 210 μm or greater, 230 μm or greater, 250 μm or greater, 270 μm or greater, 290 μm or greater, 310 μm or greater, 330 μm or greater, 350 μm or greater, 370 μm or greater, 390 μm or greater, 410 μm or greater, 430 μm or greater, 450 μm or greater, 470 μm or greater, or 490 μm or greater). In some embodiments, the interposer is 300 μm in thickness or less (e.g., 50 μm or less, 70 μm or less, 90 μm or less, 110 μm or less, 130 μm or less, 150 μm or less, 170 μm or less, 190 μm or less, 210 μm or less, 230 μm or less, 250 μm or less, 270 μm or less, 290 μm or less, 310 μm or less, 330 μm or less, 350 μm or less, 370 μm or less, 390 μm or less, 410 μm or less, 430 μm or less, 450 μm or less, 470 μm or less, or 490 μm or less). The package stack-up can, in some embodiments, eventually comprises a glass substrate (i.e., glass core), several polymer dielectric build-up and metallization layers as illustrated in
In some embodiments, a three dimensional interposer, or 3D Interposer, can be an interconnection between multiple ICs and the circuit board, or substrate, on which the ICs are installed. When used in applications involving ICs, interposers can provide an ultra-wide bandwidth between 3D ICs by means of fine pitch through-silicon-vias (TSVs) and through-package-vias (TPVs). TSVs can be vertical electrical connections passing completely through a silicon wafer or die whereas TPVs, or generally through vias, can be vertical electrical connections passing between or passing completely through one or more packages.
TPVs can be used in the creation of 3D packages and 3D ICs. TPVs can provide the means for designers to replace the edge wiring when creating 3D packages (e.g., System in Package, Chip Stack Multi-chip Module). By using TPVs, designers of 3D packages or 3D ICs can reduce the size of the IC or package, e.g., miniaturization. This is provided for because of the reduced, or eliminated, need for edge wiring as well as the ability to double-side mount both types of active circuits, logic and memory. The use of TPVs can also help reduce the size of passives on the board. These benefits also provide a means to extend wafer level packaging to higher I/Os as an alternative to wafer level fan out technologies.
Microelectronic packages can include, for instance, a through package via stress relief barrier, or buffer layer, that can provide thermal expansion and contraction stress relief barrier along with improved metallization capabilities. The stress relief barrier can help to reduce the effects of stress caused by the different CTEs while also, in some applications, promoting adhesion between the metallization layer and the interposer. This can help to increase reliability while also providing for smaller designs.
In some embodiments, a stress buffer layer can be deposited on a glass substrate material. The stress buffer layer can be designed to also act as an adhesion promoter for the metallization layer that can be added at a later time. The stress buffer layer material can vary and can have a relatively high structural stability, exhibit low-loss properties, and can have a relatively low dielectric constant, e.g., low-k. In some instances, the stress buffer layer having one or more of these characteristics can not only help to reduce the effects of thermal stress, but the stress buffer layer can also enable high quality factor RF integration (which can be helpful in higher I/O applications). In some embodiments, the stress buffer layer can be a polymer that is applied using a vacuum heating apparatus. In some embodiments, the polymer can be a copper clad polymer.
According to some embodiments, once the stress buffer layer is deposited, through vias can be formed. Vias can be formed using various methods including, but not limited to, mechanical removal, laser ablation, or chemical removal. In some embodiments, after the vias are formed, a metallization seed layer can be applied to help promote adhesion between the via side wall and the stress buffer layer with the metallization, which is, in some embodiments, copper. In some embodiments, after the metallization is applied, selective removal of portions of the metallization occurs to produce the TPVs.
Some embodiments can involve forming one or more vias in a glass substrate. Thereafter, the vias can be filled with a polymer stress buffer layer. Holes can then be formed through the stress buffer layer. A seed layer can be formed and, thereafter, metallization can be applied. Selective removal of the metallization can form TPVs. In some embodiments, the stress buffer layer can act as the support structure for the TPVs.
In some embodiments, through vias are formed in a glass substrate material. A combined seed and buffer layer can be formed on the surface and the walls of the vias. In some embodiments, the stress/buffer layer can be a metal, such as palladium. The vias can then be filled with metallization that can be subsequently selectively removed to form TPVs.
In some embodiments, the interposer is laminated with polymer lamination. Vias can then be formed and a buffer layer can be applied to the polymer lamination and the via side walls. A combined seed layer/via fill metallization layer can be applied and then subsequently selectively removed to form TPVs.
Interposer technology has evolved from ceramic to organic materials and, most recently, to silicon. Organic substrates typically require large capture pads because they exhibit relatively poor dimensional stability. However, there are two major shortcomings seen with the present-day approach using organic substrates. It is often difficult to achieve high I/Os at fine pitch because of poor dimensional stability of organic cores. Also, warpage results as the number of layers are increased. In a lot of cases, these issues cause organic substrates, or interposers, to be particularly unsuitable for very high I/Os with fine pitch interconnections. Because of this, there has been a trend to develop and use silicon interposers instead of organic interposers. But, silicon interposers also present issues. Silicon interposers are relatively expensive to process due to the need for electrical insulation around via walls. Also, silicon interposers are limited in size by the silicon wafer from which they originate.
As an alternative to silicon, glass can be used as the interposer to address the limitations of both silicon and organic interposers. The inherent electrical properties of glass, together with large area panel size availability, can offer advantages over silicon and organic interposer materials in some applications. The use of glass, though, presents some challenges, including micro-defects and cracking during processing (e.g., dicing/singulation), the formation of vias at low cost, and glass's lower thermal conductivity when compared to silicon.
Glass is increasingly being used to solve the issues presented by conventional interposers. Glass as a substrate, e.g. interposer, has several merits. Glass has a relatively good dimensional and thermal stability, the CTE of glass is closely matched to silicon, exhibits relatively good electrical properties, and is relatively available in large panel sizes. For example, machines that process large panel liquid crystal display (LCD) glass substrates used for high definition displays can be readily incorporated for processing glass substrates, achieving low cost and higher throughput.
Table 1 compares some electrical properties, process complexity and relative cost of glass, silicon and other potential metal and ceramic interposers.
In some embodiments a stress relief barrier, or stress relief layer, can be used to act as a buffer to absorb the stress caused by the difference of CTEs between the metal conductor (i.e., metallization, typically copper), and the glass substrate. According to some embodiments, the stress relief barrier can be an elastic interface that helps to maintain the physical connection between the metal conductor and the glass substrate, as well as any additional layers such as a metallization seed layer. The elastic property can help to reduce the probability of the occurrence of opens or shorts caused by the metal layer becoming physically detached from the interposer. Additionally, the stress relief barrier can help reduce or eliminate the propagation of cracks in the glass substrate formed either as a manufacturing defect, as a defect introduced during a processing step, or during thermal cycling. In some embodiments, using a stress relief barrier can help to reduce the thickness of the glass substrate, e.g. provide for “thin glass” interposers. Further, applying a stress relief barrier prior to via creation can help increase the pitch of the via, e.g. fine pitch or smaller pitch, by preventing removal of the top layer of the glass surrounding the via.
Because stress relief barrier 112 is designed to have some elastic and insulating properties, in some embodiments, a polymer having those properties can be used. Some embodiments of polymers that can be suitable include, but are not limited to, ZIF, RXP4, Dupont™ Kapton® polymide film, Dupont™ Pyralux® AC, and Dupont™ Pyralux® AP. It should be appreciated by those of ordinary skill in the art that the present disclosure is not limited to these polymers, but can also include other suitable polymers having similar physical and electrical qualities. In some embodiments, the polymer is deposited as a dry film, liquid coating or vapor phase deposition thin film In some embodiments, stress relief barrier as a coefficient of thermal expansion between glass and the metallization. Additionally, it should be understood by those of ordinary skill in the art that the present disclosure is not limited to polymers, as other non-polymeric materials having similar physical and electrical properties can be used. In some embodiments, the metallization layer and the stress relief barrier are the same materials. In one embodiment, the metallization layer and the stress relief barrier can various metals or composite materials such as, but not limited to, copper, palladium, nickel, nickel alloys, and copper alloys.
Metal layer 212 can expand and contract during the use of integrated circuit 208. The expansion can be caused by the heat generated when an electrical current passes through a conductor. In large scale applications, such as the wiring in a home, this heat can dissipate into the air. In small scale applications, such as microscale packaging designs, the heat cannot dissipate fast enough to prevent warming of the components in the package. This warming effect can cause the components in the package, including metal layer 212 and interposer 218, to expand. Upon the abatement of the current flow through metal layer 212, the materials can cool and contract. Interposer 218, glass in this example, can expand and contract at a different rate than metal layer 212, which typically expands faster than the interposer 218. The physical effects of this expansion and contraction, if not accounted for, can cause metal layer 212 to become partially or wholly removed from either glass substrate 218, ball grid array 202, or integrated circuit 208, or all of them.
To reduce the effects of the stress cause by the thermal cycling, stress relief barrier 214 can be deposited between one or more portions of the metal layer 212 and glass substrate 218. As metal layer 212 and glass substrate 218 expand and contract, stress relief barrier 214, in some embodiments an elastic or semi-elastic polymer, can absorb the stress developed between metal layer 212 and interposer 218, maintaining the physical connection between metal layer 212 and vias 21. Stress relief barrier 214 can help to prevent the lifting or failure of vias 210, thereby maintaining electrical connectivity from printed circuit board 200 to integrated circuit 208. Additionally, depending on the type of polymer selected, stress relief barrier 214 can also promote adhesion of metal layer 212 to interposer 218 by acting as a type of “glue” that maintains the bond between interposer 218 and metal layer 212.
According to some embodiments, the stress relief barrier is between the metal layer on the surface of the glass substrate and the metal in the core of the vias as well. In addition, the stress relief barrier can also help reduce the physical impact of a laser on the glass surface during the ablation process. In conventional systems, when a laser or other material removing means, such as acid, is used to create a through via, the top portion of the substrate can be acted upon by the removal means for a longer period of time than the lower portions. An unintended consequence of this longer reaction time can be that there is a continual removal of some of the top layers of the substrate. This can cause low pitch vias, i.e. vias having side walls angles less than normal to the plane of the substrate. Low pitch vias can not only require an increased amount of metallization to fill the via, thus increasing costs, but the dimensions of low pitch vias can reduce the number of through vias that can be placed in an area on the substrate.
It is often desirable to produce through vias that have small or fine pitches. As previously discussed, a small or fine pitch means that the walls of the vias are normal or nearly normal to the plane of the surface of the substrate, e.g. vertical or nearly vertical. A through via with coarse pitch can have walls that extend in a diagonal direction from the base of the through via, forming a “V” shape. The formation of fine pitch vertical feed through on glass is a challenge while building a 3D interposer. Etching glass is typically more difficult than etching silicon. Wet etching yields higher etch rates (˜10 μm/min) but the isotropy of etch profile is unfavorable for through vias on thick substrates.
To achieve higher pitch through vias in glass, a stress relief barrier can be used as a shield or protective barrier to prevent the material removal means from undesirably removing top portions of the substrate around the through via.
A hot press machine 304 can be used to carry out the double sided lamination of polymer 306. It should be noted that the lamination process can be used on one surface, e.g. the top surface or bottom surface of glass 302, or, on both the bottom and top surfaces. The laminated glass 302 can then be subjected to laser ablation. During the laser ablation process, polymer 306 can act as a stress relief barrier as well as a protective shield.
As discussed previously, the stress relief barrier can help to promote adhesion between the glass substrate and the metal conductor. In some embodiments it can be preferable or necessary to deposit the metal directly on the glass substrate, such as in the case of a wall of a through via. Direct Metallization on glass can be a challenge due to CTE mismatch at the metal glass interface. Surface modification techniques can enhance direct metal adhesion on glass, but fabrication of a relatively thick metal liner on glass can result in de-lamination. The use of a polymer stress relief barrier can help to promote metal adhesion on the glass surface. Typically, TPV metallization is a two step process. A seed layer can be first formed on all or part of the surfaces of the TPV which can be followed by metallization using, among other metals and methods, copper electroplating. There can be various ways to form a seed layer. For example, and not by way of limitation, electroless copper deposition or sputtering can be used to form the seed layer.
When removing the metallization seed layer and the lamination, as disclosed by way of example in
As shown in
In some embodiments, additional stabilization features are provided in a through via.
To help maintain the metallization in the through via through periods of thermal cycling,
Top interlock 746 can have an outer diameter AB whereas bottom interlock 748 can have an outer diameter CD. In some embodiments, the length of diameter AB can be longer, shorter, or the same length as diameter CD. The relationship between the lengths of diameters AB and CD can vary depending on the particular application of through via 742, costs, or other factors. Interlocks 746 and 748 secure metallization 744 in through via 742. It is intended that even if through via 742 metallization 744 separates from the side walls of through via 742, the securing action provided by top interlock 746 in combination with bottom interlock 748 can secure metallization 744 in through via 742.
Using various securement features, such as interlocks 746 and 748 of
The layers depicted in
The panels and packages disclosed herein undergo processing that can include dicing (aka singulation). Microelectronic packages with glass substrates, for instance, can have micro-defects that occur during processing (e.g., during dicing/singulation) that impact performance. For instance, before assembly, a microelectronic panel has to be singulated (singulation and dicing are used interchangeably herein) into individual functional structures. Various dicing methods exist that can be applied such as mechanical or laser dicing. The dicing processes can be adapted from wafer-level processes to minimize the damage created on the glass edges during singulation. Nonetheless, micro-defects can originate at the dicing interface from the physical dicing operation itself, or from release of the stress accumulated in the glass core during the various fabrication steps. Micro-cracks, for instance, can be created on the singulated interface and evolve into full-length cracks, propagating within the bulk of the glass core during later processing steps, such as chip-level and board-level assembly or reliability testing where heat treatments are applied to the glass structure. This phenomenon, known as SeWaRe, can considerably affect the fabrication yield of glass packages.
The occurrence of this failure mechanism can be limited by, for instance, improving glass handling during fabrication steps, optimizing of the dicing parameters, and/or optimizing the stack-up design rules to reduce residual stress in the glass core arising from copper and polymer coverage. These solutions can be highly beneficial and can improve the yield, but their application can limited by fabrication and equipment capability, as well as the needs to meet the requirements of emerging systems in terms of number of metal layers and copper coverage.
As previously described, the process of dicing glass panels may result in defects in the glass.
Coating the edges of the microelectronic package is a new, more systematic approach to preventing the development of SeWaRe failures from unavoidable micro-defects present in the structure, such as those caused by dicing. The coated microelectronic packages described herein can, in some embodiments, can address the technical challenges by coating the exposed edges of the package with a coating (which can comprise a polymer). This technology can include applying a layer of coating material on all exposed edges of glass panels, interposers or packages.
The coating added to the exposed edges of the microelectronic package can include any material that can reduce additional cracking or propagation of defects in the package. In some embodiments, the coating has ideal flowability, viscosity and particles size to fill all defects, even sub-micron size cracks, in the package. In some embodiments, the coating is curable. In some embodiments, the curable coating has ideal curing properties (e.g., shrinkage upon curing) to reduce defects sizes and stress concentration by polymer shrinkage. In some embodiments, the polymer has ideal mechanical properties (e.g., low modulus, low glass transition point, and low coefficient of thermal expansion) to considerably slow crack propagation. Any material that would seal the edge and reduce crack propagation can be used in the coating.
In some embodiments, the coating includes a polymer. In some embodiments, the coating includes any polymer or combination of polymers as described herein for use in the stress relief barrier. In some embodiments, the coating includes a polyepoxide. In some embodiments, the polyepoxide has at least two 1,2-epoxy groups per molecule. The polyepoxides can, in some embodiments, be saturated, unsaturated, cyclic or acyclic, aliphatic, alicyclic, aromatic or heterocyclic polyepoxy compounds. Examples of polyepoxides include, but are not limited to, the polyglycidyl ethers obtained by reacting epichlorohydrin or epibromohydrin with a polyphenol in the presence of alkali. Polyphenols suitable for this purpose are, for example, resorcinol, pyrocatechol, hydroquinone, bisphenol A (bis(4-hydroxyphenyl)-2,2-propane)), bisphenol F(bis(4-hydroxyphenyl)methane), bis(4-hydroxyphenyl)-1,1-isobutane, 4,4′-dihydroxybenzophenone, bis(4-hydroxyphenyl)-1,1-ethane, 1,5-hydroxynaphthalene.
Further polyepoxides include, but are not limited to, the polyglycidyl ethers of polyalcohols or diamines. These polyglycidyl ethers are derives from polyalcohols, such as ethylene glycol, diethylene glycol, triethylene glycol, 1,2-propylene glycol, 1,4-butylene glycol, triethylene glycol, 1,5-pentanediol, 1,6-hexanediol or trimethylolpropane. Further polyepoxides include, but are not limited to, polyglycidyl esters of polycarboxylic acids, for example reaction products of glycidol or epichlorohydrin with aliphatic or aromatic polycarboxylic acids, such as oxalic acid, succinic acid, glutaric acid, terephthalic acid or dimer fatty acid. Further epoxides include, but are not limited to, those derived from the epoxidation products of olefinically unsaturated cycloaliphatic compounds or from natural oils and fats.
Polyepoxides derived from the reaction of bisphenol A or bisphenol F and epichlorohydrin can be used, in some embodiments. Mixtures of liquid and solid epoxy can be used. Liquid epoxy resins based on bisphenol A can be used. In some embodiments, the polyepoxide has a mean epoxide functionality of from 1 to 10 (e.g., 1 or greater, 2 or greater, 3 or greater, 4 or greater, 5 or greater, 6 or greater, 7 or greater, 8 or greater, 9 or greater, 1 or less, 2 or less, 3 or less, 4 or less, 5 or less, 6 or less, 7 or less, 8 or less, or 9 or less).
In some embodiments, the microelectronic package has one or more edges (e.g., 2 edges, 3 edges, 4 edges). In some embodiments, the coating covers all of the exposed edges of the microelectronic package. In some embodiments, the coating covers substantially all of the exposed edges of the microelectronic package (e.g., 95% or more, 98% or more, 99% or more, or 99.5% or more). In some embodiments, the coating covers only a portion of the exposed edges of the microelectronic package (e.g., a top portion of the edge, a bottom portion of the edge, or both). In other words, in some embodiments the edge is not coated fully but only a portion of the edge is covered by polymer (the upper and lower sections of the edges), because there are methods that may only coat the edges near the top and bottom but not the middle of the edge. In some embodiments, the coating covers a portion of the top of the microelectronic package. In some embodiments, the coating covers a portion of the bottom of the microelectronic package. In some embodiments, the coating covers all or substantially all of the top, the bottom, and the exposed edges of the microelectronic package. In some embodiments, the coating has an average thickness of from 0.1 microns to 200 microns. In some embodiments, the coating has an average thickness of 0.2 microns or greater (e.g., 0.5 microns or greater, 1 micron or greater, 2 microns or greater, 3 microns or greater, 4 microns or greater, 5 microns or greater, 6 microns or greater, 7 microns or greater, 8 microns or greater, 9 microns or greater, 10 microns or greater, 25 microns or greater, 50 microns or greater, 75 microns or greater, 100 microns or greater, 125 microns or greater, 150 microns or greater, or 175 microns or greater). In some embodiments, the coating has an average thickness of 10 microns or less (e.g., 0.5 microns or less, 1 micron or less, 2 microns or less, 3 microns or less, 4 microns or less, 5 microns or less, 6 microns or less, 7 microns or less, 8 microns or less, 9 microns or less, 10 microns or less, 25 microns or less, 50 microns or less, 75 microns or less, 100 microns or less, 125 microns or less, 150 microns or less, or 175 microns or less). In some embodiments, the coating is uniform.
In some embodiments, the coating further comprises a polyfunctional amine, acid anhydride, phenol, alcohol, thiol, or combination thereof. In some embodiments, the coating comprises an additive (e.g., pigment, filler, hardener, dispersing additive). In some embodiments, the coating is substantially free of fillers.
In some embodiments, the polymer has a viscosity of 180,000 centipoises or less (e.g., 160,000 centipoises or less, 140,000 centipoises or less, 120,000 centipoises or less, 100,000 centipoises or less, 90,000 centipoises or less, 80,000 centipoises or less, 60,000 centipoises or less, 40,000 centipoises or less, 20,000 centipoises or less, 10,000 centipoises or less, 5,000 centipoises or less, 1,000 centipoises or less, or 500 centipoises or less) at 25° C. In some embodiments, the polymer has a weight average molecular weight of 400 or less (e.g., 350 or less, 300 or less, 250 or less, 200 or less, or 100 or less). In some embodiments, the polymer has a Young's modulus of 35 GN/m2 or less (e.g., 30 or less, 25 or less, 20 or less, 15 or less, 10 or less, or 5 or less) at 25° C. In some embodiments, the polymer has a coefficient of thermal expansion of 70 10−6 m/(m*K) or less at 25° C. These ranges are non-limiting. Any polymer or non-polymer coating material that can halt defect propagation can be used.
The coating can be applied to the microelectronic package using any coating method known in the art. The coating can be dispensed by classic underfilling dispense methods, dipping or overmolding to, for instance, coat exposed edges of the glass in a few microns thin layer. In some embodiments for trial testing, the polymer is coated on collar material on the side of the interposer (spread thin layer on FR4 board and dip the side of the interposer), dried at, for instance 70° C. (e.g., with a hot plate); the interposer can then be cleaned on the back side using for instance acetone and a wipe, and then subject to reflow. The coating material, in some embodiments, does not contain any filler and can have a low enough viscosity to flow and fill all surface defects, even micron-size ones. Shrinkage during curing of the polymer introduces compressive stress in the structure to reduce the width of micro-cracks, and thus, in some embodiments, the shrinking of the coating during drying or curing can be minimized. After curing, the polymer can act as a stress buffer, reducing stress concentration on the singularity points where the defects were previously located, thus eliminating the risk of SeWaRe failure during post-process steps such as chip-level and board-level assembly.
Also disclosed herein are methods of making an edge-coated microelectronic package, comprising providing a microelectronic package comprising a glass substrate, wherein the microelectronic package has a top, a bottom, and an exposed edge; and coating at least a portion of the top, at least a portion of the bottom, and substantially all of the exposed edge of the microelectronic package with a coating comprising a polymer. The coating can be a curable coating. Curing can be done by any method or combination of methods known in the art (e.g., UV curing, thermosetting, laser curing, etc.). In some embodiments, the coating does not need to be cured. As used herein, “edge” is not intended to include the sidewalls of a via.
The edge-coated microelectronic package have improved properties. For instance,
Laser dicing shows promising reliability. There can be multiple laser dicing methods, such as, CO2 laser, pulsed laser, or laser break.
Table 2 below shows mobile demonstrator (sample C) diced with two different conditions (wherein C-1, 3, and 4 have a dicing speed of 1 mm/s and C-2 has a dicing speed of 2 mm/s).
The coated microelectronics packages and methods disclosed herein can be used in a variety of commercial applications. For instance, glass as a package and interposer can be used in a variety of mobile and high-performance systems. This technology can benefit glass manufacturers, supply chain and end users in all microsystems applications. Additionally, high volume manufacturing for displays and other applications is also possible.
The coated microelectronics packages and methods disclosed herein can have a variety of advantages. For instance, exposed glass edges are a reliability concern due to glass cracking after dicing (SeWaRe failure). This packages and methods disclosed herein can provide a low-cost manufacturable structure that protects glass edges and prevents this failure mechanism during processing steps and in operation.
While certain embodiments of the disclosed technology have been described in connection with what is presently considered to be the most practical embodiments, it is to be understood that the disclosed technology is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
This written description uses examples to disclose certain embodiments of the disclosed technology, including the best mode, and also to enable any person skilled in the art to practice certain embodiments of the disclosed technology, including making and using any devices or systems and performing any incorporated methods. The patentable scope of certain embodiments of the disclosed technology is defined in the claims, and can include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.
This application claims priority to, and the benefit under 35 U.S.C. §119(e), of U.S. Provisional Patent Application No. 62/066,609, filed 21 Oct. 2014, the entire contents and substance of which are hereby incorporated by reference as if fully set forth below.
| Number | Date | Country | |
|---|---|---|---|
| 62066609 | Oct 2014 | US |
