Patent Application
20240321709
Various features relate to a package comprising an integrated device and a metallization portion.
A package may include a package substrate and an integrated device. These components are coupled together to provide a package that may perform various electrical functions. How the integrated device and the package substrate are coupled together affects how the package performs overall. There is an ongoing need to provide better performing packages.
Various features relate to a package comprising an integrated device and a package substrate.
One example provides a package comprising an integrated device; a substrate coupled to the integrated device through at least a first plurality of solder interconnects; and a metallization portion coupled to the substrate through at least a second plurality of solder interconnects. The metallization portion comprises at least one dielectric layer; and a plurality of metallization interconnects. The plurality of metallization interconnects comprises a first metallization interconnect located on a first metal layer, wherein the first metallization interconnect includes a first thickness; and a second metallization interconnect located on the first metal layer, wherein the second metallization interconnect includes a second thickness that is different from the first thickness.
Another example provides a package that includes a first integrated device, a second integrated device, a bridge coupled to the first integrated device and the second integrated device and a metallization portion coupled to the first integrated device and the second integrated device. The metallization portion comprises at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects comprise a first metallization interconnect located on a first metal layer and a second metallization interconnect located on the first metal layer. The first metallization interconnect includes a first thickness. The second metallization interconnect includes a second thickness that is different from the first thickness.
Various features, nature and advantages may become apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.
In the following description, specific details are given to provide a thorough understanding of the various aspects of the disclosure. However, it will be understood by one of ordinary skill in the art that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the aspects of the disclosure.
The present disclosure describes a package comprising an integrated device; a substrate coupled to the integrated device through at least a first plurality of solder interconnects; and a metallization portion coupled to the substrate through at least a second plurality of solder interconnects. The metallization portion comprises at least one dielectric layer; and a plurality of metallization interconnects. The plurality of metallization interconnects comprises a first metallization interconnect located on a first metal layer, wherein the first metallization interconnect includes a first thickness; and a second metallization interconnect located on the first metal layer, wherein the second metallization interconnect includes a second thickness that is different from the first thickness.
In some implementations, a package that includes a first integrated device, a second integrated device, a bridge coupled to the first integrated device and the second integrated device and a metallization portion coupled to the first integrated device and the second integrated device. The metallization portion comprises at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects comprise a first metallization interconnect located on a first metal layer and a second metallization interconnect located on the first metal layer. The first metallization interconnect includes a first thickness. The second metallization interconnect includes a second thickness that is different from the first thickness.
As will be further described below, the use of metallization interconnects with different thicknesses in the metallization portion provides several technical advantages, including the ability to customize and optimize the metallization interconnects for the type of signals and/or power that will travel through the metallization interconnects, which can help provide a package with improved performance.
The package 100 includes a metallization portion 102, an integrated device 103 and an encapsulation layer 106. The integrated device 103 is coupled to a first surface of the metallization portion 102. The integrated device 103 may be a first integrated device. The integrated device 103 may be bare die (e.g., semiconductor bare die). The integrated device 103 is coupled to the metallization portion 102. The front side of the integrated device 103 may face the metallization portion 102. The encapsulation layer 106 may encapsulate the integrated device 103. The encapsulation layer 106 may be coupled to the first surface of the metallization portion 102. An encapsulation layer (e.g., 106) may include a mold, a resin and/or an epoxy. The encapsulation layer may be a means for encapsulation. The encapsulation layer may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.
The metallization portion 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 122. The plurality of metallization interconnects 122 may include a first plurality of metallization interconnects 122a and a second plurality of metallization interconnects 122b. The first plurality of metallization interconnects 122a include a metallization interconnect 122aa, a metallization interconnect 122ab, a metallization interconnect 122ac, a metallization interconnect 122ad, a metallization interconnect 122ae, a metallization interconnect 122af, a metallization interconnect 122ag, and a metallization interconnect 122ah. The second plurality of metallization interconnects 122b include a metallization interconnect 122ba, a metallization interconnect 122bb, a metallization interconnect 122bc, a metallization interconnect 122bd, a metallization interconnect 122be, a metallization interconnect 122bf, a metallization interconnect 122bg, and a metallization interconnect 122bh.
The metallization interconnect 122aa is coupled to the metallization interconnect 122ab. The metallization interconnect 122ab is coupled to the metallization interconnect 122ac. The metallization interconnect 122ac is coupled to the metallization interconnect 122ad. The metallization interconnect 122ad is coupled to the metallization interconnect 122ac. The metallization interconnect 122ac is coupled to the metallization interconnect 122af. The metallization interconnect 122af is coupled to the metallization interconnect 122ag. The metallization interconnect 122ag is coupled to the metallization interconnect 122ah. The metallization interconnect 122aa, the metallization interconnect 122ac, the metallization interconnect 122ae and the metallization interconnect 122ag may include metallization vias (e.g., via interconnects, metallization via interconnects). The metallization interconnect 122ab, the metallization interconnect 122ad, the metallization interconnect 122af and the metallization interconnect 122ah may include metallization pads and/or metallization traces.
The metallization interconnect 122ba is coupled to the metallization interconnect 122bb. The metallization interconnect 122bb is coupled to the metallization interconnect 122bc. The metallization interconnect 122bc is coupled to the metallization interconnect 122bd. The metallization interconnect 122bd is coupled to the metallization interconnect 122be. The metallization interconnect 122be is coupled to the metallization interconnect 122bf. The metallization interconnect 122bf is coupled to the metallization interconnect 122bg. The metallization interconnect 122bg is coupled to the metallization interconnect 122bh. The metallization interconnect 122ba, the metallization interconnect 122bc, the metallization interconnect 122be and/or the metallization interconnect 122bg may include metallization vias (e.g., via interconnects, metallization via interconnects). The metallization interconnect 122bb, the metallization interconnect 122bd, the metallization interconnect 122bf and/or the metallization interconnect 122bh may include metallization pads and/or metallization traces.
The metallization interconnect 122ba may have a height HB1. The metallization interconnect 122bb may have a thickness TB1. The metallization interconnect 122bc may have a height HB2. The metallization interconnect 122bd may have a thickness TB2. The metallization interconnect 122be may have a height HB3. The metallization interconnect 122bf may have a thickness TB3. The metallization interconnect 122bg may have a height HB4. The metallization interconnect 122bh may have a thickness TB4.
The metallization interconnect 122ab and the metallization interconnect 122bb are located on the same metal layer (e.g., M1). The thickness (TA1) of the metallization interconnect 122ab is less than the thickness (TB1) of the metallization interconnect 122bb. The metallization interconnect 122ad and the metallization interconnect 122bd are located on the same metal layer (e.g., M2). The thickness (TA2) of the metallization interconnect 122ad is less than the thickness (TB2) of the metallization interconnect 122bd. The metallization interconnect 122af and the metallization interconnect 122bf are located on the same metal layer (e.g., M3). The thickness (TA3) of the metallization interconnect 122af is less than the thickness (TB3) of the metallization interconnect 122bb. The metallization interconnect 122ah and the metallization interconnect 122bh are located on the same metal layer (e.g., M4). The thickness (TA4) of the metallization interconnect 122ah is about the same as the thickness (TB4) of the metallization interconnect 122bh.
The metallization interconnect 122aa may have a height HA1 that is about the same as the height HB1 of the metallization interconnect 122ba. The metallization interconnect 122aa may have a width and/or diameter that is about the same as the width and/or diameter of the metallization interconnect 122ba. The metallization interconnect 122ac and the metallization interconnect 122bc may be located between the same metal layers (e.g., between M1 and M2). The metallization interconnect 122ac may have a height HA2 that is greater than the height HB2 of the metallization interconnect 122bc. The metallization interconnect 122ac may have a width and/or diameter that is less than the width and/or diameter of the metallization interconnect 122bc. The metallization interconnect 122ae and the metallization interconnect 122be may be located between the same metal layers (e.g., between M2 and M3). The metallization interconnect 122ae may have a height HA3 that is greater than the height HB3 of the metallization interconnect 122be. The metallization interconnect 122ae may have a width and/or diameter that is less than the width and/or diameter of the metallization interconnect 122be. The metallization interconnect 122ag and the metallization interconnect 122bg may be located between the same metal layers (e.g., between M3 and M4). The metallization interconnect 122ag may have a height HA4 that is greater than the height HB4 of the metallization interconnect 122bg. The metallization interconnect 122ag may have a width and/or diameter that is less than the width and/or diameter of the metallization interconnect 122bg.
As an example, in some implementations, the minimum thickness (e.g., TA1, TA2, TA3, TA4) of one or more interconnects (e.g., 122ab, 122ad, 122af) may be in a range of about 5-10 micrometers. In some implementations, the minimum height (e.g., HA2, HA3, HA4) of one or more via interconnects (e.g., 122ac, 122ae, 122ag) may be in a range of about 7-20 micrometers. In some implementations, the minimum thickness (e.g., TB1, TB2, TB3, TB4) of one or more interconnects (e.g., 122bb, 122bd, 122bf) may be in a range of about 7-20 micrometers. In some implementations, the minimum height (e.g., HB2, HB3, HB4) of one or more via interconnects (e.g., 122bc, 122be, 122bg) may be in a range of about 5-15 micrometers. In some implementations, one or more interconnects (e.g., trace interconnects) may have a minimum width of about 2 micrometers.
It is noted that the above minimum thicknesses, minimum heights, minimum widths and/or minimum diameters are exemplary. Different implementations may have metallization interconnects with different thicknesses, heights, widths and/or diameters (e.g., different minimum thicknesses, minimum heights, minimum widths and/or minimum diameters). Moreover, different implementations may have metallization interconnects with different relative thicknesses, relative heights, relative widths and/or relative diameters. In some implementations, metallization interconnects on a same metal layer may have one metallization interconnect that has a thickness that is at least 1.2 greater than the thickness of another metallization interconnect on the same layer. For example, the metallization interconnect 122bb may have a thickness TB1 that is at least 1.5 greater than the thickness TA1 of the metallization interconnect 122ab.
In some implementations, it may be optimal, preferred and/or more ideal to have metallization interconnects that are thicker, to allow more current to pass through, with less resistance. For example, when metallization interconnects are configured as an electrical path for power, it may be desirable to have thicker metallization interconnects so that there is less resistance in the electrical path, which may allow more power to travel to an integrated device. In contrast, metallization interconnects that are configured to provide electrical paths for signals (e.g., input/output (I/O) signals) may not need to be as big and/or thick since input/output signals operate at a lower voltage, and thus the dimensions (e.g., line width, line thickness) do not need to be a big as those of metallization interconnects configured to provide an electrical path for power.
Thus, the thickness and/or height of various metallization interconnects may be configured to optimize for the type of current that will travel through the metallization interconnects in the metallization portion. In one example, metallization interconnects that are configured to provide an electrical path for power, may have on higher thicknesses and/or greater widths and/or diameters than interconnects configured to provide electrical paths for signals. In another example, metallization interconnects that are configured to provide an electrical path for input/output signals, may have the smallest possible thickness, widths and/or diameters and/or thickness, widths and/or diameters that are smaller than interconnects configured to provide electrical paths for power and/or ground.
The integrated device 103 includes a die interconnect 130a and a die interconnect 130b. The die interconnect 130a and/or the die interconnect 130b may be a die pad for the integrated device 103. The die interconnect 130a is coupled to and touching the metallization interconnect 122aa of the metallization portion 102. The die interconnect 130b is coupled to and touching the metallization interconnect 122ba of the metallization portion 102.
The metallization interconnect 122ah may be coupled to and touching a solder interconnect from the plurality of solder interconnects 110. The metallization interconnect 122bh may be coupled to and touching another solder interconnect from the plurality of solder interconnects 110.
In some implementations, an electrical path between the board 108 and the integrated device 103 may include a board interconnect from the plurality of board interconnects 182, a solder interconnect from the plurality of solder interconnects 110, the first plurality of metallization interconnects 122a, and the die interconnect 130a.
In some implementations, an electrical path for input/output signals, between the board 108 and the integrated device 103, may include a board interconnect from the plurality of board interconnects 182, a solder interconnect from the plurality of solder interconnects 110, the first plurality of metallization interconnects 122a, and the die interconnect 130a.
In some implementations, an electrical path for power or ground, between the board 108 and the integrated device 103, may include a board interconnect from the plurality of board interconnects 182, a solder interconnect from the plurality of solder interconnects 110, the first plurality of metallization interconnects 122b, and the die interconnect 130a.
The package 200 includes a metallization portion 202, an integrated device 103 and an encapsulation layer 106. The integrated device 103 is coupled to a first surface of the metallization portion 202. The integrated device 103 may be a first integrated device. The integrated device 103 is coupled to the metallization portion 202. The front side of the integrated device 103 may face the metallization portion 202. The encapsulation layer 106 may encapsulate the integrated device 103. The encapsulation layer 106 may be coupled to the first surface of the metallization portion 202.
The metallization portion 202 includes at least one dielectric layer 220 and a plurality of metallization interconnects 222. The plurality of metallization interconnects 222 may include a first plurality of metallization interconnects 222a and a second plurality of metallization interconnects 222b. The first plurality of metallization interconnects 222a includes a metallization interconnect 222aa, a metallization interconnect 222ab, a metallization interconnect 222ac, a metallization interconnect 222ad, a metallization interconnect 222ae, a metallization interconnect 222af, a metallization interconnect 222ag, and a metallization interconnect 222ah. The second plurality of metallization interconnects 222b includes a metallization interconnect 222ba, a metallization interconnect 222bb, a metallization interconnect 222bc, a metallization interconnect 222bd, a metallization interconnect 222be, a metallization interconnect 222bf, a metallization interconnect 222bg, and a metallization interconnect 222bh.
The metallization interconnect 222aa is coupled to the metallization interconnect 222ab. The metallization interconnect 222ab is coupled to the metallization interconnect 222ac. The metallization interconnect 222ac is coupled to the metallization interconnect 222ad. The metallization interconnect 222ad is coupled to the metallization interconnect 222ac. The metallization interconnect 222ac is coupled to the metallization interconnect 222af. The metallization interconnect 222af is coupled to the metallization interconnect 222ag. The metallization interconnect 222ag is coupled to the metallization interconnect 222ah. The metallization interconnect 222aa, the metallization interconnect 222ac, the metallization interconnect 222ac and/or the metallization interconnect 222ag may include metallization vias. The metallization interconnect 222ab, the metallization interconnect 222ad, the metallization interconnect 222af and/or the metallization interconnect 222ah may include metallization pads and/or metallization traces.
The metallization interconnect 222ba is coupled to the metallization interconnect 222bb. The metallization interconnect 222bb is coupled to the metallization interconnect 222bc. The metallization interconnect 222bc is coupled to the metallization interconnect 222bd. The metallization interconnect 222bd is coupled to the metallization interconnect 222be. The metallization interconnect 222be is coupled to the metallization interconnect 222bf. The metallization interconnect 222bf is coupled to the metallization interconnect 222bg. The metallization interconnect 222bg is coupled to the metallization interconnect 222bh. The metallization interconnect 222ba, the metallization interconnect 222bc, the metallization interconnect 222be and/or the metallization interconnect 222bg may include metallization vias. The metallization interconnect 222bb, the metallization interconnect 222bd, the metallization interconnect 222bf and/or the metallization interconnect 222bh may include metallization pads and/or metallization traces.
The metallization interconnect 222ba may have a height HB1. The metallization interconnect 222bb may have a thickness TB1. The metallization interconnect 222bc may have a height HB2. The metallization interconnect 222bd may have a thickness TB2. The metallization interconnect 222be may have a height HB3. The metallization interconnect 222bf may have a thickness TB3. The metallization interconnect 222bg may have a height HB4. The metallization interconnect 222bh may have a thickness TB4.
The metallization interconnect 222ab and the metallization interconnect 222bb are located on the same metal layer (e.g., M1). The thickness (TA1) of the metallization interconnect 222ab is less than the thickness (TB1) of the metallization interconnect 222bb. The metallization interconnect 222ad and the metallization interconnect 222bd are located on the same metal layer (e.g., M2). The thickness (TA2) of the metallization interconnect 222ad is less than the thickness (TB2) of the metallization interconnect 222bd. The metallization interconnect 222af and the metallization interconnect 222bf are located on the same metal layer (e.g., M3). The thickness (TA3) of the metallization interconnect 222af is less than the thickness (TB3) of the metallization interconnect 222bb. The metallization interconnect 222ah and the metallization interconnect 222bh are located on the same metal layer (e.g., M4). The thickness (TA4) of the metallization interconnect 222ah is about the same as the thickness (TB4) of the metallization interconnect 222bh.
The metallization interconnect 222aa may have a height HA1 that is about the same as the height HB1 of the metallization interconnect 222ba. The metallization interconnect 222aa may have a width and/or diameter that is about the same as the width and/or diameter of the metallization interconnect 222ba. The metallization interconnect 222ac and the metallization interconnect 222bc may be located between the same metal layers (e.g., between M1 and M2). The metallization interconnect 222ac may have a height HA2 that is greater than the height HB2 of the metallization interconnect 222bc. The metallization interconnect 222ac may have a width and/or diameter that is less than the width and/or diameter of the metallization interconnect 222bc. The metallization interconnect 222ae and the metallization interconnect 222be may be located between the same metal layers (e.g., between M2 and M3). The metallization interconnect 222ae may have a height HA3 that is greater than the height HB3 of the metallization interconnect 222be. The metallization interconnect 222ae may have a width and/or diameter that is less than the width and/or diameter of the metallization interconnect 222be. The metallization interconnect 222ag and the metallization interconnect 222bg may be located between the same metal layers (e.g., between M3 and M4). The metallization interconnect 222ag may have a height HA4 that is greater than the height HB4 of the metallization interconnect 222bg. The metallization interconnect 222ag may have a width and/or diameter that is less than the width and/or diameter of the metallization interconnect 222bg. As an example, a first via metallization interconnect (e.g., 222ac) may include a first minimum diameter, and second via metallization interconnect (e.g., 222bc) may include a second minimum diameter that is greater than the first minimum diameter.
The electrical path 304 between the integrated device 103 and the board 108 may include another board interconnect from the plurality of board interconnects 182, another solder interconnect from the plurality of solder interconnects 110, the second plurality of metallization interconnects 222b, and the die interconnect 130b. The electrical path 304 may be configured to provide an electrical path for power or ground.
The electrical path 306 between the integrated device 103 and the board 108 may include another board interconnect from the plurality of board interconnects 182, another solder interconnect from the plurality of solder interconnects 110, a third plurality of metallization interconnects 222c, and the die interconnect 130c. The electrical path 306 may be configured to provide an electrical path for power or ground. The third plurality of metallization interconnects 222c may be similar to the second plurality of metallization interconnects 222b, in that they have metallization interconnects on the same metal layer with different thicknesses.
The metallization portion 402 includes at least one dielectric layer 420 and a plurality of metallization interconnects 422. The plurality of metallization interconnects 422 may include a first plurality of metallization interconnects 422a, a second plurality of metallization interconnects 422b, a third plurality of metallization interconnects 422c, and a fourth plurality of metallization interconnects 422d.
The first plurality of metallization interconnects 422a may be similar to the first plurality of metallization interconnects 122a and/or the first plurality of metallization interconnects 222a. The third plurality of metallization interconnects 422c may be similar to the first plurality of metallization interconnects 122a and/or the first plurality of metallization interconnects 222a. The second plurality of metallization interconnects 422b may be similar to the second plurality of metallization interconnects 122b and/or the second plurality of metallization interconnects 222b. The fourth plurality of metallization interconnects 422d may be similar to the second plurality of metallization interconnects 122b and/or the second plurality of metallization interconnects 222b.
An electrical path between the integrated device 403 and the board 108 may include the electrical path 404. The electrical path 404 may include another board interconnect from the plurality of board interconnects 182, another solder interconnect from the plurality of solder interconnects 110, the second plurality of metallization interconnects 422b, and a second die interconnect from the integrated device 403. The electrical path 404 may be configured to provide an electrical path for power or ground.
An electrical path between the integrated device 405 and the board 108 may include the electrical path 412. The electrical path 412 may include a board interconnect from the plurality of board interconnects 182, a solder interconnect from the plurality of solder interconnects 110, the third plurality of metallization interconnects 422c, and a first die interconnect from the integrated device 405. The electrical path 412 may be configured to provide an electrical path for input/output signals.
An electrical path between the integrated device 405 and the board 108 may include the electrical path 414. The electrical path 414 may include another board interconnect from the plurality of board interconnects 182, another solder interconnect from the plurality of solder interconnects 110, the fourth plurality of metallization interconnects 422d, and a second die interconnect from the integrated device 405. The electrical path 414 may be configured to provide an electrical path for power or ground.
An electrical path 416 between the integrated device 405 and the integrated device 403 may include a die interconnect from the integrated device 405, at least one metallization interconnect from the plurality of metallization interconnects 422 and a die interconnect from the integrated device 403.
A metallization portion may include a redistribution portion that includes redistribution interconnects (e.g., redistribution layer (RDL) interconnects). A redistribution interconnect may include portions that have a U-shape or V-shape. The terms “U-shape” and” V-shape” shall be interchangeable. The terms “U-shape” and “V-shape” may refer to the side profile shape of the interconnects and/or redistribution interconnects. The U-shape interconnect (e.g., U-shape side profile interconnect) and the V-shape interconnect (e.g., V-shape side profile interconnect) may have a top portion and a bottom portion. A bottom portion of a U-shape interconnect (or a V-shape interconnect) may be coupled to a top portion of another U-shape interconnect (or a V-shape interconnect).
An integrated device (e.g., 103, 403, 405) may include a die (e.g., semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs) based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si) based integrated device, a silicon carbide (SIC) based integrated device, a memory, power management processor, and/or combinations thereof. An integrated device (e.g., 103, 403, 405) may include at least one electronic circuit (e.g., first electronic circuit, second electronic circuit, etc. . . . ). An integrated device may include transistors. An integrated device may be an example of an electrical component and/or electrical device. In some implementations, an integrated device may be a chiplet. A chiplet may be fabricated using a process that provides better yields compared to other processes used to fabricate other types of integrated devices, which can lower the overall cost of fabricating a chiplet. Different chiplets may have different sizes and/or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different width and/or spacing). In some implementations, several chiplets may be used to perform the functionalities of one or more chips (e.g., one more integrated devices). As mentioned above, using several chiplets that perform several functions may reduce the overall cost of a package relative to using a single chip to perform all of the functions of a package. In some implementations, one or more of the chiplets and/or one of more of integrated devices (e.g., 103, 403, 405) described in the disclosure may be fabricated using the same technology node or two or more different technology nodes. For example, an integrated device (e.g., 403) may be fabricated using a first technology node, and a chiplet (e.g., 405) may be fabricated using a second technology node that is not as advanced as the first technology node. In such an example, the integrated device (e.g., 403) may include components (e.g., interconnects, transistors) that have a first minimum size, and the chiplet (e.g., 405) may include components (e.g., interconnects, transistors) that have a second minimum size, where the second minimum size is greater than the first minimum size. In some implementations, the integrated device 403 and the integrated device 405 of a package, may be fabricated using the same technology node or different technology nodes. In some implementations, a chiplet and another chiplet of a package, may be fabricated using the same technology node or different technology nodes.
A technology node may refer to a specific fabrication process and/or technology that is used to fabricate an integrated device and/or a chiplet. A technology node may specify the smallest possible size (e.g., minimum size) that can be fabricated (e.g., size of a transistor, width of trace, gap with between two transistors). Different technology nodes may have different yield loss. Different technology nodes may have different costs. Technology nodes that produce components (e.g., trace, transistors) with fine details are more expensive and may have higher yield loss, than a technology node that produces components (e.g., trace, transistors) with details that are less fine. Thus, more advanced technology nodes may be more expensive and may have higher yield loss, than less advanced technology nodes. When all of the functions of a package are implemented in single integrated devices, the same technology node is used to fabricate the entire integrated device, even if some of the functions of the integrated devices do not need to be fabricated using that particular technology node. Thus, the integrated device is locked into one technology node. To optimize the cost of a package, some of the functions can be implemented in different integrated devices and/or chiplets, where different integrated devices and/or chiplets may be fabricated using different technology nodes to reduce overall costs. For example, functions that require the use of the most advance technology node may be implemented in an integrated device, and functions that can be implemented using a less advanced technology node can be implemented in another integrated device and/or one or more chiplets. One example, would be an integrated device, fabricated using a first technology node (e.g., most advanced technology node), that is configured to provide compute applications, and at least one chiplet, that is fabricated using a second technology node, that is configured to provide other functionalities, where the second technology node is not as costly as the first technology node, and where the second technology node fabricates components with minimum sizes that are greater than the minimum sizes of components fabricated using the first technology node. Examples of compute applications may include high performance computing and/or high performance processing, which may be achieved by fabricating and packing in as many transistors as possible in an integrated device, which is why an integrated device that is configured for compute applications may be fabricated using the most advanced technology node available, while other chiplets may be fabricated using less advanced technology nodes, since those chiplets may not require as many transistors to be fabricated in the chiplets. Thus, the combination of using different technology nodes (which may have different associated yield loss) for different integrated devices and/or chiplets, can reduce the overall cost of a package, compared to using a single integrated device to perform all the functions of the package.
Another advantage of splitting the functions into several integrated devices and/or chiplets, is that it allows improvements in the performance of the package without having to redesign every single integrated device and/or chiplet. For example, if a configuration of a package uses a first integrated device and a first chiplet, it may be possible to improve the performance of the package by changing the design of the first integrated device, while keeping the design of the first chiplet the same. Thus, the first chiplet could be reused with the improved and/or different configured first integrated device. This saves cost by not having to redesign the first chiplet, when packages with improved integrated devices are fabricated.
It should be noted that the sequence of
Stage 1, as shown in
Stage 2 illustrates a state after an integrated device 103 is placed on the carrier 500 and the adhesive coat 501. A pick and place process may be used to place the integrated device. The front side of the integrated device 103 may be placed on the carrier 500 and the adhesive coat 501. In some implementations, more than one integrated device (e.g., 403, 405) may be placed on the carrier 500 and the adhesive coat 501.
Stage 3 illustrates a state after an encapsulation layer 106 is formed over the carrier 500, the adhesive coat 501 and the integrated device 103. The encapsulation layer 106 may encapsulate the integrated device 103. The encapsulation layer 106 may include a mold, a resin and/or an epoxy. The encapsulation layer 106 may be a means for encapsulation. The encapsulation layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, once the encapsulation layer 106 is provided, portions of the encapsulation layer 106 may be removed. For example, a grinding process may be used to remove a top portion of the encapsulation layer 106 and/or a back side of the integrated device 103.
Stage 4 illustrates a state after the carrier 500 and the adhesive coat 501 are decoupled from the integrated device 103 and the encapsulation layer 106. The carrier 500 and the adhesive coat 501 may be detached from the integrated device 103 and the encapsulation layer 106.
Stage 5, as shown in
Stage 6 illustrates a state after a dielectric layer 510 is formed over the integrated device 103 and the encapsulation layer 106. A deposition and/or a lamination process may be used to form the dielectric layer 510. The dielectric layer 510 may be formed over a front side of the integrated device 103.
Stage 7 illustrates a state after a plurality of cavities 511 are formed in the dielectric layer 510. The plurality of cavities 511 may be formed using an etching process (e.g., photo etching process). A masking process, an exposure process and/or a development process may be used to form the plurality of cavities 511. The plurality of cavities 511 may be formed over the plurality of die interconnects 130 of the integrated device 103, such that the plurality of die interconnects 130 are exposed (or at least part of the plurality of die interconnects 130 are exposed).
Stage 8 illustrates a state after metallization interconnects are formed in and over surfaces of the dielectric layer 510 and in the plurality of cavities 511. A plurality of metallization interconnects 512 may be formed over (e.g., above) a first surface of the dielectric layer 510 and the plurality of cavities 511. A masking process, a plating process, an exposure process, a development process and/or an etching process may be used to form the plurality of metallization interconnects 512.
Stage 9, as shown in
Stage 10 illustrates a state after some metallization interconnects from the plurality of metallization interconnects 512 are thickened to form a plurality of metallization interconnects 514. A masking process, a plating process, an exposure process, a development process and/or an etching process may be used to form the plurality of metallization interconnects 514. As a result, some metallization interconnects on the same metal layer may have different thicknesses.
Stage 11 illustrates a state after the photo resist layer 513 is removed. An etching process may be used to remove the photo resist layer 513.
Stage 12 illustrates a state after a dielectric layer 520 is formed over the dielectric layer 510, the plurality of metallization interconnects 512 and the plurality of metallization interconnects 514. A deposition and/or a lamination process may be used to form the dielectric layer 520. The dielectric layer 520 may be similar to the dielectric layer 510.
Stage 13 illustrates a state after a plurality of cavities 521 are formed in the dielectric layer 520. The plurality of cavities 521 may be formed using an etching process (e.g., photo etching process). A masking process, an exposure process and/or a development process may be used to form the plurality of cavities 521.
Stage 14 illustrates a state after metallization interconnects are formed in and over surfaces of the dielectric layer 520 and in the plurality of cavities 521. A plurality of metallization interconnects 522 may be formed over (e.g., above) a first surface of the dielectric layer 520 and the plurality of cavities 521. A masking process, a plating process, an exposure process, a development process and/or an etching process may be used to form the plurality of metallization interconnects 522.
Stage 15 illustrates a state after a photo resist layer 523 is formed over the dielectric layer 520. A deposition and/or lamination process may be used to form the photo resist layer 523. The photo resist layer 523 may include openings over some metallization interconnects from the plurality of metallization interconnects 522.
Stage 16 illustrates a state after some metallization interconnects from the plurality of metallization interconnects 522 are thickened to form a plurality of metallization interconnects 524. A masking process, a plating process, an exposure process, a development process and/or an etching process may be used to form the plurality of metallization interconnects 524. As a result, some metallization interconnects on the same metal layer may have different thicknesses.
Stage 17, as shown in
Stage 18 illustrates a state after a dielectric layer 530 is formed over the dielectric layer 520, the plurality of metallization interconnects 522 and the plurality of metallization interconnects 524. A deposition and/or a lamination process may be used to form the dielectric layer 530. The dielectric layer 530 may be similar to the dielectric layer 520.
Stage 19 illustrates a state after a plurality of cavities 531 are formed in the dielectric layer 530. The plurality of cavities 531 may be formed using an etching process (e.g., photo etching process). A masking process, an exposure process and/or a development process may be used to form the plurality of cavities 531.
Stage 20, as shown in
Stage 21 illustrates a state after a photo resist layer 533 is formed over the dielectric layer 530. A deposition and/or lamination process may be used to form the photo resist layer 533. The photo resist layer 533 may include openings over some metallization interconnects from the plurality of metallization interconnects 532.
Stage 22 illustrates a state after some metallization interconnects from the plurality of metallization interconnects 532 are thickened to form a plurality of metallization interconnects 534. A masking process, a plating process, an exposure process, a development process and/or an etching process may be used to form the plurality of metallization interconnects 534. As a result, some metallization interconnects on the same metal layer may have different thicknesses.
Stage 23, as shown in
Stage 24 illustrates a state after a dielectric layer 540 is formed over the dielectric layer 530, the plurality of metallization interconnects 532 and the plurality of metallization interconnects 534. A deposition and/or a lamination process may be used to form the dielectric layer 540. The dielectric layer 540 may be similar to the dielectric layer 530.
Stage 25 illustrates a state after a plurality of cavities 541 are formed in the dielectric layer 540. The plurality of cavities 541 may be formed using an etching process (e.g., photo etching process). A masking process, an exposure process and/or a development process may be used to form the plurality of cavities 541.
Stage 26, as shown in
Stage 27 illustrates a state after the carrier 502 is decoupled from the integrated device 103 and the encapsulation layer 106. The carrier 502 may be detached from the integrated device 103 and the encapsulation layer 106. The at least one dielectric layer 220 may represent the dielectric layer 510, the dielectric layer 520, the dielectric layer 530 and/or the dielectric layer 540. The plurality of metallization interconnects 222 may represent the plurality of metallization interconnects 512, the plurality of metallization interconnects 514, the plurality of metallization interconnects 522, the plurality of metallization interconnects 524, the plurality of metallization interconnects 532, the plurality of metallization interconnects 534, the plurality of metallization interconnects 542 and/or the plurality of metallization interconnects 544. The plurality of metallization interconnects 222 may include a first plurality of metallization interconnects 222a and a second plurality of metallization interconnects 222b, as described in at least
Stage 28 illustrates a state after a plurality of solder interconnects 110 are coupled to the metallization portion 202. A solder reflow process may be used to couple the plurality of solder interconnects 110 to the plurality of metallization interconnects 222 of the metallization portion 202.
In some implementations, fabricating a package includes several processes.
It should be noted that the method 600 of
The method provides (at 605) a carrier. In some implementations, the carrier may be provided with an adhesive. Stage 1 of
The method places (at 610) a front side of an integrated device over the carrier. In some implementations, the front side of the integrated device is placed over a carrier that includes and adhesive. In some implementations, more than one integrated device may be placed over the carrier. Stage 2 of
The method forms (at 615) an encapsulation layer that encapsulates the integrated device. The encapsulation layer may be coupled to the integrated device and the carrier. Stage 3 of
The method decouples (at 620) the carrier from the encapsulation layer and the integrated device. Stage 4 of
The method places (at 625) a back side of the integrated device and the encapsulation layer over another carrier (e.g., second carrier). The carrier may include an adhesive. Stage 5 of
The method forms (at 630) a metallization portion that is coupled to the front side of the integrated device and the encapsulation layer. The metallization portion may include at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects may include a first metallization interconnect on a first metal layer and a second metallization interconnect on a first metal layer, where the second interconnect has a second thickness that is different from a first thickness of the first metallization interconnect. Forming the metallization portion may include forming at least one dielectric layer and forming a first metallization interconnect on a first metal layer and a second metallization interconnect on a first metal layer. The second interconnect may have a second thickness that is different from a first thickness of the first metallization interconnect. Stage 6 of
The method couples (at 635) a plurality of solder interconnects to the metallization interconnects of the metallization portion. Stage 28 of
Exemplary Package Comprising an Integrated Device, a Metallization Portion, a Bridge and/or an Interposer
The integrated device 403 may be configured to perform a first plurality of functions and/or operations. The integrated device 405 may be configured to perform a second plurality of functions and/or operations. The second plurality of functions and/or operations include at least one function and/or operation that is different from the first plurality of functions and/or operations.
The metallization portion 402 is coupled to a second surface of the interposer 702 through a plurality of solder interconnects 740. The metallization portion 402 includes at least one dielectric layer 420 and a plurality of metallization interconnects 422. The plurality of metallization interconnects 422 may include a first plurality of metallization interconnects 422a, a second plurality of metallization interconnects 422b, a third plurality of metallization interconnects 422c, and a fourth plurality of metallization interconnects 422d.
The first plurality of metallization interconnects 422a may be similar to the first plurality of metallization interconnects 122a and/or the first plurality of metallization interconnects 222a. The third plurality of metallization interconnects 422c may be similar to the first plurality of metallization interconnects 122a and/or the first plurality of metallization interconnects 222a. The second plurality of metallization interconnects 422b may be similar to the second plurality of metallization interconnects 122b and/or the second plurality of metallization interconnects 222b. The fourth plurality of metallization interconnects 422d may be similar to the second plurality of metallization interconnects 122b and/or the second plurality of metallization interconnects 222b.
An electrical path between the integrated device 403 and the board 108 may include the electrical path 704. The electrical path 704 may include another board interconnect from the plurality of board interconnects 182, another solder interconnect from the plurality of solder interconnects 110, the second plurality of metallization interconnects 422b, a solder interconnect from the plurality of solder interconnects 740, an interposer interconnect from the plurality of interposer interconnects 722 (e.g., a substrate interconnect from the plurality of substrate interconnects), a solder interconnect from the plurality of solder interconnects 730, and a second die interconnect from the integrated device 403. The electrical path 704 may be configured to provide an electrical path for power or ground.
An electrical path between the integrated device 405 and the board 108 may include the electrical path 712. The electrical path 712 may include a board interconnect from the plurality of board interconnects 182, a solder interconnect from the plurality of solder interconnects 110, the third plurality of metallization interconnects 422c, a solder interconnect from the plurality of solder interconnects 740, an interposer interconnect from the plurality of interposer interconnects 722 (e.g., a substrate interconnect from the plurality of substrate interconnects), a solder interconnect from the plurality of solder interconnects 750, and a first die interconnect from the integrated device 405. The electrical path 712 may be configured to provide an electrical path for input/output signals.
An electrical path between the integrated device 405 and the board 108 may include the electrical path 714. The electrical path 714 may include another board interconnect from the plurality of board interconnects 182, another solder interconnect from the plurality of solder interconnects 110, the fourth plurality of metallization interconnects 422d, a solder interconnect from the plurality of solder interconnects 740, an interposer interconnect from the plurality of interposer interconnects 722 (e.g., a substrate interconnect from the plurality of substrate interconnects), a solder interconnect from the plurality of solder interconnects 750, and a second die interconnect from the integrated device 405. The electrical path 714 may be configured to provide an electrical path for power or ground.
An electrical path between the integrated device 405 and the integrated device 403 may include a die interconnect from the integrated device 405, at least one interposer interconnect from the plurality of interposer interconnects 722 and a die interconnect from the integrated device 403.
In some implementations, the package 700 may be fabricated by coupling the integrated device 403 and the integrated device 405 to the interposer 702 through a plurality of solder interconnects (e.g., 730, 750). A method may then couple the interposer 702 to the metallization portion 402 through a plurality of solder interconnects 740. A method may then couple the metallization portion 402 to the board 108 through a plurality of solder interconnects 110. However, different implementations may use a different sequence to fabricate the package 700. The interposer 702 may be used when there is a meaningful difference between the size and/or pitch of the pad interconnects of the integrated device (e.g., 403, 405) and the interconnects of the metallization portion 402.
The integrated device 403 is coupled to a first surface of the metallization portion 402. The integrated device 405 is coupled to the first surface of the metallization portion 402. The integrated device 403 may be bare die (e.g., semiconductor bare die). The integrated device 405 may be bare die (e.g., semiconductor bare die). The integrated device 403 may be a first integrated device (e.g., first chiplet), and the integrated device 405 may be a second integrated device (e.g., second chiplet). The integrated device 403 and the integrated device 405 are coupled to and touching the metallization portion 402. The front side of the integrated device 403 may face the metallization portion 402. The front side of the integrated device 405 may face the metallization portion 402. The encapsulation layer 106 may encapsulate the integrated device 403 and the integrated device 405. The encapsulation layer 106 may be coupled to the first surface of the metallization portion 402. The integrated device 403 may be configured to perform a first plurality of functions and/or operations. The integrated device 405 may be configured to perform a second plurality of functions and/or operations. The second plurality of functions and/or operations includes at least one function and/or operation that is different from the first plurality of functions and/or operations.
The bridge 808 is located at least partially in the metallization portion 402. The bridge 808 is coupled to the integrated device 403 and the integrated device 405. The bridge 808 may be coupled to the integrated device 403 and/or the integrated device 405 through hybrid bonding (e.g., copper to copper bonding, interconnect to interconnect bonding). In some implementations, the bridge 808 may be coupled to the integrated device 403 and/or the integrated device 405 through at least a plurality of solder interconnects (not shown). The front side of the integrated device 403 and the front side of the integrated device 405 may face the bridge 808. The bridge 808 may include a bridge substrate 880 and a plurality of bridge interconnects 882. The bridge 808 may include at least one dielectric layer 884. In some implementations, the bridge 808 may be a silicon based bridge. The bridge substrate 880 may include silicon. The plurality of bridge interconnects 882 may be coupled to the die pads (e.g., 430) of the integrated device 403 and the die pads (e.g., 450) of the integrated device 405.
The electrical path 816 includes a die interconnect from the integrated device 403, at least one bridge interconnect from the plurality of bridge interconnects 882 of the bridge 808 and a die interconnect from the integrated device 405.
The metallization portion 402 includes at least one dielectric layer 420 and a plurality of metallization interconnects 422. The bridge 808 may be located at least partially in the metallization portion 402. The plurality of metallization interconnects 422 may include a first plurality of metallization interconnects 422a, a second plurality of metallization interconnects 422b, a third plurality of metallization interconnects 422c, and a fourth plurality of metallization interconnects 422d.
The first plurality of metallization interconnects 422a may be similar to the first plurality of metallization interconnects 122a and/or the first plurality of metallization interconnects 222a. The third plurality of metallization interconnects 422c may be similar to the first plurality of metallization interconnects 122a and/or the first plurality of metallization interconnects 222a. The second plurality of metallization interconnects 422b may be similar to the second plurality of metallization interconnects 122b and/or the second plurality of metallization interconnects 222b. The fourth plurality of metallization interconnects 422d may be similar to the second plurality of metallization interconnects 122b and/or the second plurality of metallization interconnects 222b.
An electrical path between the integrated device 403 and the board 108 may include the electrical path 404. The electrical path 404 may include another board interconnect from the plurality of board interconnects 182, another solder interconnect from the plurality of solder interconnects 110, the second plurality of metallization interconnects 422b, and a second die interconnect from the integrated device 403. The electrical path 404 may be configured to provide an electrical path for power or ground.
An electrical path between the integrated device 405 and the board 108 may include the electrical path 412. The electrical path 412 may include a board interconnect from the plurality of board interconnects 182, a solder interconnect from the plurality of solder interconnects 110, the third plurality of metallization interconnects 422c, and a first die interconnect from the integrated device 405. The electrical path 412 may be configured to provide an electrical path for input/output signals.
An electrical path between the integrated device 405 and the board 108 may include the electrical path 414. The electrical path 414 may include another board interconnect from the plurality of board interconnects 182, another solder interconnect from the plurality of solder interconnects 110, the fourth plurality of metallization interconnects 422d, and a second die interconnect from the integrated device 405. The electrical path 414 may be configured to provide an electrical path for power or ground.
In some implementations, an electrical path between the integrated device 405 and the integrated device 403 may include a die interconnect from the integrated device 405, at least one metallization interconnect from the plurality of metallization interconnects 422 and a die interconnect from the integrated device 403.
It is noted that different portions of the metallization portion of a package may have different minimum interconnect thickness, minimum line and space dimensions, minimum pitches. In one example, the metallization portion may have the same global sets of minimum interconnect thickness, minimum line and space dimensions, and/or minimum pitches. In another example, the metallization portion includes (i) a first set of minimum interconnect thickness, minimum line and space dimensions, and/or minimum pitches, and (ii) a second set of minimum interconnect thickness, minimum line and space dimensions, and/or minimum pitches. For example, the second set of minimum interconnect thickness, minimum line and space dimensions, and/or minimum pitches may be located in a region of metallization portion that is vertically overlapping with one or more integrated devices. Some of the minimum dimensions may be local minimum dimensions for the metallization portion. Some of these minimum dimensions may be global dimensions for the metallization portion. Thus, different portions of the metallization portion may have different minimum interconnect thickness, different minimum line and space dimensions, and/or different minimum pitches.
It should be noted that the sequence of
Stage 1, as shown in
Stage 2 illustrates a state after an integrated device 403 and an integrated device 405 are placed on the carrier 500 and the adhesive coat 501. A pick and place process may be used to place the integrated device. The front side of the integrated device 403 and the front side of the integrated device 405 may be placed on the carrier 500 and the adhesive coat 501.
Stage 3 illustrates a state after an encapsulation layer 106 is formed over the carrier 500, the adhesive coat 501 the integrated device 403 and the integrated device 405. The encapsulation layer 106 may encapsulate the integrated device 103. The encapsulation layer 106 may include a mold, a resin and/or an epoxy. The encapsulation layer 106 may be a means for encapsulation. The encapsulation layer 106 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, once the encapsulation layer 106 is provided, portions of the encapsulation layer 106 may be removed. For example, a grinding process may be used to remove a top portion of the encapsulation layer 106, a back side of the integrated device 403 and/or a back side of the integrated device 405.
Stage 4 illustrates a state after the carrier 500 and the adhesive coat 501 are decoupled from the integrated device 403, the integrated device 405 and the encapsulation layer 106. The carrier 500 and the adhesive coat 501 may be detached from the integrated device 403, the integrated device 405 and the encapsulation layer 106.
Stage 5, as shown in
Stage 6 illustrates a state after the bridge 808 is coupled to the integrated device 403 and the integrated device 405. The bridge 808 may be coupled to the integrated device 403 and/or the integrated device 405 through hybrid bonding (e.g., copper to copper bonding, interconnect to interconnect bonding, metal to metal bonding) In some implementations, the bridge 808 may be coupled to the integrated device 403 and/or the integrated device 405 through at least a plurality of solder interconnects (not shown). The front side of the integrated device 403 and the front side of the integrated device 405 may face the bridge 808. The bridge 808 may include a bridge substrate 880 and a plurality of bridge interconnects 882. The bridge 808 may include at least one dielectric layer 884. In some implementations, the bridge 808 may be a silicon bridge. The bridge substrate 880 may include silicon. The plurality of bridge interconnects 882 may be coupled to the die pads (e.g., 430) of the integrated device 403 and the die pads (e.g., 450) of the integrated device 405.
Stage 7 illustrates a state after a metallization portion 402 is formed over the integrated device 403, the integrated device 405, the bridge 808 and the encapsulation layer 106. The metallization portion 402 may include at least one dielectric layer 420 and a plurality of metallization interconnects 422. The bridge 808 may be at least partially located in the metallization portion 402 and/or at least partially surrounded by the at least one dielectric layer 420 of the metallization portion 402. Stage 6 of
Stage 8 illustrates a state after the carrier 502 is decoupled from the integrated device 403, the integrated device 405 and the encapsulation layer 106. The carrier 502 may be detached from the integrated device 403, the integrated device 405 and the encapsulation layer 106.
Stage 9 illustrates a state after a plurality of solder interconnects 110 are coupled to the metallization portion 402. A solder reflow process may be used to couple the plurality of solder interconnects 110 to the plurality of metallization interconnects 222 of the metallization portion 202.
In some implementations, fabricating a package includes several processes.
It should be noted that the method 1000 of
The method provides (at 1005) a carrier. In some implementations, the carrier may be provided with an adhesive. Stage 1 of
The method places (at 1010) a front side of a first integrated device and a front side of second integrated device over the carrier. In some implementations, the front side of the integrated device(s) is placed over a carrier that includes and adhesive. In some implementations, two or more integrated devices may be placed over the carrier. Stage 2 of
The method forms (at 1015) an encapsulation layer that encapsulates the integrated devices. The encapsulation layer may be coupled to the integrated devices and the carrier. Stage 3 of
The method decouples (at 1020) the carrier from the encapsulation layer and the integrated devices. Stage 4 of
The method places (at 1025) a back side of the integrated devices and the encapsulation layer over another carrier (e.g., second carrier). The carrier may include an adhesive. Stage 5 of
The method couples (at 1030) a bridge to the integrated devices. For example, the bridge 808 is coupled to the integrated device 403 and the integrated device 405. The bridge 808 may be coupled to the integrated device 403 and/or the integrated device 405 through hybrid bonding (e.g., copper to copper bonding, interconnect to interconnect bonding, metal to metal bonding) In some implementations, the bridge 808 may be coupled to the integrated device 403 and/or the integrated device 405 through at least a plurality of solder interconnects. The front side of the integrated device 403 and the front side of the integrated device 405 may face the bridge 808. The bridge 808 may include a bridge substrate 880 and a plurality of bridge interconnects 882. The bridge 808 may include at least one dielectric layer 884. In some implementations, the bridge 808 may be a silicon bridge. The bridge substrate 880 may include silicon. The plurality of bridge interconnects 882 may be coupled to the die pads (e.g., 430) of the integrated device 403 and the die pads (e.g., 450) of the integrated device 405. Stage 6 of
The method forms (at 1035) a metallization portion that is coupled to the front side of the integrated devices and the encapsulation layer. The metallization portion may at least partially surround and/or encapsulate the bridge. The metallization portion may include at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects may include a first metallization interconnect on a first metal layer and a second metallization interconnect on a first metal layer, where the second interconnect has a second thickness that is different from a first thickness of the first metallization interconnect. Forming the metallization portion may include forming at least one dielectric layer and forming a first metallization interconnect on a first metal layer and a second metallization interconnect on a first metal layer. The second interconnect may have a second thickness that is different from a first thickness of the first metallization interconnect. Stage 7 of
The method couples (at 1040) a plurality of solder interconnects to the metallization interconnects of the metallization portion. Stage 9 of
One or more of the components, processes, features, and/or functions illustrated in
It is noted that the figures in the disclosure may represent actual representations and/or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and/or transistors. In some instances, the figures may not be to scale. In some instances, for purpose of clarity, not all components and/or parts may be shown. In some instances, the position, the location, the sizes, and/or the shapes of various parts and/or components in the figures may be exemplary. In some implementations, various components and/or parts in the figures may be optional.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another-even if they do not directly physically touch each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that an electrical current (e.g., signal, power, ground) may travel between the two objects. Two objects that are electrically coupled may or may not have an electrical current traveling between the two objects. The use of the terms “first”, “second”, “third” and “fourth” (and/or anything above fourth) is arbitrary. Any of the components described may be the first component, the second component, the third component or the fourth component. For example, a component that is referred to a second component, may be the first component, the second component, the third component or the fourth component. The term “encapsulating” means that the object may partially encapsulate or completely encapsulate another object. A first component that is “located” in a second component may mean that the first component is “partially located” in the second component or “completely located” in the second component. A first component that is “embedded” in a second component may mean that the first component is “partially embedded” in the second component or “completely embedded” in the second component. The terms “top” and “bottom” are arbitrary. A component that is located on top may be located over a component that is located on a bottom. A top component may be considered a bottom component, and vice versa. As described in the disclosure, a first component that is located “over” a second component may mean that the first component is located above or below the second component, depending on how a bottom or top is arbitrarily defined. In another example, a first component may be located over (e.g., above) a first surface of the second component, and a third component may be located over (e.g., below) a second surface of the second component, where the second surface is opposite to the first surface. It is further noted that the term “over” as used in the present application in the context of one component located over another component, may be used to mean a component that is on another component and/or in another component (e.g., on a surface of a component or embedded in a component). Thus, for example, a first component that is over the second component may mean that (1) the first component is over the second component, but not directly touching the second component, (2) the first component is on (e.g., on a surface of) the second component, and/or (3) the first component is in (e.g., embedded in) the second component. A first component that is located “in” a second component may be partially located in the second component or completely located in the second component. The term “about ‘value X’”, or “approximately value X”, as used in the disclosure means within 10 percent of the ‘value X’. For example, a value of about 1 or approximately 1, would mean a value in a range of 0.9-1.1.
In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and/or an under bump metallization (UBM) layer/interconnect. In some implementations, an interconnect may include an electrically conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground and/or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and/or sequences for forming the interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and/or a plating process may be used to form the interconnects.
Also, it is noted that various disclosures contained herein may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed.
In the following, further examples are described to facilitate the understanding of the invention.
Aspect 1: A package comprising an integrated device; a substrate coupled to the integrated device through at least a first plurality of solder interconnects; and a metallization portion coupled to the substrate through at least a second plurality of solder interconnects. The metallization portion comprises at least one dielectric layer; and a plurality of metallization interconnects comprising a first metallization interconnect located on a first metal layer, wherein the first metallization interconnect includes a first thickness; and a second metallization interconnect located on the first metal layer, wherein the second metallization interconnect includes a second thickness that is different from the first thickness.
Aspect 2: The package of aspect 1, wherein the second thickness is greater than the first thickness.
Aspect 3: The package of aspect 2, wherein the second thickness is at least 1.2 times greater than the first thickness.
Aspect 4: The package of aspects 1 through 3, wherein the plurality of metallization interconnects comprise a third metallization interconnect located on a second metal layer; a fourth metallization interconnect located on the second metal layer; a first via metallization interconnect coupled to the first metallization interconnect and the third metallization interconnect, wherein the first via metallization interconnect comprises a first via height; and a second via metallization interconnect coupled to the second metallization interconnect and the fourth metallization interconnect, wherein the second via metallization interconnect comprises a second via height that is different from the first via height.
Aspect 5: The package of aspect 4, wherein the second thickness is greater than the first thickness, and wherein the first via height is greater than the second via height.
Aspect 6: The package of aspects 4 through 5, wherein the second metal layer is adjacent to the first metal layer.
Aspect 7: The package of aspects 4 through 6, wherein the first via metallization interconnect includes a first minimum diameter, and wherein the second via metallization interconnect includes a second minimum diameter that is greater than the first minimum diameter.
Aspect 8: The package of aspects 4 through 7, wherein the third metallization interconnect includes a third thickness, and wherein the fourth metallization interconnect includes a fourth thickness that is greater than the third thickness.
Aspect 9: The package of aspects 4 through 8, wherein the plurality of metallization interconnects comprise a fifth metallization interconnect located on a third metal layer, wherein the fifth metallization interconnect includes a fifth thickness; a sixth metallization interconnect located on the third metal layer, wherein the sixth metallization interconnect includes a sixth thickness that is greater than the fifth thickness; a third via metallization interconnect coupled to the fifth metallization interconnect and the third metallization interconnect, wherein the third via metallization interconnect comprises a third via height; and a fourth via metallization interconnect coupled to the sixth metallization interconnect and the fourth metallization interconnect, wherein the fourth via metallization interconnect comprises a fourth via height that is different from the third via height.
Aspect 10: The package of aspects 4 through 9, wherein the first metallization interconnect, the first via metallization interconnect and the third metallization interconnect are part of an electrical path for input/output signals to and/or from the integrated device, and wherein the second metallization interconnect, the second via metallization interconnect and the fourth metallization interconnect are part of an electrical path for power to the integrated device.
Aspect 11: The package of aspects 1 through 10, wherein the substrate includes an interposer comprising a plurality of interposer interconnects.
Aspect 12: The package of aspects 1 through 11, further comprising a second integrated device coupled to the substrate through at least a third plurality of solder interconnects, wherein the integrated device is a first chiplet, and wherein the second integrated device is a second chiplet.
Aspect 13: The package of aspect 12, wherein the plurality of metallization interconnects comprise a first plurality of metallization interconnects comprising a first minimum thickness, a first minimum spacing, a first minimum pitch and/or a first minimum width, wherein the first plurality of metallization interconnects include interconnects that vertically overlap with the first integrated device and the second integrated device; and a second plurality of metallization interconnects comprising a second minimum thickness, a second minimum spacing, a second minimum pitch and/or a second minimum width, wherein the metallization portion includes a redistribution portion, wherein the first metallization interconnect includes a first redistribution interconnect, and wherein the second metallization interconnect includes a second redistribution interconnect.
Aspect 14: A package comprising a first integrated device; a second integrated device; a bridge coupled to the first integrated device and the second integrated device; and a metallization portion coupled to the first integrated device and/or the second integrated device. The metallization portion comprises at least one dielectric layer; and a plurality of metallization interconnects comprising a first metallization interconnect located on a first metal layer, wherein the first metallization interconnect includes a first thickness; and a second metallization interconnect located on the first metal layer, wherein the second metallization interconnect includes a second thickness that is different from the first thickness.
Aspect 15: The package of aspect 14, wherein the second thickness is greater than the first thickness.
Aspect 16: The package of aspect 15, wherein the second thickness is at least 1.2 times greater than the first thickness.
Aspect 17: The package of aspects 14 through 16, wherein the plurality of metallization interconnects comprise a third metallization interconnect located on a second metal layer; a fourth metallization interconnect located on the second metal layer; a first via metallization interconnect coupled to the first metallization interconnect and the third metallization interconnect, wherein the first via metallization interconnect comprises a first via height; and a second via metallization interconnect coupled to the second metallization interconnect and the fourth metallization interconnect, wherein the second via metallization interconnect comprises a second via height that is different from the first via height.
Aspect 18: The package of aspect 17, wherein the second thickness is greater than the first thickness, and wherein the first via height is greater than the second via height.
Aspect 19: The package of aspects 17 through 18, wherein the first via metallization interconnect includes a first maximum diameter, and wherein the second via metallization interconnect includes a second maximum diameter that is less than the first maximum diameter.
Aspect 20: The package of aspects 14 through 19, wherein the bridge is located in the metallization portion.
Aspect 21: The package of aspect 20, wherein the bridge includes a silicon based bridge.
Aspect 22: The package of aspects 20 through 21, wherein the first integrated device and the second integrated device are configured to be electrically coupled to each other through an electrical path that includes the bridge.
Aspect 23: The package of aspects 20 through 22, wherein the bridge includes a silicon based bridge, wherein the first integrated device comprises a first technology node, and wherein the second integrated device comprises a second technology node.
Aspect 24: The package of aspects 14 through 23, wherein the plurality of metallization interconnects comprise a first plurality of metallization interconnects comprising a first minimum thickness, a first minimum spacing, a first minimum pitch and/or a first minimum width; and a second plurality of metallization interconnects comprising a second minimum thickness, a second minimum spacing, a second minimum pitch and/or a second minimum width.
Aspect 25: The package of aspect 24, wherein the first plurality of metallization interconnects include interconnects that vertically overlap with the first integrated device and the second integrated device.
Aspect 26: The package of aspects 14 through 25, wherein the package is implemented in a device is that is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.
The various features of the disclosure described herein can be implemented in different systems without departing from the disclosure. It should be noted that the foregoing aspects of the disclosure are merely examples and are not to be construed as limiting the disclosure. The description of the aspects of the present disclosure is intended to be illustrative, and not to limit the scope of the claims. As such, the present teachings can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.
This application claims priority to and the benefit of Provisional Application Ser. No. 63/491,985 filed in the United States Patent and Trademark Office on Mar. 24, 2023, the entire content of which is incorporated herein by reference as if fully set forth below in its entirety and for all applicable purposes.
| Number | Date | Country | |
|---|---|---|---|
| 63491985 | Mar 2023 | US |
