1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to apparatus and methods of reducing capacitive-based impedance discontinuity in semiconductor chip carrier substrates.
2. Description of the Related Art
Packaged integrated circuits often consist of one or more semiconductor chips mounted to a package or carrier substrate. The carrier substrate includes plural input/outputs designed to interface with input/outputs of a printed circuit board (PCB) of one sort or another. The input/outputs convey power, ground and signals. A typical conventional carrier substrate includes several conductor layers or planes stacked and interwoven with insulating material. Some of these planes are devoted to power and others to ground. Still other conductor pathways in the carrier substrate are slated for signals.
A typical signal propagation channel consists of a PCB, a PCB socket, and a carrier substrate. The conductor planes carrying ground or power in the carrier substrate tend to be large in order to efficiently convey current. However, the current carrying efficiency comes with a penalty in the form of significant electrical parasitics which hamper the quality of signals propagating on the signals channels associated with the carrier substrate, particularly at higher frequencies.
One conventional technique for reducing the capacitive coupling between, for example, a carrier substrate pin pad slated for signals and an overlying conductor plane is to form a large hole in the conductor plane and position a via through the hole. The hole reduces the capacitive overlap area with the underlying pin pad. Such holes can be numerous for a given conductor plane if there are many signal pins and reduce the current carrying capability of the conductor plane.
Another conventional technique employs silicon level equalization techniques such as transmitter de-emphasis and receiver filtering in circuit design to compensate for the parasitics of the signal channels. This technique presents very challenging design complexities, particularly at higher frequencies or data rates of operation.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
In accordance with one aspect of the present invention, a method of manufacturing is provided that includes assembling a semiconductor chip carrier substrate with a first input/output site adapted to electrically connect to an external component and a second input/output site adapted to electrically connect to an input/output site of a semiconductor chip. An inductor is placed in the semiconductor chip carrier substrate. The inductor is electrically connected between the first input/output site or the second input/output site and a first conductor in the carrier substrate. The inductor has a preselected inductance to reduce an impedance discontinuity between the first input/output site or the second input/output site due to coupling to a second conductor in the semiconductor chip carrier substrate.
In accordance with another aspect of the present invention, a method of manufacturing is provided that includes forming a first conductor plane in a semiconductor chip carrier substrate. A first input/output site is formed on the semiconductor chip carrier substrate and adapted to electrically connect to an external component. A second input/output site is formed on the semiconductor chip carrier substrate and adapted to electrically connect to an input/output site of a semiconductor chip. A conductive pathway is formed between the first and second input/output sites. An inductor is formed in the semiconductor chip carrier substrate and the conductive pathway. The inductor has a preselected inductance to reduce an impedance discontinuity between the first input/output site or the second input/output site and a conductor in the carrier substrate due to coupling to the first conductor plane.
In accordance with another aspect of the present invention, an apparatus is provided that includes a semiconductor chip carrier substrate that has a first input/output site adapted to electrically connect to an external component and a second input/output site adapted to electrically connect to an input/output site of a semiconductor chip. An inductor is in the semiconductor chip carrier substrate and electrically connected between the first input/output site or the second input/output site and a first conductor in the carrier substrate. The inductor has a preselected inductance to reduce an impedance discontinuity between the first input/output site or the second input/output site and the first conductor due to coupling to a second conductor in the semiconductor chip carrier substrate.
The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:
In the drawings described below, reference numerals are generally repeated where identical elements appear in more than one figure. Turning now to the drawings, and in particular to
The package substrate 30 provides electrical connectivity between the semiconductor chip 25 and the printed circuit board 20 by way of the socket 15. The printed circuit board 20 may be virtually any type of printed circuit board, such as a motherboard, a circuit card or the like. The socket 15 is depicted as a pin grid array socket. However, ball grid arrays, land grid arrays or other types of interconnects could be used.
In this illustrative embodiment, the semiconductor chip 25 is electrically connected to the carrier substrate 30 by way of a plurality of solder joints, a few of which are visible and labeled 35a, 35b, 35c, 35d, 35e, 35f and 35g. The following description of the solder joint 35a will be illustrative of the others 35b, 35c, 35d, 35e, 35f and 35g. The solder joint 35a is sandwiched between a conductor pad 37a of the semiconductor chip 25 and a conductor pad 39a of the carrier substrate 30. The conductor pad 37a provides an input/output site for electrical signals, power or ground. The pads 37a and 39a may be composed of various conductor materials, such as copper, gold, silver, aluminum, platinum, palladium, molybdenum, combinations of these or the like. The solder joint 35a may be composed of lead-based solders, lead-free solders, or combinations of the two. It should be understood that other types of interconnection schemes could be used, such as, conductive pillars, wire bonds or other interconnects as desired.
The carrier substrate 30 may be composed of ceramics or organic materials as desired. If organic, the substrate 30 may actually consist of multiple layers of metallization and dielectric materials. The substrate 30 may interconnect electrically with external devices, such as the socket 15, in a variety of ways, such as the depicted pin grid array, or optionally a land grid array, a ball grid array or other configuration. The number of individual layers for the substrate 30 is largely a matter of design discretion. In certain exemplary embodiments, the number of layers may vary from two to sixteen. If such a build-up design is selected, a standard core, thin core or coreless arrangement may be used. The dielectric materials may be, for example, epoxy resin with or without fiberglass fill. For simplicity of illustration, the illustrative embodiment of the package substrate 30 is shown with three layers 45, 50 and 55. To establish electrical contact with the socket 15, the substrate 30 is provided with a plurality of conductor pins, a few of which are visible and labeled 60a, 60b, 60c, 60d, 60e, 60f and 60g. The pins 60a, 60b, 60c, 60d, 60e, 60f and 60g are coupled to respective conductor pads, two of which are labeled 65a and 65g, respectively, and seat in respective socket holes of the socket 15, two of which are labeled 70a and 70g, respectively. In this example, the conductor pads 65a and 65g serve as input/output sites for electrical signals and the unlabeled conductor pads for the pins 60b, 60c, 60d, 60e and 60f serve as input/output sites for power or ground. In terms of composition, the conductor pads 65a and 65g may be like the conductor pads 37a and 39a described above. It should be understood that there may be large numbers of pins, solder joints and conductor pads.
The electrical pathways between the pins 60a, 60b, 60c, 60d, 60e, 60f and 60g and the solder joints 35a, 35b, 35c, 35d, 35e, 35f and 35g are provided by way of an interconnect system 80 in the package substrate 30. The interconnect system 80 may consist of several stacked layers of conductor planes and traces interconnected vertically by vias. The basic function of the interconnect system is to carry power and signals and provide a ground path between the semiconductor chip 25 and the pins 60a, 60b, 60c, 60d, 60e, 60f and 60g. It should be understood that the interconnect system 80 may include large numbers of conductor planes, traces and vias. However in this simplified example, the interconnect system 80 includes a conductor plane 85 positioned below a plurality of conductor traces, two of which are labeled 90a and 90g, respectively. The conductor plane 85 may connect the solder joints 35b, 35c, 35d, 35e and 35f to either power or ground by way of the pins 60b, 60c, 60d, 60e and 60f. If desired, the conductor plane 85 may be formed substantially like a conductive sheet that may extend across the entire expanse of the package substrate 30.
The conductor traces 90a and 90g in this example are slated to carry signals and thus should not be electrically connected to the conductor plane 85. The conductor trace 90a may be connected to the pin pad 65a by a via 95a, a via 100a and a tuning inductor 105a connected between the vias 95a and 100a. A via 107a connects the conductor trace 90a to the solder joint 35a. Another via 107g connects the conductor trace 90g to the solder joint 35g. To avoid shorting to the conductor plane 85, a cutout 110a is formed in the conductor plane 85 for the tuning inductor 105a. In a conventional design to be discussed in more detail below, the vias 95a and 100a would be merged and simply pass through the cutout 110a. However, in this illustrative embodiment, the tuning inductor 105a is positioned between the vias 100a and 95a to provide the capacity to tune out undesirable impedance discontinuity resulting from capacitive coupling between the conductor plane 85 and the underlying pin pad 65a. A corresponding tuning inductor 105g is provided in a cutout 110g in the conductor plane 85 between the vias 95g and 100g connecting the conductor trace 90g to the pin pad 65g.
Assume for the purposes of this illustration that an external component 120 is positioned on the printed circuit board 20 and electrically connected to the socket hole 70a, and thus the pin 60a, by way of a transmission line 125. The transmission line 125 is shown as a simplified electrical line, however, the transmission line 125 may be fabricated by a complex interconnect scheme on and/or in the printed circuit board 20 that is not unlike the interconnect scheme 80 associated with the package substrate 30, albeit, on a larger scale. The external component 120 may be virtually any type of integrated circuit that may be used in conjunction with the semiconductor chip package 10 and may function as a driver, a receiver or both. At this point, note the location of the dashed oval 130. The portion of
Attention is now turned to
However, the impedance discontinuity caused by this capacitive coupling Cpp may be effectively tuned away by the incorporation of the inductor 105a.
Attention is now turned again to
A three dimensional depiction of one exemplary embodiment of the inductor 105a may be understood by referring now to
Additional detail of the exemplary inductor 105a may be understood by referring now to
In another alternate exemplary embodiment depicted in
It may be useful at this juncture to contrast the tuned inductor design of the disclosed embodiments with a conventional pin pad to overlying conductor plane electrical pathway. In this regard, attention is now turned to
An exemplary method for fabricating any of the tuning inductors 105a, 105g and 105a′ disclosed herein may be understood by referring now to
Next and as shown in
Finally, and as shown in
The skilled artisan will appreciate that the same process would be used regardless of the particular shape of the inductor 105a or the type of interface connected to the pad 65a, such as a pin, a land grid or ball grid, a ball, etc. Furthermore, the number and locations of the tuning inductors used may be varied. For example, tuning inductors could be electrically connected between carrier substrate input/output (I/O) sites slated for chip connection and substrate conductors or between carrier substrate I/O sites slated for external component connection and substrate conductors. Different sizes and inductances can be selected for different tuning inductors. While the via pathways between a given I/O pad have been depicted as being generally vertically aligned, other geometries can be used with the disclosed tuning inductors.
While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.