The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. The individual dies are typically packaged separately. A package not only provides protection for semiconductor devices from environmental contaminants, but also provides a connection interface for the semiconductor devices packaged therein.
Three-dimensional integrated circuits (3DICs) are a recent development in semiconductor packaging in which multiple semiconductor dies are stacked upon one another, using package-on-package (POP) and system-in-package (SiP) packaging techniques. Some 3DICs are prepared by placing dies over dies on a semiconductor wafer level. 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked dies, for example. However, there are many challenges related to 3DICs.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Embodiments of package structures and method for forming the same are provided. The package structure includes a first alignment mark and a second alignment mark corresponding to each other. Each of the first alignment mark and the second alignment mark includes a first group and a second group extending in two directions. Accordingly, the two-dimensional (2D) alignment may be achieved. In addition, a plurality of sub-alignment marks are provided in the first alignment mark and the second alignment mark, and therefore different resolution of may be obtained.
In addition, a first bonding film 110 is formed over the first package component 100 for the subsequent bonding process. For example, the material of the first bonding film 110 includes SiON, SiO2, any other suitable material, or a combination thereof. In some embodiments, a patterned photoresist layer (not shown) is formed over the first bonding film 110. The patterned photoresist layer may be formed by a deposition process and a patterning process. The deposition process for forming the patterned photoresist layer may include a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, a sputtering process, or another applicable process. The patterning process for forming the patterned photoresist layer may include a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, and drying (e.g., hard baking). The etching process may include a dry etching process or a wet etching process. Then, the first package component 100 may be recessed by performing an etching process, using the patterned photoresist layer as a mask, and a plurality of first trenches 115 are formed in the first bonding film 110. The etching process may be a dry etching process or a wet etching process. In some embodiments, the dry etching process includes using a fluorine-based etchant gas, such as SF6, CxFy, NF3 or a combination thereof. The etching process may be a time-controlled process. Afterwards, the patterned photoresist layer is removed.
In some embodiments, each of the first trenches 115 has a bottom surface 115B and a sidewall 115S that is connected to the bottom surface 115B. For example, the exemplary sidewall 115S is substantially perpendicular to the bottom surface 115B. However, the present disclosure is not limited thereto. The first trenches 115 are separated from each other by a part of the first bonding film 110. In some embodiments, the part of the first bonding film 110 is sandwiched between the adjacent first trenches 115 in a horizontal direction (for example, parallel to the X axis). In some embodiments, the depth of the first trenches 115 is less than the thickness of the first bonding film 110. That is, the first trenches 115 may not penetrate the first bonding film 110 and expose the underlying first package component 100. However, the present disclosure is not limited thereto. In some embodiments, the first trenches 115 are formed to have the same width in the direction parallel to the X-Y plane. In some embodiments, the first trenches 115 are formed with a constant interval. Accordingly, the spacing between the first trenches 115 is constant in the direction parallel to the X-Y plane. However, the present disclosure is not limited thereto.
Then, as shown in
For example, the first dielectric material 122 includes one or more sub-dielectric layers formed of materials such as silicon dioxide (SiO2), Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like. In some embodiments, the first dielectric material 122 is formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. However, the present disclosure is not limited thereto. Any suitable material and method for the formation of the first dielectric material 122 is contemplated within the scope of the present disclosure.
As shown in
As shown in
In some embodiments, the first alignment mark 120 may be formed by the first trenches 115, and the first dielectric material 122 and the first conductive material 124 may be omitted. The detail of the bonding process is further discussed in the following paragraphs in accompany with
In some embodiments, the first alignment mark 120 has a first axis C1, and the second alignment mark 220 has a second axis C2. To be more specific, the first axis C1 is perpendicular to the top surface 110T of the first bonding film 110. Similarly, the second axis C2 is perpendicular to the top surface 210T of the second bonding film 210. As shown in
In some embodiments, in the top view (for example, shown in
In addition, each of the first patterns 125A is divided into a first portion 125A1 and a second portion 125A2 connected to the first portion 125A1. However, the present disclosure is not limited thereto. In some embodiments, the first portions 125A1 of the first patterns 125A may be disconnected from the second portions 125A2 of the first patterns 125A. For example, the width of the first portions 125A1 and/or the second portions 125A2 is in a range from about 0.1 μm to about 10 μm, but the present disclosure is not limited thereto. The first portions 125A1 of the first patterns 125A are separated by a first pitch PA1. The second portions 125A2 of the first patterns 125A are separated by a second pitch PA2. The first pitch PA1 is different from the second pitch PA2. In some embodiments, a standard pattern 125AC is selected in the first group of the first patterns 125A. To be more specific, the standard pattern 125AC includes a first portion 125A1 and a second portion 125A2 that are aligned with each other in the second direction (such as the direction parallel to the Y axis). That is to say, one of the edges of the first portion 125A1 and a corresponding one of the edges of the second portion 125A2 form a straight line in the standard pattern 125AC.
In some embodiments, in the top view (for example, shown in
In the present embodiment, the first pitch PA1 is in a range from about 0.1 μm to about 10 μm, such as about 2.0 μm. In addition, and the second pitch PA2 is in a range from about 0.1 μm to about 10 μm, such as about 2.1 μm. In some embodiments, the first pitch PA1 is different from (for example, shorter than) the second pitch PA2. In some embodiments, the difference between the first pitch PA1 and the second pitch PA2 is, for example, about 0.1 μm. However, the present disclosure is not limited thereto. Other possible values of the difference between the first pitch PA1 and the second pitch PA2 are included within the scope of the present disclosure and will not be listed one-by-one below. For example, the first pitch PA1 and the second pitch PA2 are interchangeable, so that in some embodiments the first pitch PA1 may be greater than the second pitch PA2. It should be noted that the difference between the first pitch PA1 and the second pitch PA2 may determine the resolution of the misalignment error (for example, the shift between the first alignment mark 120 and the second alignment mark 220). The determination of a misalignment error is discussed further in the following paragraphs.
In some embodiments, the second sub-alignment mark 120B of the first alignment mark 120 includes a plurality of first patterns 125B. It should be noted that although the first patterns 125B are each illustrated as a one-piece structure in the present embodiment, the present disclosure is not limited thereto. That is the first patterns 125B may include a first portion and a second portion that are disconnected from each other. For example, the width of the first patterns 125B is in a range from about 0.1 μm to about 10 μm, but the present disclosure is not limited thereto. For example, a first group of the first patterns 125B are arranged in the first direction (such as a direction parallel to the X axis), and a second group of the first patterns 125B are arranged in a second direction (such as the direction parallel to the Y axis) that is substantially perpendicular to the first direction. Accordingly, the first alignment mark 120 may be used to align two components of the package structure in two dimensions.
In addition, the first patterns 125B are separated by a first pitch PB1. In some embodiments, a standard pattern 125BC is selected in the first group of the first patterns 125B. In some embodiments, in the top view (for example, shown in
In some embodiments, the third sub-alignment mark 120C of the first alignment mark 120 includes a plurality of first patterns 125C. For example, a first group of the first patterns 125C are arranged in the first direction (such as a direction parallel to the X axis), and a second group of the first patterns 125C are arranged in a second direction (such as a direction parallel to the Y axis) that is substantially perpendicular to the first direction. Accordingly, the first alignment mark 120 may be used to align two components of the package structure in two dimensions.
In addition, each of the first patterns 125C is divided into a first portion 125C1 and a second portion 125C2 connected to the first portion 125C1. However, the present disclosure is not limited thereto. In some embodiments, the first portions 125C1 of the first patterns 125C may be disconnected from the second portions 125C2 of the first patterns 125C. For example, the width of the first portions 125C1 and/or the second portions 125C2 is in a range from about 0.1 μm to about 10 μm, but the present disclosure is not limited thereto. The first portions 125C1 of the first patterns 125C are separated by a first pitch PC1. The second portions 125C2 of the first patterns 125C are separated by a second pitch PC2. The first pitch PC1 is different from the second pitch PC2. In some embodiments, a standard pattern 125CC is selected in the first group of the first patterns 125C. To be more specific, the standard pattern 125CC includes a first portion 125C1 and a second portion 125C2 that are aligned with each other in the second direction (such as the direction parallel to the Y axis). That is to say, one of the edges of the first portion 125C1 and a corresponding one of the edges of the second portion 125C2 form a straight line in the standard pattern 125CC.
In some embodiments, in the top view (for example, shown in
In the present embodiment, the first pitch PC1 is in a range from about 0.1 μm to about 10 μm, such as about 2.0 μm. In addition, and the second pitch PC2 is in a range from about 0.1 μm to about 10 μm, such as about 2.02 μm. In some embodiments, the first pitch PC1 is different from (for example, shorter than) the second pitch PC2. In some embodiments, the difference between the first pitch PC1 and the second pitch PC2 is, for example, about 0.02 μm. However, the present disclosure is not limited thereto. Other possible values of the difference between the first pitch PC1 and the second pitch PC2 are included within the scope of the present disclosure and will not be listed one-by-one below. For example, the first pitch PC1 and the second pitch PC2 are interchangeable, so that in some embodiments the first pitch PC1 may be greater than the second pitch PC2.
It should be noted that the difference between the first pitch PC1 and the second pitch PC2 may determine the resolution of the misalignment error (for example, the shift between the first alignment mark 120 and the second alignment mark 220). In particular, compared with the first pitch PA1 and the second pitch PA2, the first pitch PC1 and the second pitch PC2 are shorter and may achieve higher resolution of the misalignment error. The determination of a misalignment error is discussed further in the following paragraphs.
In some embodiments, the fourth sub-alignment mark 120D of the first alignment mark 120 includes a first pattern 125D, which has a cross profile in the top view (for example, shown in
In some embodiments, in the top view (for example, shown in
In addition, each of the second patterns 225A is divided into a first portion 225A1 and a second portion 225A2 connected to the first portion 225A1. However, the present disclosure is not limited thereto. In some embodiments, the first portions 225A1 of the second patterns 225A may be disconnected from the second portions 225A2 of the second patterns 225A. For example, the width of the first portions 225A1 and/or the second portions 225A2 is in a range from about 0.1 μm to about 10 μm, but the present disclosure is not limited thereto. The first portions 225A1 of the second patterns 225A are separated by the second pitch PA2. The second portions 225A2 of the second patterns 225A are separated by the first pitch PA1. In some embodiments, a standard pattern 225AC is selected in the first group of the second patterns 225A. To be more specific, the standard pattern 225AC includes a first portion 225A1 and a second portion 225A2 that are aligned with each other in the second direction (such as the direction parallel to the Y axis). That is to say, one of the edges of the first portion 225A1 and a corresponding one of the edges of the second portion 225A2 form a straight line in the standard pattern 225AC.
In some embodiments, in the top view (for example, shown in
In some embodiments, the second sub-alignment mark 220B of the second alignment mark 220 includes a plurality of second patterns 225B. For example, a first group of the second patterns 225B are arranged in the first direction (such as a direction parallel to the X axis), and a second group of the second patterns 225B are arranged in a second direction (such as the direction parallel to the Y axis) that is substantially perpendicular to the first direction. Accordingly, the second alignment mark 220 may be used to align two components of the package structure in two dimensions and correspond to the first alignment mark 120.
In addition, the second patterns 225B each include a first portion 225B1 and a second portion 225B2. For example, the width of the first portions 225B1 and/or the second portions 225B2 is in a range from about 0.1 μm to about 10 μm, but the present disclosure is not limited thereto. In some embodiments, the first portions 225B1 of the second patterns 225B are separated by a second pitch PB2, and the second portions 225B2 of the second patterns 225B are separated by a third pitch PB3. In some embodiments, the second pitch PB2 is different from the third pitch PB3. In the present embodiment, the second pitch PB2 is in a range from about 0.1 μm to about 10 μm, such as about 2.1 μm. The third pitch PB3 is in a range from about 0.1 μm to about 10 μm, such as about 2.0 μm. For example, the relationship among the first pitch PB1, the second pitch PB2, and the third pitch PB3 are reversable, so that in some embodiments the first pitch PC1 may be shorter than the second pitch PB2 and/or the third pitch PB3. In some embodiments, a standard pattern 225BC is selected in the first group of the second patterns 225B. In some embodiments, in the top view (for example, shown in
In some embodiments, the third sub-alignment mark 220C of the second alignment mark 220 includes a plurality of second patterns 225C. For example, a first group of the second patterns 225C are arranged in the first direction (such as a direction parallel to the X axis), and a second group of the second patterns 225C are arranged in a second direction (such as a direction parallel to the Y axis) that is substantially perpendicular to the first direction. Accordingly, the second alignment mark 220 may be used to align two components of the package structure in two dimensions and correspond to the first alignment mark 120.
In addition, each of the second patterns 225C is divided into a first portion 225C1 and a second portion 225C2 connected to the first portion 225C1. However, the present disclosure is not limited thereto. In some embodiments, the first portions 225C1 of the second patterns 225C may be disconnected from the second portions 225C2 of the second patterns 225C. For example, the width of the first portions 225C1 and/or the second portions 225C2 is in a range from about 0.1 μm to about 10 μm, but the present disclosure is not limited thereto. The first portions 225C1 of the second patterns 225C are separated by the second pitch PC2. The second portions 225C2 of the second patterns 225C are separated by the first pitch PC1. In some embodiments, a standard pattern 225CC is selected in the first group of the second patterns 225C. To be more specific, the standard pattern 225CC includes a first portion 225C1 and a second portion 225C2 that are aligned with each other in the second direction (such as the direction parallel to the Y axis). That is to say, one of the edges of the first portion 225C1 and a corresponding one of the edges of the second portion 225C2 form a straight line in the standard pattern 225CC.
In some embodiments, in the top view (for example, shown in
In some embodiments, the fourth sub-alignment mark 220D of the second alignment mark 220 includes a plurality of second pattern 225D, each of which has a rectangular profile in the top view (for example, shown in
Although the detail structures of the first alignment mark 120 and the second alignment mark 220 are discussed above, the present disclosure is not limited thereto. It should be noted that the structures of the first alignment mark 120 and the second alignment mark 220 are interchangeable. For example, the second alignment mark 220 may be formed at the top of the overall package structure 10 and the first alignment mark 120 may be formed at the bottom of the overall package structure 10.
As set forth above, various alignment marks are provided. It should be noted that it may not be necessary to include all kinds of alignment marks which are discussed above, one or more alignment marks described in the present disclosure may be selected for alignment of the package structure 10.
As shown in
The misalignment error=The resolution*The inversion point of light signal
In some embodiments, the inversion point of light signal may be identified as the two elongated patterns that are most aligned and have the widest spacing therebetween. Accordingly, the misalignment error may be obtained rapidly and the risk of miscalculating the misalignment error may be reduced.
In some embodiments, the misalignment error may be determined by identifying the centers of the first sub-alignment mark 120A and the first sub-alignment mark 220A and calculating the overlay (or misalignment) between the centers of the first sub-alignment mark 120A and the first sub-alignment mark 220A. In particular, the center of the first sub-alignment mark 120A may be identified by averaging the position of the centers of the first patterns 125A. For example, thirteen first patterns 125A are shown in this embodiment, and the positions of the centers of these first patterns 125A are averaged to obtain the averaged center of the first sub-alignment mark 120A. Similarly, the averaged center of the first sub-alignment mark 220A may be obtained in the same manner.
In some embodiments, the misalignment error may be determined by the following formula:
The misalignment error=The number of the first patterns 125A or the second patterns 225A*Pitch Difference between the first patterns 125A and the second pattern 225A (i.e. the pitch difference between the pitch PA1 and the pitch PA2)−Pitch Difference/2
Accordingly, the misalignment error may be obtained rapidly and the risk of miscalculating the misalignment error may be reduced. In some embodiments, the number of the first patterns 125A or the second patterns 225A in a range from 10 to 100 on each side.
As shown in
As shown in
The misalignment error=The resolution*The inversion point of light signal
In some embodiments, the inversion point of light signal may be identified as the two elongated patterns that are most aligned and have the widest spacing therebetween. Accordingly, the misalignment error may be obtained rapidly and the risk of miscalculating the misalignment error may be reduced.
As shown in
The misalignment error=The resolution*The inversion point of light signal
In some embodiments, the inversion point of light signal may be identified as the two elongated patterns that are most aligned and have the widest spacing therebetween. Accordingly, the misalignment error may be obtained rapidly and the risk of miscalculating the misalignment error may be reduced.
In some embodiments, an interconnect structure 315 is formed in the first package component 300. In some embodiments, the interconnect structure 315 includes a plurality of through-silicon via (TSV) structures 310, a plurality of metallization patterns 312, and a plurality of conductive features 314. In some embodiments, the TSV structures 310 are formed in the first package component 300 and a dielectric layer 302 formed on the first package component 300. However, the present disclosure is not limited thereto. In some other embodiments, the dielectric layer 302 may be omitted, and the TSV structures 310 are completely located in the first package component 300.
In some embodiments, the dielectric layer 302 includes one or more sub-dielectric layers formed of materials such as silicon dioxide (SiO2), Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like. In some embodiments, the dielectric layer 302 is formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like.
In some embodiments, the formation of the TSV structures 310 includes forming a plurality of trenches in the first package component 300. In some embodiments, the trenches extend into the first package component 300 and penetrate the dielectric layer 302 (if present) to electrically and physically couple the overlying metallization patterns 312. In some other embodiments, the TSV structures 310 may have a rectangular profile in the cross-sectional view. In some embodiments, the TSV structures 310 are formed of tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination thereof. However, the present disclosure is not limited thereto.
The metallization patterns 312 and the conductive features 314 are surrounded by a dielectric layer 304 for proper insulation, reducing the probability of forming short-circuit. In some embodiments, the dielectric layer 304 includes one or more sub-dielectric layers formed of materials such as silicon dioxide (SiO2), Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like. In some embodiments, the dielectric layer 304 is formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the dielectric layer 304 is formed by using material or method that is the same as that of the dielectric layer 302. However, the present disclosure is not limited thereto. In some embodiments, the dielectric layer 304 is formed by using material or method that is different from that of the dielectric layer 302.
In some embodiments, one or more devices (not individually shown) are in the formed in first package component 300 or the overlying dielectric layers 302, 304, and electrically connected to the TSV structures 310, the metallization patterns 312, and/or the conductive features 314. In some embodiments, the devices are active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. For example, the devices are metal-oxide-semiconductor field-effect transistor (MOSFET), in accordance with some embodiments of the present disclosure.
In some embodiments, the metallization patterns 312 include metal lines and the conductive features 314 include vias formed in the dielectric layer 304. For example, the metallization patterns 312 and/or the conductive features 314 include conductive material such as tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination thereof. In some embodiments, the TSV structures 310, the metallization patterns 312, and/or the conductive features 314 are formed of the same material. In some other embodiments, the TSV structures 310, the metallization patterns 312, and/or the conductive features 314 are formed of different materials.
Accordingly, the TSV structures 310 is electrically connected to the metallization patterns 312 and the conductive features 314 for forming a conductive path connected to external environment (e.g. another semiconductor die or external devices). For example, when the devices in the first package component 300 are transistors, the TSV structures 310 may couple the gates or source/drain regions of the transistors. Source/drain regions may refer to a source or a drain, individually or collectively dependent upon the context.
In addition, a bonding film 320 is formed over the first package component 300 for the bonding process. For example, the material of the bonding film 320 includes SiON, SiO2, any other suitable material, or a combination thereof. In some embodiments, a plurality of bonding pads 322 are formed in the bonding film 320. For example, the bonding pads 322 include conductive material such as tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination thereof. In some embodiments, the bonding pads 322 are formed corresponding to a second package component 400. However, the present disclosure is not limited thereto. In some embodiments, a first alignment mark 330 may be formed in the bonding film 320 and adjacent to the bonding pads 322. The first alignment mark 330 may be, for example, the second alignment mark 220, which includes one or more of the sub-alignment marks 220A-220D shown in the present disclosure. As set forth above, the sub-alignment marks 220A, 220B, 220C, and 220D may exist and function independently, as long as their corresponding sub-alignment marks 120A, 120B, 120C and 120D are present. However, all the possible alignment marks formed by the method shown in
In some embodiments, a second package component 400 is bonded over the first package component 300. For example, the second package component 400 may be a device die, a package with a device die(s) packaged therein, a System-on-Chip (SoC) die including a plurality of device dies packaged as a system, or the like. The second package component 400 may be or may comprise logic dies, memory dies, input-output dies, Integrated Passive Devices (IPDs), or the like, or combinations thereof. For example, the logic device dies in the second package component 400 may be Central Processing Unit (CPU) dies, Graphic Processing Unit (GPU) dies, mobile application dies, Micro Control Unit (MCU) dies, BaseBand (BB) dies, Application processor (AP) dies, or the like. The memory dies in the second package component 400 may include Static Random Access Memory (SRAM) dies, Dynamic Random Access Memory (DRAM) dies, or the like. The second package component 400 may include semiconductor substrates and interconnect structures, which are not individually shown in the present embodiment.
In addition, another bonding film 420 is formed on the second package component 400 for the bonding process. For example, the material of the bonding film 420 includes SiON, SiO2, any other suitable material, or a combination thereof. In some embodiments, the material of the bonding film 420 is the same as the material of the bonding film 320. Although two bonding films (e.g. the bonding film 320 and the bonding film 420) are shown in the present disclosure, it should be appreciated that one or multiple (more than two) bonding films are also adopted in the present disclosure.
In some embodiments, a plurality of bonding pads 422 are formed in the bonding film 420. For example, the bonding pads 422 include conductive material such as tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination thereof. In some embodiments, the bonding pads 422 are each aligned with the bonding pads 322 over the first package component 300 to form electrical connection between the second package component 400 and the interconnect structure 315. In some embodiments, a second alignment mark 430 may be formed in the bonding film 420 and adjacent to the bonding pads 422. The second alignment mark 430 may be, for example, the first alignment mark 120, which includes one or more of the sub-alignment marks 120A-120D shown in the present disclosure. As set forth above, the sub-alignment marks 120A, 120B, 120C, and 120D may exist and function independently, as long as their corresponding sub-alignment marks 220A, 220B, 220C and 220D are present. However, all the possible alignment marks formed by the method shown in
In some embodiments, a plurality of bump structures 360 are formed on the exposed TSV structures 310. That is, the bump structures 360 are formed on the first package component 300 and cover the exposed surfaces of the TSV structures 310. In some embodiments, the bump structures 360 may include controlled collapse chip connection (C4) bumps, solder bumps, copper bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, ball grid array (BGA) bumps, copper pillars, or the like.
In some embodiments, a third package component 500 is bonded over the first package component 300. For example, the third package component 500 may be a device die, a package with a device die(s) packaged therein, a System-on-Chip (SoC) die including a plurality of device dies packaged as a system, or the like. The third package component 500 may be or may comprise logic dies, memory dies, input-output dies, Integrated Passive Devices (IPDs), or the like, or combinations thereof. For example, the logic device dies in the third package component 500 may be Central Processing Unit (CPU) dies, Graphic Processing Unit (GPU) dies, mobile application dies, Micro Control Unit (MCU) dies, BaseBand (BB) dies, Application processor (AP) dies, or the like. The memory dies in the third package component 500 may include Static Random Access Memory (SRAM) dies, Dynamic Random Access Memory (DRAM) dies, or the like. The third package component 500 may include semiconductor substrates and interconnect structures, which are not individually shown in the present embodiment.
In addition, another bonding film 520 is formed on the third package component 500 for the bonding process. For example, the material of the bonding film 520 includes SiON, SiO2, any other suitable material, or a combination thereof. In some embodiments, the material of the bonding film 520 is the same as the material of the bonding film 320. Although two bonding films (e.g. the bonding film 320 and the bonding film 520) are shown in the present disclosure, it should be appreciated that one or multiple (more than two) bonding films are also adopted in the present disclosure.
In some embodiments, a plurality of bonding pads 522 are formed in the bonding film 520. For example, the bonding pads 522 include conductive material such as tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), any other suitable conductive material, or a combination thereof. In some embodiments, the bonding pads 522 are each aligned with the bonding pads 322 over the first package component 300 to form electrical connection between the third package component 500 and the interconnect structure 315.
In some embodiments, a third alignment mark 530 may be formed in the bonding film 520 and adjacent to the bonding pads 522. The third alignment mark 530 may be, for example, the first alignment mark 120, which includes one or more of the sub-alignment marks 120A-120D shown in the present disclosure. As set forth above, the sub-alignment marks 120A, 120B, 120C, and 120D may exist and function independently, as long as their corresponding sub-alignment marks 220A, 220B, 220C and 220D are present. However, all the possible alignment marks formed by the method shown in
As described above, the present disclosure is directed to package structures and methods for forming the same. The package structure includes a first alignment mark and a second alignment mark corresponding to each other. Each of the first alignment mark and the second alignment mark includes a first group and a second group extending in two directions. Accordingly, the two-dimensional (2D) alignment may be achieved. In addition, a plurality of overlapped sub-alignment marks are provided in the first alignment mark and the second alignment mark, and therefore different resolution of alignment error during the assembly of package structure may be obtained. By means of arranging multiple sub-alignment marks, the alignment error may be double-checked.
In accordance with some embodiments, a package structure is provided and includes a first bonding film on a first package component, and a first alignment mark in the first bonding film. The first alignment mark includes a plurality of first patterns spaced apart from each other. The package structure includes a second bonding film on a second package component and bonded to the first bonding film, and a second alignment mark in the second bonding film. The second alignment mark includes a plurality of second patterns spaced apart from each other, and the first patterns overlap the second patterns. In a top view, each of the first patterns is divided into a first portion and a second portion, the first portions of the first patterns are separated by a first pitch, the second portions of the first patterns are separated by a second pitch, and the first pitch is different from the second pitch.
In accordance with some embodiments, a method of forming a package structure is provided and includes forming a first bonding film on a first package component. The method includes forming a first alignment mark in the first bonding film. The first alignment mark includes a plurality of first patterns spaced apart from each other. The method includes forming a second bonding film on a second package component. The method includes forming a second alignment mark in the second bonding film. The second alignment mark includes a plurality of second patterns spaced apart from each other. The method includes moving either the first package component or the second package component to align the first alignment mark with the second alignment mark. The method includes determining if the first alignment mark is aligned with the second alignment mark by determining whether the edges of the standard pattern of the first patterns coincide with the edges of the standard pattern of the second patterns. After determining that the first alignment mark is aligned with the second alignment mark the method includes bonding the second package component to the first package component.
In accordance with some embodiments, a package structure is provided and includes a first bonding film and a second bonding film. The first bonding film is on a first package component, wherein a first alignment mark is formed in the first bonding film and includes a plurality of first patterns spaced apart from each other by a first pitch. The second bonding film is on a second package component and bonded to the first bonding film, wherein a second alignment mark is formed in the second bonding film and includes a plurality of second patterns spaced apart from each other by a second pitch. The second package component is bonded to the first package component via the first bonding film and the second bonding film, and the first pitch is different from the second pitch.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.