Patent Application
20250125276
The present disclosure relates to package substrates, and more particularly, to a package substrate having embedded capacitor dies, a semiconductor device and a method for forming a package substrate.
Due to the miniaturization of logic components (e.g. circuit components of a logic integrated circuit (IC)) with technological advancements, their operating voltages decrease, leading to a smaller tolerance for voltage variations. For instance, assuming a voltage tolerance range of 10% of the rated value, a supply voltage of 3.3 volts allows a variation space of ±0.3 volts, while a supply voltage of 0.7 volts merely leaves a variation space of ±0.07 volts. However, delivering voltage to logic components usually involves transmitting electrical power over long traces on a circuit board, causing significant voltage fluctuations. This, in turn, diminishes the stability and performance of logic components. Thus, there is a need in the art for an improved design to reduce the adverse effects resulting from power transmission.
The described embodiments provide a package substrate having embedded capacitor dies, a semiconductor device and a method for forming a package substrate.
Some embodiments described herein may include a package substrate. The package substrate includes a first dielectric layer, a second dielectric layer and a core layer. The first dielectric layer includes first electrical interconnect. The second dielectric layer includes second electrical interconnect. The core layer is situated between the first dielectric layer and the second dielectric layer, and includes a plurality of semiconductor dies stacked one above another between the first dielectric layer and the second dielectric layer. A first semiconductor die of the semiconductor dies is a capacitor die electrically connected to the first electrical interconnect of the first dielectric layer.
Some embodiments described herein may include a semiconductor device. The semiconductor device includes a package substrate and a semiconductor chip. The package substrate has a core layer. The core layer includes an embedded capacitor device. The embedded capacitor device includes a plurality of semiconductor dies and a plurality of adhesive layers. The semiconductor dies are stacked one above another. A first semiconductor die of the semiconductor dies is a capacitor die with exposed terminal electrodes. The adhesive layers are alternately stacked with the semiconductor dies. Each adhesive layer is bonded to two semiconductor dies on opposite sides of the adhesive layer respectively. The semiconductor chip is arranged at a first side the package substrate, and is electrically connected to the embedded capacitive device.
Some embodiments described herein may include a method of forming a package substrate. The method includes: bonding a first semiconductor die and a second semiconductor die to form a semiconductor capacitor stack, wherein at least one of the first semiconductor die and the second semiconductor die is a capacitor die; embedding the semiconductor capacitor stack into a core layer of the package substrate; and forming a first dielectric layer and a second dielectric layer on opposite sides of the core layer, respectively, wherein electrical interconnect of the first dielectric layer is electrically connected to the capacitor die.
With the use of the proposed substrate structure, the package substrate not only can integrate high-performance logic devices with multiple peripheral devices, but also can provide sufficient mechanical strength and efficient power management.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, it will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.
Moreover, spatially relative terms, such as “below,” “above,” “left,” “right,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
To effectively manage power consumption and improve overall performance in the integrated circuit (IC), heterogeneous integration is proposed to integrate multiple chips or devices on a shared substrate. Referring to
In the example of
The core layer 130 includes a plurality of conductive structures 132, and a capacitor die 136. The conductive structures 132 are arranged to provide conductive paths between respective electrical interconnect structures of the dielectric layers 110 and 120. Each conductive structure 132 can be implemented using a plated through-hole (PTH). The capacitor die 136, embedded within a cavity 138 of the core layer 130, can be a semiconductor die that is manufactured and separated from a wafer. The capacitor die 136 contains numerous capacitor structures that include electrode and dielectric structures formed by semiconductor manufacturing processes, thereby providing a larger capacitor surface area and higher capacitance. By way of example but not limitation, the capacitor die 136 can be a trench capacitor die with multiple trench capacitor structures (e.g. multiple trench metal-insulator-metal (MIM) capacitors).
The capacitor die 136 is arranged to store electrical energy and provide the stored electrical energy to the logic device 102, thereby maintaining power stability of the logic device 102. For example, the capacitor die 136 can receive and store electrical energy through the electrical interconnect of the dielectric layer 110 and the bump structure 114, and provide the stored electrical energy to the logic device 102 through the electrical interconnect of the dielectric layer 120 and the bump structure 124. Compared to the energy transmission path from a power source on a printed circuit board (not shown) to the logic device 102, the energy transmission path between the capacitor die 136 and the logic device 102 is significantly shorter when the logic device 102 is placed on the package substrate 100 having the capacitor die 136. Thus, the package substrate 100 can effectively reduce energy losses, and increase power integration and system stability.
For high-end products (e.g., artificial intelligence (AI) produces, high-performance computing (HPC) products, 5G communication applications) that require high computational power or multiple functionalities, a logic device will be used to control more peripheral devices, resulting in an increase in substrate area for heterogeneous integration. For example, in a case where the package substrate 100 is used to integrate one logic device 102 and three peripheral devices 104, the area of the package substrate 100 can be represented by SA. When the package substrate 100 is used to integrate one logic device 102 and six peripheral devices 104, the area of the package substrate 100 may require 4×SA. As the substrate area increases, the thickness of the core layer would need to increase to provide sufficient mechanical support. Additionally, in a case where the logic device 102 is a high-end semiconductor chip (e.g. a GPU or CPU chip with high computational performance), a dielectric layer of the package substrate 100 may need to be thicker to accommodate more metal routing counts, which may require further increase in the thickness of core layer 130 to provide sufficient mechanical support. However, when the thickness of the core layer 130 increases, the capacitor die 136 may be separated from the dielectric layer, making it difficult for the capacitor die 136 to store electrical energy through the dielectric layer or provide electrical energy to the logic device 102 through the dielectric layer.
The present disclosure describes exemplary package substrates, each of which includes a core layer having multiple semiconductor dies stacked on top of each other. At least one of the semiconductor dies is a capacitor die. The package substrate has a thickness greater than that of a single semiconductor die, thus providing sufficient mechanical support. For example, the thickness of the core layer can be substantially equal to the overall thickness of the stacked semiconductor dies. In some embodiments, adjacent semiconductor dies can be bonded using an adhesive layer, such as glue, polymer adhesive or photosensitive adhesive. In some embodiments, at least one semiconductor die (e.g. a capacitor die) can be electrically connected to a logic device placed on the package substrate via electrical interconnect. In some embodiments, the package substrate can be placed on a printed circuit board, and at least one semiconductor die (e.g. a capacitor die) can store electrical energy provided by a power source on the printed circuit board via electrical interconnect. In some embodiments, at least one semiconductor die can be a dummy die, which can be electrically isolated from the electroconductive structures of the package substrate.
The present disclosure further describes exemplary methods for forming a package substrate. The exemplary method can form multiple semiconductor dies stacked one above another (including at least one capacitor die) in a core layer of the package substrate. In addition, the present disclosure describes exemplary semiconductor devices, each of which includes a package substrate and a semiconductor chip formed on the package substrate. The package substrate includes a capacitor device that is embedded into a core layer of the package substrate. The capacitor device includes a semiconductor die stack, in which adjacent semiconductor dies can be bonded using an adhesive layer, such as glue, polymer adhesive or photosensitive adhesive. In some embodiments, adjacent semiconductor dies can be electrically connected to each other via a conductive structure (e.g. a through-substrate via (TSV) structure). The conductive structure can penetrate through the adhesive layer between adjacent semiconductor dies. The proposed structures and methods not only can enable the heterogeneous integration of HPC logic devices with multiple peripheral devices on a package substrate, but also can provide sufficient mechanical strength to support multiple devices/chips on the package substrate.
The core layer 230, situated between the dielectric layers 210 and 220, can serve as the primary support layer of the package substrate 200 to provide mechanical strength and support. By way of example but not limitation, the core layer 230 can be filled with glass fiber and resin materials to provide sufficient mechanical support. The core layer 230 may include, but is not limited to, a plurality of conductive structures 232 and a semiconductor capacitor device (also referred to as a capacitor device for brevity) 236. Each conductive structure 232 is arranged to provide a conductive path between the dielectric layers 210 and 220. At least one conductive structure 232 can be implemented using (but not limited to) a plated through-hole (PTH).
The semiconductor capacitor device 236, embedded in the core layer 230, can have a thickness matching that of the core layer 230. In the present embodiment, the semiconductor capacitor device 236 can be located within the cavity 238. The cavity 238 can be filled with filling material to provide mechanical support and protect the semiconductor capacitor device 236. The filling material may be, but is not limited to, silicone gel, silicone resin, or thermally conductive adhesive.
The semiconductor capacitor device 236 includes a plurality of semiconductor dies 236_1 to 236_n (where n is an integer greater than 1) stacked one above another between the dielectric layers 210 and 220. At least one of the semiconductor dies 236_1 to 236_n is a capacitor die. In the present embodiment, two adjacent semiconductor dies can be bonded to each other using a corresponding adhesive layer 240. In other words, the adhesive layers 240 can be alternately stacked with the semiconductor dies 236_1 to 236_n. Each adhesive layer 240 can be implemented using an adhesive film, glue, adhesive, or polymer adhesive. The thickness of the adhesive layer 240 can range from, but is not limited to, 35 to 50 μm.
For example, the semiconductor dies 236_1 to 236_n can be manufactured and separated from n wafers. Each semiconductor die that is configured as a capacitor die have a large number of capacitor structures designed according to power management requirements. At least one wafer can be processed using semiconductor manufacturing technology to form multiple semiconductor capacitor structures with electrodes and dielectric layers. After the n wafers are stacked together using the adhesive layers 240, the stacked wafers can be cut to form multiple semiconductor capacitor devices. As a result, each semiconductor capacitor device can have stacked semiconductor dies.
Note that each semiconductor capacitor structure can be a three-dimensional (3D) capacitor with high charge storage capacity to facilitate effective power management in HPC applications. For example, as the capacitance density is proportional to the dielectric constant and the capacitor surface area, high-k 3D capacitors are employed to enhance the charge storage capacity. In some embodiments, at least one wafer can be processed using a dynamic random-access memory (DRAM) process to form multiple semiconductor capacitor structures. Thus, at least one of the semiconductor dies 236_1 to 236_n can have a plurality of 3D capacitors formed by the DRAM process. The 3D capacitors can be, but are not limited to, cylindrical capacitors, trench capacitors, or pillar capacitors. A semiconductor die can include millions or more of 3D capacitors.
At least one of the semiconductor dies 236_1 to 236_n can be electrically connected to electrical interconnect of a dielectric layer to receive electrical energy provided by a power source on a circuit board (not shown). Additionally or alternatively, at least one of the semiconductor dies 236_1 to 236_n can be electrically connected to electrical interconnect of a dielectric layer to provide the stored electrical energy to devices/chips placed on the dielectric layer. For example, when the semiconductor die 236_n is configured as a capacitor die and electrically connected to the electrical interconnect 222 of the dielectric layer 220, the semiconductor die 236_n can receive and store electrical energy through the electrical interconnect 222, and provide the stored energy to chip(s) placed on dielectric layer 220 (not shown), such as the logic device 102 shown in
Compared to the transmission path from an external power source (outside the package substrate 200) to a chip on the dielectric layer 220, the transmission path from the semiconductor dies 236_1 to 236_n to the chip on the dielectric layer 220 is shorter. Therefore, using the semiconductor capacitor device 236 embedded within the core layer 230 to provide electrical energy can effectively reduce power supply noise and enhance overall performance. Additionally, by embedding the stacked semiconductor dies 236_1 to 236_n into the core layer 230, the package substrate 200 not only can have sufficient mechanical support for large substrate area applications, but also can provide sufficient energy storage capacity for efficient power management, thereby enhancing system performance.
To facilitate understanding of the present disclosure, some embodiments are given as follows for further description of the proposed substrate structure. Those skilled in the art should understand that other embodiments employing the core layer structure shown in
The area of the package substrate 300 used to accommodate devices (e.g. the cross-sectional area of the package substrate 300 in the xy-plane) is greater than that of the package substrate 100 shown in
Each of the peripheral devices 1041 and 1042 can be, but are not limited to, a memory chip, an SoC, a video chip, an audio chip, an RF chip, a power management chip, or other types of semiconductor chips. Each peripheral device may be, but is not limited to, a semiconductor chip that includes a GAA transistor structure or a FinFET structure. In addition, the thickness of the package substrate 300 (the dimension of the package substrate 300 in the z direction) is greater than that of the package substrate 100 shown in
The package substrate 300 includes a dielectric layer 310, a dielectric layer 320 and a core layer 330, which can serve as embodiments of the dielectric layer 210, the dielectric layer 220 and the core layer 230 shown in
The core layer 330 may include a plurality of conductive structures 332 and a semiconductor capacitor device 336. Each conductive structure 332 is arranged to provide a conductive path between the dielectric layers 310 and 320. The semiconductor capacitor device 336 can serve as an embodiment of the semiconductor capacitor device 236 shown in
In the embodiment shown in
In addition, the semiconductor die 336_2 can be a capacitor die that is electrically connected to the electrical interconnect 322 of the dielectric layer 320. For example, the semiconductor die 336_2 may include a conductive layer ML2 (e.g. a metal layer containing top and bottom electrodes) electrically connected to the electrical interconnect 322. The semiconductor die 336_2 can receive and store electrical energy via the conductive layer ML2 and the electrical interconnect 322.
In some embodiments, at least one semiconductor die embedded in the core layer may be a dummy die. Referring to
In some embodiments, a plurality of semiconductor capacitor devices can be embedded in the core layer, and each semiconductor capacitor device includes a plurality of semiconductor dies stacked between opposite sides of a core layer.
The semiconductor capacitor device 736A includes a plurality of semiconductor dies 736_1A to 736_3A stacked one above another. The semiconductor die 736_1A is electrically connected to the electrical interconnect 312 of the dielectric layer 310, while the semiconductor dies 736_2A and 736_3A are electrically connected to the electrical interconnect 322 of the dielectric layer 320. In the example shown in
The semiconductor capacitor device 736B includes a plurality of semiconductor dies 736_1B to 736_3B stacked one above another. The structure of the semiconductor capacitor device 736B is substantially identical/similar to that of the semiconductor capacitor device 736A except that the semiconductor die 736_1B is implemented as a dummy die. The semiconductor capacitor device 736C includes a plurality of semiconductor dies 736_1C to 736_3C stacked one above another. The semiconductor die 736_1C is electrically connected to the electrical interconnect 312 of the dielectric layer 310; the semiconductor die 736_2C is implemented as a dummy die; the semiconductor die 736_3C is electrically connected to the electrical interconnect 322 of the dielectric layer 320. In the example shown in
At operation 810, a first semiconductor die and a second semiconductor die are bonded to form a semiconductor capacitor stack. At least one of the first semiconductor die and the second semiconductor die is a capacitor die, such as a capacitor die with exposed terminal electrodes. For example, the semiconductor dies 336_1 and 336_2 are bonded using the adhesive layer 240 to form a semiconductor capacitor stack (i.e. the semiconductor capacitor device 336).
At operation 820, the semiconductor capacitor stack structure is embedded into a core layer of the package substrate. For example, the semiconductor capacitor device 336 is embedded into the core layer 330.
At operation 830, a first dielectric layer and a second dielectric layer are formed on opposite sides of the core layer, respectively. Electrical interconnect of the first dielectric layer is electrically connected to the capacitor die in the semiconductor capacitor stack. For example, the dielectric layers 310 and 320 are formed on opposite sides of the core layer 330, respectively. The electrical interconnect 312 of the dielectric layer 310 is electrically connected to the semiconductor die 336_1, and the electrical interconnect 322 of the dielectric layer 320 is electrically connected to the semiconductor die 336_2.
In some embodiments, the first semiconductor die and the second semiconductor die combined at operation 810 may be separated from associated wafers respectively. Referring to
Next, the first wafer and the second wafer can be bonded to form a wafer stack, which includes the semiconductor die 336_1 and the semiconductor die 336_2 bonded together by the adhesive layer 240. For example, the adhesive layer 240 can be applied to the first wafer to facilitate the bonding of the first wafer and the second wafer. After the first wafer and the second wafer are bonded to each other, the carriers 951 and 952 can be removed.
Furthermore, after the first wafer and the second wafer are bonded to each other, the wafer stack can be diced to form a plurality of semiconductor capacitor stacks. Referring to
For example, referring to
In some embodiments, the width of the scribe line SL can range from, but is not limited to, 160 to 300 μm. In some embodiments, the thickness of the core layer (the height H of the stacked wafers 1101 and 1102) can range from, but is not limited to, 800 to 1500 μm. In some embodiments, the ratio of the width of the scribe line SL to the thickness of the core layer can range from, but is not limited to, 5% to 30%.
In some embodiments, the depth of the groove SG can be less than (but not limited to) 100 μm. In some embodiments, the depth of the gap AG can be less than (but not limited to) 200 μm. In some embodiments, the ratio of the depth of the groove SG to the thickness of the core layer can be less than (but not limited to) 30%. In some embodiments, the ratio of the depth of the gap AG to the thickness of the core layer can be less than (but not limited to) 30%. In some embodiments, the ratio of the width of the scribe line SL to the depth of the groove SG can be less than (but not limited to) 10%.
In some embodiments, the embedded semiconductor capacitor stack can be located within a cavity of the core layer. Referring to
In some embodiments, the embedded semiconductor capacitor stack can be surrounded by material of the core layer.
As those skilled in the art can appreciate that the method described above for forming a package substrate can be applied to a capacitor stack having with three or more semiconductor dies, repeated description is omitted here for brevity. With the use of the proposed structures and methods, the package substrate not only can integrate high-performance logic devices with multiple peripheral devices, but also can provide sufficient mechanical strength and efficient power management.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
The present application claims priority to U.S. Provisional Patent Application No. 63/590,521, filed on Oct. 16, 2023, which is incorporated by reference herein in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63590521 | Oct 2023 | US |
