Claims
- 1. A method for fabricating a dual gate semiconductor device, comprising:
forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate; patterning a photoresist over said nitridated, high voltage gate dielectric layer to expose said nitridated, high voltage dielectric within a low voltage region, said patterning leaving an accelerant residue on said exposed nitridated, high voltage gate dielectric layer; and subjecting said exposed nitridated, high voltage dielectric to a high vacuum to remove said accelerant residue.
- 2. The method as recited in claim 1 wherein said subjecting includes subjecting said exposed nitridated, high voltage dielectric to a vacuum ranging from about 1 e−3 torr to about 1 e−8 torr.
- 3. The method as recited in claim 2 wherein a temperature associated with said high vacuum ranges from about 20° C. to about 5° C. that the glass transition temperature (Tg) of said photoresist.
- 4. The method as recited in claim 2 wherein said subjecting includes subjecting said exposed nitridated, high voltage dielectric to a vacuum of about 1 e−6 torr.
- 5. The method as recited in claim 1 wherein said subjecting includes subjecting said exposed nitridated, high voltage dielectric to said high vacuum for a period of time ranging from about 2 minutes to about 60 minutes.
- 6. The method as recited in claim 5 wherein said time is about 10 minutes.
- 7. The method as recited in claim 1 wherein said accelerant residue acts as an accelerant for buffered hydrogen fluoride to increase a silicon etch rate of said buffered hydrogen fluoride.
- 8. The method as recited in claim 1 further including etching said nitridated, high voltage gate dielectric subsequent to said subjecting.
- 9. The method as recited in claim 1 further including forming a nitridated, low voltage gate dielectric over said low voltage region subsequent to subjecting said low voltage region to said vacuum.
- 10. The method as recited in claim 1 wherein forming said nitridated, high voltage gate dielectric layer includes nitridating said high voltage gate dielectric layer using a decoupled nitridation process or a remote nitridation process.
- 11. The method as recited in claim 1 wherein said dielectric layer is silicon dioxide.
- 12. A method for manufacturing a dual gate integrated circuit, comprising:
forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate; patterning a photoresist over said nitridated, high voltage gate dielectric layer to expose said nitridated, high voltage dielectric within a low voltage region, said patterning leaving an accelerant residue on said exposed nitridated, high voltage gate dielectric layer; and subjecting said exposed nitridated, high voltage dielectric to a high vacuum to remove said accelerant residue; forming a nitridated, low voltage gate dielectric layer over said semiconductor substrate within said low voltage regions; forming high voltage gate transistors over said nitridated, high voltage gate dielectric layer; forming low voltage gate transistors over said nitridated, low voltage gate dielectric layer; forming source/drain regions associated with each of said high voltage and low voltage transistors; forming dielectric layers located over said high voltage and low voltage transistors; and forming interconnects extending through said dielectric layers to interconnect said high voltage and low voltage transistors to form an operative integrated circuit.
- 13. The method as recited in claim 12 wherein said subjecting includes subjecting said exposed nitridated, high voltage dielectric to a vacuum ranging from about 1 e−3 torr to about 1 e−8 torr.
- 14. The method as recited in claim 13 wherein a temperature associated with said high vacuum ranges from about 20° C. to about 5° C. less than the Tg of said photoresist.
- 15. The method as recited in claim 13 wherein said subjecting includes subjecting said exposed nitridated, high voltage dielectric to a vacuum of about 1 e−6 torr.
- 16. The method as recited in claim 12 wherein said subjecting includes subjecting said exposed nitridated, high voltage dielectric to said high vacuum for a period of time ranging from about 2 minutes to about 60 minutes.
- 17. The method as recited in claim 16 wherein said time is about 10 minutes.
- 18. The method as recited in claim 12 wherein said accelerant residue acts as an accelerant for buffered hydrogen fluoride to increase a silicon etch rate of said buffered hydrogen fluoride.
- 19. The method as recited in claim 12 further including etching said nitridated, high voltage gate dielectric subsequent to said subjecting.
- 20. The method as recited in claim 12 further includingforming a nitridated, low voltage gate dielectric over said low voltage region subsequent to subjecting said low voltage region to said plasma.
- 21. The method as recited in claim 12 wherein forming said nitridated, high voltage gate dielectric layer includes nitridating said high voltage gate dielectric layer using a decoupled nitridation process or a remote nitridation process
- 22. The method as recited in claim 12 wherein said dielectric layer is silicon dioxide.
CROSS-REFERENCE TO PROVISIONAL APPLICATION
[0001] This application claims the benefit of U.S. Provisional Application No. 60/438,112 entitled “POST HIGH VOLTAGE GATE OXIDE PATTERN HIGH-VACUUM OUTGAS SURFACE TREATMENT,” to Kirkpatrick, et al., filed on Jan. 6, 2003, which is commonly assigned with the present invention and incorporated herein by reference as if reproduced herein in its entirety.
Provisional Applications (1)
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Number |
Date |
Country |
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60438112 |
Jan 2003 |
US |