Power Switches in Interconnect Structures and the Method Forming the Same

Abstract

A method includes forming first integrated circuit devices and second integrated circuit devices on a semiconductor substrate of a wafer, forming a metal layer as a part of the wafer, and forming a transistor comprising a first source/drain region connected to the first integrated circuit devices. The transistor is farther away from the semiconductor substrate than the metal layer. An electrical connector is formed on a surface of the wafer, and is electrically connected to a second source/drain region of the transistor.

Description

BACKGROUND

Header cells (power switches) are used in integrated circuits for gating the power provided to a circuit. A header cell may include a transistor, whose source may be connected to a power node such as VDD. The drain may be used as another power node, whose voltage is determined by whether the transistor is turned on or off. When the header cell is turned on, the drain receives the power, and hence the circuit is powered. When the header cell is turned off, no power is provided to the circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1-6 illustrate the cross-sectional views of intermediate stages in the formation of dies including a power switch(es) in accordance with some embodiments.

FIGS. 7-11 illustrate views of a power switch in accordance with some embodiments.

FIG. 12 illustrates the packaging of a device die including a power switch in accordance with some embodiments.

FIG. 13 illustrates the bonding of a device die including a power switch in accordance with some embodiments.

FIG. 14 illustrates a process flow for forming a device die including a power switch in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A power switch formed in a Back-End-of-Line (BEOL) structure of a die or in a backside interconnector structure of the die is provided. The method of forming the same are provided. In accordance with some embodiments of the present disclosure, a thin-film transistor, which may be an InGaZnO (IGZO) transistor, is formed in a BEOL structure of the device die or a backside interconnect structure of the device die, and is used as a power switch to gate power to a circuit in the die. Since power switches occupy large chip areas, moving the power switches from the surface of semiconductor substrate to interconnect structures releases the chip area for forming other circuits. In addition, the path for providing power is reduced, and the resistance is reduced, hence the performance of the circuit may be improved.

Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

FIGS. 1 through 6 illustrate the cross-sectional views of intermediate stages in the formation of a device die in accordance with some embodiments of the present disclosure. The corresponding processes are also reflected schematically in the process flow shown in FIG. 14.

FIG. 1 illustrates a cross-sectional view of wafer 20. In accordance with some embodiments, wafer 20 is or comprises a device wafer including active devices and possibly passive devices, which are represented as integrated circuit devices 24. Wafer 20 may include a plurality of chips/dies 20′ therein, with one of chips 20′ being illustrated.

In accordance with some embodiments, wafer 20 includes semiconductor substrate 22 and the features formed at a top surface of semiconductor substrate 22. Semiconductor substrate 22 may be formed of or comprise crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. Shallow Trench Isolation (STI) regions (not shown) may be formed in semiconductor substrate 22 to isolate the active regions in semiconductor substrate 22.

In accordance with some embodiments, integrated circuit devices 24 are formed on the top surface of semiconductor substrate 22, and are collectively referred to as Front-end-of-line (FEOL) structures. The respective process is illustrated as process 202 in the process flow 200 as shown in FIG. 14. Integrated circuit devices 24 may include Complementary Metal-Oxide Semiconductor (CMOS) transistors, resistors, capacitors, diodes, and/or the like in accordance with some embodiments. In accordance with some embodiments, integrated circuit devices 24 include integrated circuit devices 24A that is powered by a gated power and integrated circuit devices 24B powered by un-gated power, as discussed in detail in subsequent paragraphs.

As shown in FIGS. 1 and 2, interconnect structure 32 is formed over, and is electrically connected to, integrated circuit devices 24. The respective process is illustrated as process 204 in the process flow 200 as shown in FIG. 14. In accordance with some embodiments, interconnect structure 32 includes Inter-Layer Dielectric (ILD) 28 formed over semiconductor substrate 22 and filling the spaces between the gate stacks of transistors (not shown) in integrated circuit devices 24. In accordance with some embodiments, ILD 28 is formed of silicon oxide, Phospho Silicate Glass (PSG), Boro Silicate Glass (BSG), Boron-doped Phospho Silicate Glass (BPSG), Fluorine-doped Silicate Glass (FSG), or the like. ILD 28 may be formed using spin coating, Flowable Chemical Vapor Deposition (FCVD), or the like. In accordance with some embodiments, ILD 28 may also be formed using a deposition method such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), or the like.

Contact plugs 30 are formed in ILD 28, and are used to electrically connect integrated circuit devices 24 to overlying metal lines and vias. In accordance with some embodiments, contact plugs 30 are formed of or comprise a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys therefore, and/or multi-layers thereof. The formation of contact plugs 30 may include forming contact openings in ILD 28, filling a conductive material(s) into the contact openings, and performing a planarization process (such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process) to level the top surfaces of contact plugs 30 with the top surface of ILD 28.

In accordance with some embodiments, through-vias 26 (alternatively referred to as Through-silicon-vias (TSVs) or through-Semiconductor-vias (also TSVs)) are formed in wafer 20. Through-vias 26 may extend from the top surface to an intermediate level between the top surface and the bottom surface of semiconductor substrate 22. The top ends of through-vias 26 may extend to the top surface of ILD 28. Alternatively, the top ends of through-vias 26 may be at any available levels such as the top surface level of semiconductor substrate 22, or a top surface level of any one of dielectric layers 38. Each of through-vias 26 may be encircled by a dielectric isolation layer (not shown), which electrically insulates the respective through-via 26 from semiconductor substrate 22.

In accordance with some embodiments such as what are illustrated in FIG. 1, the formation of through-vias 26 includes a through-via-first process or a through-via-middle process, in which through-vias 26 are formed from the front side of semiconductor substrate 22. In accordance with alternative embodiments, a through-via-last process may be adopted to form through-vias 26, and the through-vias 26 may be formed from the backside of wafer 20.

Through-vias 26 include power through-vias 26A for conducting un-gated power, and through-vias 26B for conducting signal. There may be, or may not be, additional through-vias such as through-vias 26C, which are also used for conducting gated power, which gated power may be gated on the backside of semiconductor substrate 24.

Referring to FIG. 2, more metal layers and dielectric layers are formed to extend interconnect structure 32 upwardly. Interconnect structure 32 further includes dielectric layers 38 (also referred to as Inter-metal Dielectrics (IMDs)), etch stop layers (not shown), and metal lines 34 and vias 36 formed in dielectric layers 38. The metal lines at a same level are collectively referred to as a metal layer hereinafter. In accordance with some embodiments, interconnect structure 32 includes a plurality of metal layers (M0 through Mtop) including metal lines 34 that are interconnected through vias 36. The metal layers in interconnect structure 32 may be denoted as M0, M1, M2, M3, and the like.

Metal lines 34 and vias 36 may be formed of copper or copper alloys, and can also be formed of or comprise other metals such as aluminum, tungsten, nickel, or the like. In accordance with some embodiments, dielectric layers 38 are formed of low-k dielectric materials. The dielectric constants (k values) of the low-k dielectric materials may be lower than about 3.5 or lower than about 3.0, for example. Dielectric layers 38 may comprise a carbon-containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like. The etch stop layers may be formed of or comprise aluminum oxide, aluminum nitride, SiOC, SiON, or the like, or multi-layers thereof.

The formation of metal lines 34 and vias 36 in dielectric layers 38 may include single damascene processes and/or dual damascene processes. In a single damascene process for forming a metal line or a via, a trench or a via opening is first formed in one of dielectric layers 38, followed by filling the trench or the via opening with a conductive material. A planarization process such as a CMP process is then performed to remove the excess portions of the conductive material higher than the top surface of the dielectric layer, leaving a metal line or a via in the corresponding trench or via opening.

In a dual damascene process, both of a trench and a via opening are formed in a dielectric layer, with the via opening underlying and connected to the trench. Conductive materials are then filled into the trench and the via opening to form a metal line and a via, respectively. The conductive materials may include a diffusion barrier layer and a copper-containing metallic material over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

The top metal layer is referred to as metal layer Mtop, the metal layer immediately under metal layer Mtop is referred to as metal layer M(top-1), and the metal layer immediately under metal layer M(top-1) is referred to as metal layer M(top-2), and so on. In accordance with some embodiments, the total number of metal layers may be greater than about 9, and may be in the range between about 9 and 16. In accordance with some embodiments, the top metal layer Mtop is formed in dielectric layer 38T, which is the top layer of dielectric layers 38. Dielectric layer 38T may be formed of or comprise a low-k dielectric material, as discussed above. Alternatively, dielectric layer 38T may be formed of or comprise a non-low-k dielectric material such as un-doped Silicate Glass (USG), silicon oxide, silicon oxynitride, silicon nitride, or the like, or combinations thereof.

In accordance with some embodiments, thin-film transistor 40 is formed in one of the metal layers, or between two neighboring metal layers. The respective process is illustrated as process 206 in the process flow 200 as shown in FIG. 14. In accordance with some example embodiments, as shown in FIG. 2, thin-film transistor 40 is formed in a top position of the interconnect structure 32, such as between metal layers Mtop and M(top-1).

Dielectric layer 42 may be formed over top metal layer Mtop and the top dielectric layer 38T. The respective process is illustrated as process 208 in the process flow 200 as shown in FIG. 14. In accordance with some embodiments, dielectric layer 42 may be formed of or comprise a silicon-based dielectric material such as SiO, SiN, SiON, SiOCN, SiOC, or the like, combinations thereof, or multi-layers thereof. Dielectric layer 42 may sometimes be used for bonding to a supporting substrate, and hence may be referred to as a bond layer hereinafter.

Forming thin-film transistor 40 in a top position of interconnect structure 32 has some advantageous features. The thin-film transistor 40 is used as a power switch. Accordingly, the size (and the occupied chip area) of thin-film transistor 40 is large. For example, the chip area occupied by thin-film transistor(s) 40 in a device die may range between about 4 percent and about 8 percent of the device die. The upper metal layers have large pitches and large metal line widths that fit the formation of thin-film transistor 40. Also, the upper metal layers have greater thicknesses and greater distances from their neighboring metal layers, and the process difficulty in the formation of thin-film transistor 40 is reduced.

FIG. 7 illustrates a perspective view of thin-film transistor 40 and the underlying metal layers in accordance with some embodiments. Integrated circuit devices 24 and M0 power rails are also illustrated schematically.

FIG. 8 illustrates a cross-sectional view of thin-film transistor 40 in accordance with some embodiments. In accordance with some embodiments, thin-film transistor 40 is formed on the front side of semiconductor substrate 22 as a power switch. In accordance with alternative embodiments, the front-side thin-film transistor 40 is not formed. Rather, a backside power switch is formed. Thin-film transistor 40 may include channel layer 142, which may be formed of or comprise a metal oxide. For example, channel layer 142 may comprise InGaZnO (IGZO), which is a semiconductor. In accordance with some embodiments, source region 144 and drain region 146 are in contact with channel layer 142, and are spaced apart from each other by dielectric layer 148. Gate dielectric 145 may be under channel layer 142, and may be formed of a high-K (HK) dielectric material. Bottom gate 150 may be underlying and in contact with gate dielectric 145. Dielectric regions/layer 152 are formed to surround bottom gate 150.

In the illustrated example, thin-film transistor 40 is a bottom-gate transistor. In accordance with alternative embodiments, thin-film transistor 40 is a top-gate transistor. In accordance with yet alternative embodiments, thin-film transistor 40 may be a double-gate transistor including both of a top gate and a bottom gate.

In accordance with some embodiments, as shown in FIG. 2, thin-film transistor 40 may be formed between metal layers Mtop and M(top-1). For example, thin-film transistor 40 may be formed at the same level as the vias 36T (FIG. 2), which is between metal layers Mtop and M(top-1). In accordance with alternative embodiments, depending on how many integrated circuits are powered by the gated power, and depending on the corresponding routing requirement, thin-film transistor 40 may be formed in any of the underlying layer such as between metal layers M(top-1) and M(top-2), between metal layers M(top-2) and M(top-3) . . . between metal layers M3 and M2, or between metal layers M2 and M1.

Also, there may be a plurality of thin-film transistors 40 (as power switches) formed at different levels. For example, when thin-film transistor 40 is formed between metal layers Mtop and M(top-1), there may be other thin-film transistors 40 formed between metal layers M(top-1) and M(top-2), between metal layers M(top-2) and M(top-3), and/or at other levels. Forming multiple thin-film transistors 40 at different levels may save more chip area, so that the multiple thin-film transistors 40 do not compete for the same chip area. Also, upper thin-film transistors 40 may support more circuits due to that more metal layers may be used for routing their power, while lower thin-film transistors 40 may support fewer circuits.

An example formation process of thin-film transistor 40 is briefly discussed herein. In subsequent discussion, it is assumed that bottom gate 150 is formed over metal layer M(top-1). In accordance with some embodiments, metal layer M(top-1) is formed. The bottom gate 150 as shown in FIG. 8 may be a part of the metal layer M(top-1) in accordance with some embodiments, as also shown in FIG. 9. Alternatively, the bottom gate 150 as shown in FIG. 8 is formed as being over and contacting a metal line in the metal layer M(top-1).

In accordance with some embodiments, as shown FIG. 8, dielectric layer 152 is deposited. Dielectric layer 152 may comprise silicon oxide, silicon nitride, silicon oxynitride, or the like. Next, bottom gate 150 is formed in dielectric layer 152, for example, through a damascene process. Bottom gate 150 may be formed of or comprise copper, aluminum, tungsten, nickel, cobalt, or the like, or combinations thereof. Alternative, bottom gate 150 and dielectric layer 152 are formed by depositing a metallic layer, patterning the metallic layer to form bottom gate 150, depositing a dielectric layer, and performing a planarization process.

Next, gate dielectric 145 is deposited, which may comprise silicon oxide or a high-k dielectric material such as hafnium oxide, lanthanum oxide, zirconium oxide, or the like. Channel layer 142, which may comprise InGaZnO, is then deposited. In subsequent processes, source regions(S) and drain regions (D) are formed over and contacting channel layer 142. Oxide layer 148 is formed between and separating source region 144 from drain region 146. The formation process may be similar to the formation of bottom gate 150 and dielectric layer 152.

In subsequent processes, the dielectric layer 148, channel layer 142, gate dielectric 145, and dielectric layer 152 are patterned in anisotropic etching processes, so that the portions of these layer outside of the thin-film transistor 40 are patterned, leaving thin-film transistor 40 standing over metal layer M(top-1). The top dielectric layer 38T (FIG. 2) may then be formed, followed by the formation of the vias 155 (FIGS. 9 and 10) for connecting to source regions 144 and drain regions 146. Metal layer Mtop may then be formed connecting to vias 155.

FIG. 9 illustrates thin-film transistor 40 in a larger view in accordance with some embodiments. In accordance with some embodiments, there are a plurality of source regions 144 and a plurality of drain regions 146 formed alternatingly. Each of the source regions 144 is connected to an overlying via 155. Each of the drain regions 146 is also connected to an overlying via 155. Through vias 155 and an overlying metal line 156 (also refer to FIG. 10) in metal layer Mtop, all of the drain regions 146 are interconnected. Through the vias 155 (marked as being dashed to indicate that they are not in the illustrated plane) and an overlying metal line 158 (FIG. 10) in metal layer Mtop, all of the source regions 144 are interconnected. Accordingly, thin-film transistor 40 includes a plurality of sub transistors connected in parallel, and hence may have a large current supporting the operation of a plurality of integrated circuit devices.

FIG. 10 illustrates a thin-film transistor 40 in accordance with some embodiments. Channel layer 142 may be formed as a long and wide sheet. Source regions 144 and drain regions may 146 be formed as a plurality of elongated strips in the top view. The elongated strips of source regions 144 are parallel to the elongated strips of drain regions 146, and are formed on channel layer 142. Bottom gate 150 may also be formed as an elongated strip or a plurality of elongated strips underlying and contacting the channel layer 142. Vias 155 connecting to source regions 144 and drain regions 146 are also illustrated.

FIGS. 3 through 6 illustrate the process for forming backside features on the backside of semiconductor substrate 22. Referring to FIG. 3, carrier 48 (which may be a glass carrier) is attached to the front side of wafer 20. The respective process is illustrated as process 210 in the process flow 200 as shown in FIG. 14. The attachment may be performed through an adhesive such as a light-to-heat-Conversion (LTHC) material 50, which is configured to be decomposed under the heat of light (such as a laser beam).

In accordance with alternative embodiments, carrier 48 may be a supporting substrate, which may be a blank silicon substrate in accordance with some embodiments. The supporting substrate may be formed of a homogeneous material such as silicon, and there is no other material other than the homogeneous material in the supporting substrate. Layer 50 in accordance with these embodiments may be a bond layer formed of a silicon-containing dielectric material such as SiO, SiC, SiOC, SiON, SiOCN, or the like.

Referring to FIG. 4, a backside grinding process is performed to remove a portion of semiconductor substrate 22, until through-vias 26 are revealed. The respective process is illustrated as process 212 in the process flow 200 as shown in FIG. 14. Semiconductor substrate 22 is then recessed slightly (for example, through etching), so that end portions of through-vias 26 protrude out of the back surface of semiconductor substrate 22. Next, dielectric layer 52 is deposited, followed by a CMP process or a mechanical grinding process to re-expose through-vias 26. Through-vias 26 thus penetrate through dielectric layer 52 also. In accordance with some embodiments, dielectric layer 52 is formed of silicon oxide, silicon nitride, or the like.

Referring to FIG. 5, metal pads 54 and dielectric layer 56 are formed. In accordance with some embodiments, the formation process may include depositing dielectric layer 56 on the backside of semiconductor substrate 22, etching dielectric layer 56 to form openings, through with through-vias 26 are formed, and filling the openings with conductive materials. The respective process is illustrated as processes 214 and 216 in the process flow 200 as shown in FIG. 14.

Referring to FIG. 6, in subsequent processes, backside redistribution structure 62 is formed. The respective process is illustrated as process 218 in the process flow 200 as shown in FIG. 14. Backside redistribution structure 62 include dielectric layers 58, and RDLs 60 are formed in dielectric layers 58. RDLs 60 may be formed of or comprise aluminum, copper, nickel, tungsten, titanium, or the like. In accordance with some embodiments, the formation of a layer of RDLs 60 may include forming a dielectric layer 58, etching the respective dielectric layer 58 to form openings, plating a metal seed layer extending into the openings, forming a patterned plating mask, with some portions of the metal seed layer being exposed, and plating to form the RDLs 60. In accordance with alternative embodiments, RDLs 60 may be formed through damascene processes.

Thin-film transistor 40′ may be formed inside backside redistribution structure 62. The respective process is illustrated as process 220 in the process flow 200 as shown in FIG. 14. In accordance with some embodiments, similar to thin-film transistor 40, thin-film transistor 40′ is formed in a metal layer that is farther away from semiconductor substrate 22 than some other metal layers. For example, there may be four backside metal layers on the backside of semiconductor substrate 22, which metal layers are referred to as BM0, BM1, BM2, and BM3. Thin-film transistor 40′ may be formed between metal layers BM2 and BM3, while it may also be formed between other neighboring backside metal layers (such as between metal layers BM3 and BM4 as shown in FIG. 11).

Thin-film transistor 40′ may be formed using essentially the same processes, and may have similar or the same structure as, thin-film transistor 40. The structure of thin-film transistor 40 may thus be essentially the same as illustrated in FIGS. 8 through 10. Thin-film transistor 40′ may include source region 144′, gate 150′, and drain region 146′, as shown in FIG. 6.

In accordance with some embodiments, thin-film transistor 40′ is formed on the backside of semiconductor substrate 22, while thin-film transistor 40 is not formed. In accordance with alternative embodiments, thin-film transistor 40 is formed on the front side of semiconductor substrate 22, while thin-film transistor 40′ is not formed. In accordance with yet alternative embodiments, both of thin-film transistor 40 and thin-film transistor 40′ are formed.

FIG. 11 illustrates a perspective view of parts of the backside structure of wafer 20 in accordance with some embodiments. Front-side metal layer M0 (on the front side of substrate 22), integrated circuit devices 24, and metal layers BM0 through BM4 (on the backside of substrate 22) are illustrated. Thin-film transistor 40′ is illustrated as being formed between metal layers BM3 and BM4 in accordance with some embodiments.

Referring again to FIG. 6, electrical connectors 64 are formed. The respective process is illustrated as process 222 in the process flow 200 as shown in FIG. 14. In accordance with some embodiments, electrical connectors 64 include solder regions, which may be formed by plating solder balls on the metal pads of RDLs 60, and reflowing the solder balls. In accordance with alternative embodiments, electrical connectors 64 are formed of non-reflowable (non-solder) metallic materials. For example, electrical connectors 64 may be formed as a copper pads or pillars, and may or may not include nickel capping layers.

When carrier 48 is a glass carrier, carrier 48 may be de-bonded from the underlying wafer 20. Wafer 20 may then be singulated into a plurality of identical device dies 20′. The respective process is illustrated as process 224 in the process flow 200 as shown in FIG. 14. In accordance with alternative embodiments when carrier 48 is a silicon supporting substrate, and is bonded to wafer 20 through fusion bonding, supporting substrate 48 may be removed, or may remain on wafer 20 when singulated. The resulting packages including the supporting substrate (if included) are also referred to as devices dies 20′.

As shown in FIG. 6, in accordance with some embodiments, when thin-film 40 is formed, a True VDD (TVDD) voltage (also referred to as power TVDD or power supply voltage TVDD) may be passed in from electrical connector 64A into device die 20′. The TVDD voltage is conducted through electrical path 72 (which includes the RDLs 60, through-via 26A, metal lines 34, and vias 36) to thin-film transistor 40. The TVDD voltage is provided to source region 144 (also refer to FIG. 8), which is alternatively referred to as a TVDD node. The voltage on drain region 146 may be referred to as a Virtual VDD (VVDD) voltage (also referred to as power VVDD or power supply voltage VVDD). Drain region 146 is tuus referred to as a VVDD node, which receives the power when thin-film transistor 40 is turned on, and is cut from the power when thin-film transistor 40 is turned off. The power VVDD on the VVDD node 146 is provided to integrated circuit devices (a power user circuit) 24A through electrical path 74.

The TVDD voltage may also be conducted to metal line 34T′, which is a part of the top metal lines 34T. The connecting metal line portion that connects the top metal pad of electrical path 72 to metal line 34T′ are not illustrated, and may be in the unillustrated planes. The metal line 34T′ may also be referred to as an always-on node since whenever electrical connector 64A has power, metal line 34T′ has power. Through electrical path 76, voltage TVDD is provided to integrated circuit devices 24B, regardless of whether integrated circuit devices 24A is cut from power or provided with power.

Device die 20′ also have signal through-via 26B, which is connected to electrical connector 64B, and is used to conduct signals to integrated circuit devices 24B.

In accordance with some embodiments, when thin-film transistor 40′ is formed on the backside of semiconductor substrate 22, power TVDD may be passed in from electrical connector 64A to thin-film transistor 40′ through electrical path 72′. Drain region 146′ is a VVDD node, which receives the power when thin-film transistor 40′ is turned on, and is cut from the power when thin-film transistor 40′ is turned off. The power on the VVDD node 146′ is provided to a power user circuit 24A through electrical path 78, which includes the RDLs 60, through-via 26A, metal lines 34, and vias 36. Electrical path 78 may include an upper metal line such as a top metal line 34T in the top metal layer. The electrical path 78 also includes metal lines 34 and vias 36 connecting from the top metal line 34T to integrated circuit devices 24A.

FIG. 12 illustrates a package 120 including device die 20′ in accordance with some embodiments. Device die 20′ is bonded to package component 80. Package component 80 may be a silicon interposer, an organic interposer, a package substrate, a printed circuit board, a package, or the like. Power TVDD may be provided to the electrical connectors 81 of package component 80, and conducted to electrical connector 64A of device die. The power TVDD may be gated by thin-film transistors 40 and/or 40′, and the gated power VVDD and the ungated power TVDD are provided to some integrated circuits.

In accordance with some embodiments, heat sink 84 is attached to package component 80 through adhesive 82. The heat sink 84 may also be attached to device die 20′ through thermal interface material 86.

FIG. 13 illustrates wafer 20 (and device die 20′) formed in accordance with alternative embodiments of the present disclosure. In these embodiments, instead of providing power from the backside of device die 20′, electrical connectors 64′ (including 64A′ and 64B′) are formed on the front side of device die 20′. Power TVDD is also provided from the front side of device die 20′.

The formation process of the structure shown in FIG. 13 is briefly discussed herein. Unless specified otherwise, the materials, the structures, and the formation processes of the components in these embodiments are essentially the same as the like components denoted by like reference numerals in the preceding embodiments. The details regarding the materials, the structures, and the formation processes provided in each of the embodiments throughout the description may be applied to any other embodiment whenever applicable.

The initial steps of these embodiments are essentially the same as shown in FIGS. 1 and 2, except that no through-vias are formed. After the formation of the thin-film transistor 40 and the overlying metal layer Mtop, etch stop layer 90 may be formed over interconnect structure 32. Passivation layer 92 (sometimes referred to as passivation-1 or pass-1) is formed over etch stop layer 90. In accordance with some embodiments, passivation layer 92 is formed of a non-low-k dielectric material having a dielectric constant equal to or greater than the dielectric constant of silicon oxide. Passivation layer 92 may be formed of or comprise an inorganic dielectric material, which may include a material selected from, and is not limited to, Undoped Silicate Glass (USG), silicon nitride (SiN), silicon oxide (SiO₂), silicon oxy-nitride (SiON), silicon oxy-carbide (SiOC), silicon carbide (SiC), or the like, combinations thereof, and/or multi-layers thereof.

In accordance with some embodiments, vias 94 are formed in passivation layer 92 and etch stop layer 90 to electrically connect to the underlying top metal features 34T. Metal pads 96 are further formed over vias 94. In accordance with some embodiments, metal pads 96 comprise aluminum, aluminum copper, or the like. Passivation layer 98 (sometimes referred to as passivation-2 or pass-2) is also formed, and may extend on the sidewalls and the top surfaces of metal pads 96. Passivation layer 98 may be formed of or comprise silicon oxide, silicon nitride, or the like, or multi-layers thereof.

In accordance with some embodiments, dielectric layer 100 is formed, for example, by dispensing a polymer in a flowable form, and then curing the polymer layer. Dielectric layer 100 is patterned to expose metal pads 96. Dielectric layer 100, when formed of polymer, may be formed of or comprise polyimide, polybenzoxazole (PBO), or the like. Alternatively, dielectric layer 100 may be formed of or comprise an in organic dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or the like.

Under-Bump-Metallurgies (UBMs) 102 and bond pads 64′ may be formed to electrically connect to the underlying metal pads 96. The formation processes of UBMs 102 and bond pads 64′ may include forming openings in passivation layer 98 and dielectric layer 100, depositing a blanket metal seed layer extending into the openings, forming a patterned plating mask on the metal seed layer, plating bond pads 64′, removing the plating mask, and etching the portions of the blanket metal seed layer previously covered by the plating mask. In accordance with some embodiments, dielectric layer 106 is formed to have a top surface coplanar with the top surfaces of bond pads 64′, and may be used for hybrid bonding. Other electrical connectors used for other bonding schemes such as solder bonding may also be formed.

In device die 20′, ungated voltage TVDD may be conducted into device die 20′ through bond pad 64A′, and is conducted to the source region 144 of thin-film transistor 40. The gated voltage VVDD at the drain region 146 of thin-film transistor 40 is then conducted to integrated circuit devices 24A. This electrical path is short due to the use of thin-film transistor 40 as the power switch. The voltage conduction path 104 for conducting the power to integrated circuit devices 24A traverses metal layers a single time. The voltage drop is thus low, and the performance of the circuits is improved. This advantageous feature is compounded with the saving of chip area.

As a comparison, if a power switch is formed on semiconductor substrate 22, the ungated voltage TVDD will be conducted down (for example, through electrical path 110A) to the power switch (represented using dashed frame 112) that is below metal layer M0, and the gated voltage VVDD will be conducted upward back to a high metal layer such as metal layer Mtop through electrical paths 110B1 and 110B2, so that it may be distributed back down from the high metal layer. Accordingly, the voltage may have to traverse metal layers three times before the power VVDD is able to reach integrated circuit devices 24A, and the voltage drop is high.

The embodiments of the present disclosure have some advantageous features. By forming power switches in the interconnect structures of device dies such as in the back end of line structures and/or the backside interconnect structures of the device dies, rather than on the surface of semiconductor substrates, the chip area is saved, sometimes as much as between about 4 percent and about 8 percent of the chip area. The speed of the integrated circuits may be increased by about 1.5 percent. The IR drop may be reduced to about 80 percent.

In accordance with some embodiments of the present disclosure, a method comprises forming first integrated circuit devices and second integrated circuit devices on a semiconductor substrate of a wafer; forming a first metal layer as a part of the wafer; forming a transistor comprising a first source/drain region connected to the first integrated circuit devices, wherein the transistor is farther away from the semiconductor substrate than the first metal layer; and forming an electrical connector on a surface of the wafer, wherein the electrical connector is electrically connected to a second source/drain region of the transistor. In an embodiment, the forming the transistor comprises forming a metal oxide layer as a channel layer; forming a gate dielectric contacting the metal oxide layer; forming a gate electrode contacting the gate dielectric; and forming a source region and a drain region contacting the metal oxide layer.

In an embodiment, the method further comprises forming a second metal layer farther away from the semiconductor substrate than the first metal layer, wherein the metal oxide layer is formed between the first metal layer and the second metal layer. In an embodiment, the transistor is formed on a front side of the wafer. In an embodiment, the electrical connector is on a backside of the wafer, and wherein the method further comprises forming a through-via penetrating through the semiconductor substrate, wherein the through-via electrically connects the electrical connector to the second source/drain region of the transistor.

In an embodiment, the method further comprises forming a first electrical path connecting the through-via to the second source/drain region; and forming a second electrical path connecting the first source/drain region to the first integrated circuit devices, wherein the first electrical path and the second electrical path comprise portions in a plurality of metal layers.

In an embodiment, the electrical connector is on a front side of the wafer, and wherein the method further comprises forming a first electrical path connecting the electrical connector to the second source/drain region; and forming a second electrical path connecting the first source/drain region to the first integrated circuit devices, wherein a part of the first electrical path is farther away from the semiconductor substrate than an entirety of the second electrical path. In an embodiment, the transistor is formed on a backside of the wafer.

In an embodiment, both of the electrical connector and the transistor are formed on the backside of the wafer, and wherein the method further comprises forming a through-via penetrating through the semiconductor substrate, wherein the through-via connects the electrical connector to the second source/drain region. In an embodiment, the method further comprises forming second integrated circuit devices, wherein the second integrated circuit devices are configured to have power when the first integrated circuit devices are cut from power.

In accordance with some embodiments of the present disclosure, a structure comprises a semiconductor substrate; integrated circuit devices at a surface of the semiconductor substrate; an electrical connector; a plurality of metal layers on the semiconductor substrate, wherein the plurality of metal layers comprise an electrical path extending from a topmost end to a bottommost end of the plurality of metal layers; and a transistor comprising a first source/drain region connecting to the electrical connector; and a second source/drain region connecting to the integrated circuit devices through the first electrical path. In an embodiment, the transistor comprises a metal oxide layer as a channel layer.

In an embodiment, the channel layer comprises InGaZnO. In an embodiment, the structure further comprises a first metal layer spaced apart from the semiconductor substrate by the plurality of metal layers; and a second metal layer spaced apart from the semiconductor substrate by the first metal layer, wherein the transistor comprises a portion between the first metal layer and the second metal layer. In an embodiment, the transistor is configured to gate a power to the integrated circuit devices. In an embodiment, both of the transistor and the integrated circuit devices are on a front side of the semiconductor substrate. In an embodiment, the integrated circuit devices are on a front side of the semiconductor substrate, and the transistor is on a backside of the semiconductor substrate.

In accordance with some embodiments of the present disclosure, a structure comprises a semiconductor substrate; integrated circuit devices on a surface of the semiconductor substrate; a plurality of metal layers over integrated circuit devices; and a transistor over the plurality of metal layers, wherein a drain region of the transistor is connected to the integrated circuit devices through a first electrical path in the plurality of metal layers, and wherein the transistor is configured to gate a power supply voltage that is on a source region of the transistor. In an embodiment, the semiconductor substrate and the transistor are comprised in a device die, and the device die further comprises an electrical connector electrically connecting to the source region of the transistor; a second electrical path in the plurality of metal layer; and a through-via penetrating through the semiconductor substrate, wherein a top metal line in a top metal layer of the plurality of metal layers connects the through-via to the source region of the transistor. In an embodiment, the transistor is configured to provide power to the integrated circuit devices when the transistor is turned on, and is configured to cut off power to the integrated circuit devices when the transistor is turned off.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method comprising: forming first integrated circuit devices and second integrated circuit devices on a semiconductor substrate of a wafer;forming a first metal layer as a part of the wafer;forming a transistor comprising a first source/drain region connected to the first integrated circuit devices, wherein the transistor is farther away from the semiconductor substrate than the first metal layer; andforming an electrical connector on a surface of the wafer, wherein the electrical connector is electrically connected to a second source/drain region of the transistor.

2. The method of claim 1, wherein the forming the transistor comprises: forming a metal oxide layer as a channel layer;forming a gate dielectric contacting the metal oxide layer;forming a gate electrode contacting the gate dielectric; andforming a source region and a drain region contacting the metal oxide layer.

3. The method of claim 1 further comprising forming a second metal layer farther away from the semiconductor substrate than the first metal layer, wherein the metal oxide layer is formed between the first metal layer and the second metal layer.

4. The method of claim 1, wherein the transistor is formed on a front side of the wafer.

5. The method of claim 4, wherein the electrical connector is on a backside of the wafer, and wherein the method further comprises: forming a through-via penetrating through the semiconductor substrate, wherein the through-via electrically connects the electrical connector to the second source/drain region of the transistor.

6. The method of claim 5 further comprising: forming a first electrical path connecting the through-via to the second source/drain region; andforming a second electrical path connecting the first source/drain region to the first integrated circuit devices, wherein the first electrical path and the second electrical path comprise portions in a plurality of metal layers.

7. The method of claim 4, wherein the electrical connector is on a front side of the wafer, and wherein the method further comprises: forming a first electrical path connecting the electrical connector to the second source/drain region; andforming a second electrical path connecting the first source/drain region to the first integrated circuit devices, wherein a part of the first electrical path is farther away from the semiconductor substrate than an entirety of the second electrical path.

8. The method of claim 1, wherein the transistor is formed on a backside of the wafer.

9. The method of claim 8, wherein both of the electrical connector and the transistor are formed on the backside of the wafer, and wherein the method further comprises: forming a through-via penetrating through the semiconductor substrate, wherein the through-via connects the electrical connector to the second source/drain region.

10. The method of claim 8 further comprising forming second integrated circuit devices, wherein the second integrated circuit devices are configured to have power when the first integrated circuit devices are cut from power.

11. A structure comprising: a semiconductor substrate;integrated circuit devices at a surface of the semiconductor substrate;an electrical connector;a plurality of metal layers on the semiconductor substrate, wherein the plurality of metal layers comprise an electrical path extending from a topmost end to a bottommost end of the plurality of metal layers; anda transistor comprising: a first source/drain region connecting to the electrical connector; anda second source/drain region connecting to the integrated circuit devices through the first electrical path.

12. The structure of claim 11, wherein the transistor comprises a metal oxide layer as a channel layer.

13. The structure of claim 11, wherein the channel layer comprises InGaZnO.

14. The structure of claim 11 further comprising: a first metal layer spaced apart from the semiconductor substrate by the plurality of metal layers; anda second metal layer spaced apart from the semiconductor substrate by the first metal layer, wherein the transistor comprises a portion between the first metal layer and the second metal layer.

15. The structure of claim 11, wherein the transistor is configured to gate a power to the integrated circuit devices.

16. The structure of claim 11, wherein both of the transistor and the integrated circuit devices are on a front side of the semiconductor substrate.

17. The structure of claim 11, wherein the integrated circuit devices are on a front side of the semiconductor substrate, and the transistor is on a backside of the semiconductor substrate.

18. A structure comprising: a semiconductor substrate;integrated circuit devices on a surface of the semiconductor substrate;a plurality of metal layers over integrated circuit devices; anda transistor over the plurality of metal layers, wherein a drain region of the transistor is connected to the integrated circuit devices through a first electrical path in the plurality of metal layers, and wherein the transistor is configured to gate a power supply voltage that is on a source region of the transistor.

19. The structure of claim 18, wherein the semiconductor substrate and the transistor are comprised in a device die, and the device die further comprises: an electrical connector electrically connecting to the source region of the transistor;a second electrical path in the plurality of metal layer; anda through-via penetrating through the semiconductor substrate, wherein a top metal line in a top metal layer of the plurality of metal layers connects the through-via to the source region of the transistor.

20. The structure of claim 18, wherein the transistor is configured to provide power to the integrated circuit devices when the transistor is turned on, and is configured to cut off power to the integrated circuit devices when the transistor is turned off.