1. Field of the Invention
The present invention relates to a printed wiring board and a method for manufacturing the same.
2. Discussion of the Background
As to a printed wiring board and a method for manufacturing the same, what is described in the Japanese Patent No. 3795270 has been put forth. The Patent Document No. 3795270 describes a multilayer printed wiring board in which in a single substrate a high density region where conductor bumps are formed in a high density and a low density region where conductor bumps are formed in a low density are concurrently present, and these high density region and low density region are arranged in appropriate combinations. The contents of this publication are incorporated herein by reference in their entirety.
According to one aspect of the present invention, a printed wiring board includes a first substrate having a recess portion and multiple conductors, a second substrate having multiple conductors and inserted in the recess portion of the first substrate such that the first substrate has a surface exposing at least a portion of a surface of the second substrate. The multiple conductors in the first substrate is electrically connected to the multiple conductors in the second substrate, and the second substrate has density of the conductors which is higher than density of the conductors of the first substrate.
According to another aspect of the present invention, a method for manufacturing a printed wiring board includes forming a first substrate having multiple conductors, forming from a single substrate multiple second substrates each having multiple conductors, forming a recess portion for inserting one or more of the second substrates in the first substrate, disposing one or more of the second substrates in the recess portion formed in the first substrate such that one or more of the second substrates has at least a portion of a surface exposed at a surface of the first substrate, and electrically connecting the multiple conductors in the first substrate and the multiple conductors in the second substrates.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
a) through (d) are sectional views illustrating a step of forming the first wiring layer of the second substrate under a method for the manufacture of the same embodiment;
a) through (e) are sectional views illustrating a step of forming the second wiring layer of the second substrate under a method for the manufacture of the same embodiment;
a) through (e) are sectional views illustrating a step of forming the third wiring layer of the second substrate under a method for the manufacture of the same embodiment;
a) through (c) are sectional views illustrating a modified example of a method for manufacturing a printed wiring board.
The embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
A printed wiring board pertaining to one embodiment in accordance with the present invention is, as a sectional structure thereof is illustrated in
The first substrate 10 is provided with a non-flexible base material (10a) (corresponding to the core substrate of the first substrate 10) containing an inorganic material, for example, (glass cloth, silica filler, glass filler, to give examples). This non-flexible substrate (10a) has, as illustrated with dotted lines in
The second substrate 20 is provided, as illustrated in
The second substrate 20 is disposed in a recess portion (indentation portion) (100a) of the first substrate 10 and flip-chip mounted onto the first substrate 10. The bump metals (26c) of the second substrate 20 are directly joined to the terminals (lands) provided on the circuit of the first substrate 10 by being so-called face-down. As such, the first substrate 10 and the second substrate 20 are electrically connected. The structure being as such, the first substrate 10 and the second substrate 20 can easily be electrically connected.
It is set up such that the number of wiring layers per unit thickness with respect to the second substrate 20 is greater than the number of wiring layers per unit thickness with respect to the first substrate 10 (a number of wiring layers within a given thickness (a certain thickness as a unit, “a unit thickness”)), and upon the number of wiring layers in the regions of the same thickness between the two, it results in the second substrate 20 being higher in the density of the conductors present than the first substrate 10. As such, when it comes to said printed wiring board, the number of wiring boards formed with the conductors of the second substrate 20 is greater than the number of wiring layers in the first substrate 10 in the regions of the same thickness as that of the second substrate 20. The structure being as such, a high-density conductor region can be easily be formed, which in turn allows said printed wiring board to be easily fine-pitched in portions as well.
And, the thickness of at least a portion of the wiring layers (conductor circuits) of the second substrate 20 is the same as the thickness of the conductor circuits of the first substrate 10. However, the thickness of at least a portion of the conductor circuits of the second substrate 20 may be thinner than the thickness of the conductor circuits of the first substrate 10.
There is present a filling of a resin 30 composed of RCF (Resin Coated Copper Foil), for example, (or possibly a prepreg, etc.) between the first substrate 10 and the second substrate 20. Namely, the first substrate 10 and the second substrate 20 are physically mutually connected and adhered (insulated electrically) via the resin 30. This resin 30 may be composed of the same material as the resin constituting an insulating material 31-34.
As such, the connection between the first substrate 10 and the second substrate 20 via the resin 30 enhances the adhesion force between the first substrate 10 and the second substrate 20. And, the resin 30 filling in constitutes a buffer material allowing the connection reliability of the wiring of the second substrate 20 having a higher wiring density than the first substrate 10 to be enhanced on account of an impact, when the impact is applied from the outside as well, not being directly transmitted to the second substrate 20. And, the embedding of the second substrate 20 separately fabricated allows the complicated steps that come with a build-up to be simplified. Further, since the rigidity of the insulating layer of the first substrate 10 is greater than that of the insulating layer of the second substrate 20, the stress applied to the second substrate 20 can be eased.
When it comes to the manufacture of such printed wiring boards, a considerable number (around “32 units,” for example) of the first substrates on a single substrate 100 and a considerable number (around “96 units,” for example) of the second substrates on a single substrate 200 are manufactured with a semiconductor process respectively.
To be specific, the first substrates 10 and the second substrates 20 are manufactured by wiring layers being sequentially laminated on the front and back of the core substrates (non-flexible substrates) (10a, 20a) respectively via insulating layers. Since these first substrates 10 and second substrates 20 are, while differing in the number of wiring layers, fundamentally manufactured with similar processes, only the manufacture process of the second substrates 20 is herein indicated in details and the details of the manufacture process of the first substrates 10 are omitted.
When it comes to the fabrication of the second substrates 20, a non-flexible base material (20a) having on the front and back copper foils (601a, 601b) is prepared, as illustrated in
When it comes to the formation of the second wiring layer, on the front and back of the structure on which the above-described first wiring layers are formed there are disposed insulating materials 31, 32 composed of a prepreg, for example, and conductor films (604a, 604b) composed of a copper foil, for example. And, a pressure is applied to the conductor films (604a, 604b) being the outermost layers with a hydropress device, for example, and the structure in the entirety thereof is pressure-pressed, as illustrated in
Next, it undergoes trimming (edge-face cutting and imprinting), hole-boring for alignment, soft-etching, and laser pre-treatment, and vias 605 are formed with laser, as illustrated in
Continuing on, the conductor films (606a, 606b) are patterned with a predetermined photo etching (acid washing, resist laminate, direct depicting (exposure), development, etching, stripping, etc., for example) to form wiring layers 23, 24, as illustrated in
When it comes to the formation of the third wiring layers, on the front and back of the structure constituting the above-described first wiring layers and second wiring layers there are disposed insulating materials 33, 34 composed of a prepreg, for example, and conductor films (607a, 607b) composed of a copper foil, for example. And, a pressure is applied to the conductor films (607a, 607b) being the outermost layers with a hydropress device, for example, and the structure in the entirety thereof is pressure-pressed, as illustrated in
Next, it undergoes trimming (edge-face cutting and imprinting), hole-boring for alignment, soft-etching, and laser pre-treatment, and vias (via structures) 608 are formed with laser, as illustrated in
Continuing on, the conductor films (609a, 609b) are patterned with a predetermined photo etching (acid washing, resist laminate, direct depicting (exposure), development, etching, stripping, etc., for example) to form wiring layers 25, 26, as illustrated in
The first substrate 10 can also be fabricated by wiring layers 11-18 each via an interlaminar insulating layer on the front and back of a non-flexible substrate 10a through the steps following the steps illustrated in
Following the fabrication of the first substrates 10 and the second substrates 20 as in the above, those substrates 10, 20 formed on the substrate 100 and the substrate 200 are checked as to pass (defect-free) or fail (defective), and a determination is made, among them, as to which substrates are normal (defect-free) and which substrates are abnormal (defective). The substrates 10, 20 determined to be failed (defective) are discarded as necessary. In addition, as to the inspection of substrates 10, 20, they are subjected to an inspection with an image checker, etc., for example. Further, then, substrates 10, 20 are subjected to black-oxide treatment.
Next, as illustrated in
Continuing on, the second substrate 20 determined to be normal (defect-free) with the above-described inspection is cut out as a chip in a predetermined size with a laser, for example, of a single substrate 200, as illustrated in
The placement of this second substrate 20 places the surfaces of the first substrate 10 and of the second substrate 20 on a near alignment. However, it is not limited to this, and as long as it is exposed, the surface of the second substrate 10 may be higher or lower than the surface of the first substrate 10.
And, with the use of a dispenser the gaps (D1, D2) between the first substrate 10 and the second substrate 20 (
In addition, one embodiment described in the above may be carried out as modified in the following.
It may be such that at least one electronic component is electrically connected to at least either the first substrate 10 or the second substrate 20. As illustrated in
The second substrate being higher in the density of conductors present than the first substrate is not limited to one being greater in the number of wiring layers per unit thickness than the first substrate. As illustrated in
The above-described embodiment was such that the first substrate 10 and the second substrate 20 were electrically connected with flip-chip connection. The flip-chip connection of these two substrates allows an electrical connection between the first substrate 10 and the second substrate 20 even when the conductor density of the second substrate 20 ends up being higher. However, it is not limited to this, and a method for connecting the two substrates is optional. As illustrated in
Further, the materials, etc., for electrodes and for wiring for connecting the two substrates are also optional. The two substrates may be mutually electrically connected with an ACF (Anisotropic Conductive Film) connection or an Au—Au connection. When it comes to the ACF connection, the positioning of the first substrate 10 and the second substrate 20 for the connection can easily be done. And, when it comes to the Au—Au connection, a connection portion highly resistant to corrosion can be formed.
It may be set up such that multiple second substrates may be disposed on the surface of one first substrate. As illustrated in
When it comes to the above-described embodiment, while the two substrates are connected such that the surface of the first substrate and the surface of the second substrate are aligned at the equal height, it is not limited to this, and, as illustrated in
Further, as illustrated in
The materials for the first substrate 10 and the second substrate 20 are optional. These substrates 10, 20 may be composed of the same material as the other and of different materials.
The shape, position, arrangement at that position, etc., of the second substrate are also optional. As illustrated in
As illustrated in
In the above-described embodiment, while the recess portion (100a) is formed following the inspection of the first substrate 10 and the second substrate 20, it may be such that following the formation of the recess portion (100a) each substrate is inspected.
The shape and size of the recess portion (100a) is optional. However, the shape and size corresponding to the second substrate 20 are preferred in terms of the positioning of the second substrate 20.
The formation of a recess portion is not limited to a method of removing a portion corresponding to the space thereof with laser, etching, etc., and it may be that while a sacrificial material 311 is in advance provided on a substrate 310, as illustrated in
The features of a printed wiring board pertaining to the first aspect in accordance with the present invention are such that it is provided with the first substrate on which conductors are formed and with at least one second substrate wherein the density of conductors present is higher than that of the first substrate, that the previously-described second substrate is inserted into the previously-described first substrate such that at least a portion of the main surface of the previously-described second substrate is exposed at the surface of the previously-described first substrate, and concurrently that the conductors on the previously-described first substrate and the conductors on the previously-described second substrate are electrically connected.
The structure may be such that the number of wiring layers formed with the conductors on the previously-described second substrate is greater than the number of wiring layers of the previously-described first substrate in the region having the same thickness as that of the previously-described second substrate.
The structure may be such that each of the previously-described first substrate and the previously-described second substrate has an insulating layer and that the density of conductors present on the insulating layer of the previously-described second substrate is formed such that it is higher than the density of the conductors present on the insulating layer of the previously-described first substrate.
The structure may be such that the previously-described first substrate and the previously-described second substrate have a lower wiring layer and an upper wiring layer electrically connected via vias in an interlaminar insulating layer and that the number of vias per unit interlaminar insulating layer with respect to the previously-described second substrate is greater than the number of vias per unit interlaminar insulating layer with respect to the previously-described first substrate.
The structure may be such that the previously-described first substrate and the previously-described second substrate are electrically connected with flip chip connection.
The structure may be such that the previously-described first substrate and the previously-described second substrate are spacedly disposed and that there is present a resin in at least a portion of the space between the previously-described first substrate and the previously-described second substrate.
The structure may be such that at least one of the previously-described first substrate and the previously-described second substrate has an insulating layer containing an inorganic material.
The structure may be such that at least one of the insulating layer of the previously-described first substrate and the insulating layer of the previously-described second substrate has at least one cloth layer with the previously-described inorganic material.
The structure may be such that the number of insulating layers containing the inorganic material of the previously-described first substrate is greater than the number of insulating layers containing the inorganic material of the previously-described second substrate.
The structure may be such that the thickness of at least a portion of the conductors of the previously-described second substrate is no greater than the thickness of the conductors of the previously-described first substrate.
The structure may be such that at least one electronic component is electrically connected to at least one of the previously-described first substrate or the previously-described second substrate.
The structure may be such that at least one electronic component is electrically connected to the previously-described second substrate.
The features of a method for manufacturing a printed wiring board pertaining to the second aspect in accordance with the present invention are such that it comprises the first step of fabricating the first substrate having conductors, the second step of fabricating with a single substrate a considerable number of the second substrates having conductors, the third step of forming an indentation in the first substrate fabricated with the previously-described first step, the fourth step of disposing, of the previously-described second substrates, one or more substrates in the indentation formed with the previously-described third step, and the fifth step of electrically connecting the conductors of the previously-described first substrate and the conductors of the previously-described second substrates.
It may be such that a step of substrate inspection for inspecting, prior to the previously-described fourth step, the pass or failure of each of the first substrate fabricated with the previously-described first step and the second substrates fabricated with the previously-described second step is provided, and that one or more substrates of the second substrates determined to be normal under the previously-described substrate inspection step are disposed in the previously-described indentation in the first substrate determined to be normal under the previously-described substrate inspection step.
It may be such that under the previously-described third step an indentation having a space to the extent that it allows the determination of the positioning when the previously-described second substrates are disposed.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
The present application claims the benefits of priority to U.S. Application No. 61/071,909, filed May 23, 2008. The contents of that application are incorporated herein by reference in their entirety.
Number | Name | Date | Kind |
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5562971 | Tsuru et al. | Oct 1996 | A |
5847935 | Thaler et al. | Dec 1998 | A |
5858145 | Sreeram et al. | Jan 1999 | A |
6281446 | Sakamoto et al. | Aug 2001 | B1 |
7019221 | Noda | Mar 2006 | B1 |
7886438 | Ito et al. | Feb 2011 | B2 |
Number | Date | Country |
---|---|---|
2 346 740 | Aug 2000 | GB |
11-317582 | Nov 1999 | JP |
2000-165007 | Jun 2000 | JP |
3795270 | Apr 2006 | JP |
Number | Date | Country | |
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20090290318 A1 | Nov 2009 | US |
Number | Date | Country | |
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61071909 | May 2008 | US |