Patent Application
20240431031
The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2023-102916, filed Jun. 23, 2023, the entire contents of which are incorporated herein by reference.
The present invention relates to a printed wiring board.
Japanese Patent Application Laid-Open Publication No. 2000-114719 describes that a roughened layer formed of Cu—Ni—P is formed on a conductor circuit. The entire contents of this publication are incorporated herein by reference.
According to one aspect of the present invention, a printed wiring board includes a first resin insulating layer, a connection conductor layer formed on the first resin insulating layer and including a connection wiring, a second resin insulating layer formed on the first insulating layer such that the second resin insulating layer is covering the connection conductor layer, a mounting conductor layer formed on the second resin insulating layer and including a first electrode and a second electrode such that the first electrode mounts a first electronic component and that the second electrode mounts a second electronic component, and connection via conductors formed in the second resin insulating layer and including a first connection via conductor and a second connection via conductor such that the first connection via conductor electrically connects the first electrode in the mounting conductor layer and the connection wiring in the connection conductor layer and that the second connection via conductor electrically connects the second electrode in the mounting conductor layer and the connection wiring in the connection conductor layer. The connection conductor layer includes a seed layer and an electrolytic plating layer formed on the seed layer such that the seed layer includes a first layer formed on the first resin insulating layer and a second layer formed on the first layer, a width of the first layer is larger than a width of the second layer, and a width of the electrolytic plating layer is larger than the width of the first layer of the seed layer.
According to another aspect of the present invention, a method for manufacturing a printed wiring board includes forming a connection conductor layer on a first resin insulating layer such that the connection conductor layer includes a connection wiring, forming a second resin insulating layer on the first insulating layer such that the second resin insulating layer is covering the connection conductor layer, forming a mounting conductor layer on the second resin insulating layer such that the mounting conductor layer includes a first electrode that mounts a first electronic component and a second electrode that mounts a second electronic component, and forming connection via conductors in the second resin insulating layer such that the connection via conductors include a first connection via conductor and a second connection via conductor, that the first connection via conductor electrically connects the first electrode in the mounting conductor layer and the connection wiring in the connection conductor layer and that the second connection via conductor electrically connects the second electrode in the mounting conductor layer and the connection wiring in the connection conductor layer. The forming the connection conductor layer includes forming a seed layer and an electrolytic plating layer on the seed layer such that the seed layer includes a first layer formed on the first resin insulating layer and a second layer formed on the first layer, a width of the first layer is larger than a width of the second layer, and a width of the electrolytic plating layer is larger than the width of the first layer of the seed layer.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
As illustrated in
The connection conductor layer 30 includes the connection wirings 36. Data is transmitted from the first electronic component (E1) to the second electronic component (E2) via the connection wirings 36. The connection wirings 36 are each a part of a path for transmitting data from the first electronic component (E1) to the second electronic component (E2). The mounting conductor layer 130 includes electrodes (131, 132, 133, 134). The bumps 241, the electrodes 131, and the via conductors 141 are formed in a path (first path) between the first electronic component (E1) and the connection wirings 36. The first path is positioned directly below the first electronic component (E1). The bumps 242, the electrodes 132, and the via conductors 142 are formed in a path (second path) between the second electronic component (E2) and the connection wirings 36. The second path is positioned directly below the second electronic component (E2). The bumps 241, the electrodes 131, the via conductors 141, the bumps 242, the electrodes 132, and the via conductors 142 are also a part of a path. The bumps (241, 242) can be referred to as connection bumps (connection metal posts). The connection bumps 241 positioned directly below the first electronic component (E1) are first connection bumps (first connection metal posts), and the connection bumps 242 positioned directly below the second electronic component (E2) are second connection bumps (second connection metal posts). The electrodes (131, 132) can be referred to as connection electrodes. The connection electrodes 131 positioned directly below the first electronic component (E1) are first connection electrodes, and the connection electrodes 132 positioned directly below the second electronic component (E2) are second connection electrodes. The via conductors (141, 142) can be referred to as connection conductors. The connection via conductors 141 positioned directly below the first electronic component (E1) are first connection via conductors, and the connection via conductor 142 positioned directly below the second electronic component (E2) are second connection via conductors. The first connection bumps may also be referred to as first bumps (first metal posts). The first connection electrodes may also be referred to as first electrodes. The first connection via conductors may also be referred to as first via conductors. The second connection bumps may also be referred to as second bumps (second metal posts). The second connection electrodes may also be referred to as second electrodes. The second connection via conductors may also be referred to as second via conductors. The first bumps, the first electrodes, and the first via conductors, which are positioned directly below the first electronic component (E1) and electrically connected to the connection wirings 36, form the first path. The second bumps, the second electrodes, and the second via conductors, which are positioned directly below the second electronic component (E2) and electrically connected to the connection wirings 36, form the second path.
The via conductors (41, 42, 143, 144), the electrodes (133, 134) and the bumps (243, 244) do not form a path. These via conductors (41, 42, 143, 144), electrodes (133, 134) and bumps (243, 244) are electrically connected to power lines or ground lines in the electronic components. These via conductors (41, 42, 143, 144), electrodes (133, 134) and bumps (243, 244) are independent of the connection wirings 36. These via conductors (41, 42, 143, 144), electrodes (133, 134) and bumps (243, 244) are not electrically connected to the connection wirings 36.
As illustrated in
The resin insulating layer (first resin insulating layer) 20 is formed on the conductor layer 10. The resin insulating layer 20 has a first surface (20a) and a second surface (20b) on the opposite side with respect to the first surface (20a). The second surface (20b) of the resin insulating layer 20 forms the lower surface (2b) of the printed wiring board 2. The second surface (20b) of the resin insulating layer 20 faces the conductor layer 10. The resin insulating layer 20 has openings (via conductor openings) (21, 22) exposing the conductor layer 10. The openings 21 are positioned directly below the first mounting region (A1) and expose the pads 12. The openings 21 extend from the first surface (20a) of the resin insulating layer 20 to the pads 12. The openings 22 are positioned directly below the second mounting region (A2) and expose the pads 14. The openings 22 extend from the first surface (20a) of the resin insulating layer 20 to the pads 14. The resin insulating layer 20 is formed of a resin 80 and a large number of inorganic particles 90 dispersed in the resin 80. The resin 80 is an epoxy resin. Examples of the resin include a thermosetting resin and a photocurable resin. The inorganic particles 90 are glass particles. It is also possible that the inorganic particles 90 are alumina particles.
As illustrated in
The first surface (20a) of the resin insulating layer 20 is formed only of the resin 80. The inorganic particles 90 (second inorganic particles 92) are not exposed from the first surface (20a). The first surface (20a) does not include surfaces of the second inorganic particles 92. No unevenness is formed on the first surface (20a) of the resin insulating layer 20. The first surface (20a) is not roughened. The first surface (20a) is formed smooth.
As illustrated in
The flat parts (91a) of the first inorganic particles 91 substantially coincide with a surface obtained by extending a surface (80a) of the resin 80 formed around the first inorganic particles 91 (a surface that forms the inner wall surface 23). The flat parts (91a) drawn with substantially straight lines in
As illustrated in
In the cross-sections illustrated in
An inner wall surface can have steps between the exposed surfaces (91b) of the first inorganic particles 91 and the surface (80a) of the resin 80 surrounding the first inorganic particles 91 that have the exposed surfaces (91b). The exposed surfaces (91b) are recessed from the surface (80a) of the resin 80. Or, the exposed surfaces (91b) protrude from the surface (80a) of the resin 80. For example, there are steps between the exposed surfaces (91b) and the surface (80a) of the resin 80. Sizes of the steps (distances from the exposed surfaces (91b) to the surface (80a) of the resin 80) are 5 μm or less. The sizes of the steps are preferably 3.0 μm or less. The sizes of the steps are more preferably 1.5 μm or less. Even when the steps are formed, since the steps are small, the exposed surfaces (91b) and the surface (80a) of the resin 80 form a substantially common surface.
The openings (21, 22) formed in the resin insulating layer 20 are similar. The openings (21, 22) formed in the resin insulating layer 20 have similar inner wall surfaces (23, 24). The inner wall surfaces (23, 24) of the openings (21, 22) are each formed of the surface (80a) of the resin 80 and the exposed surfaces (91b) of the first inorganic particles 91.
As illustrated in
The connection wirings 36 are formed substantially parallel to each other. Among the multiple connection wirings 36, a connection wiring 36 having a smallest width (W1) is a smallest connection wiring (36a). The width (W1) of the smallest connection wiring (36a) is 1 μm or more and 3 μm or less. There are spaces 37 between adjacent connection wirings 36. Among the multiple spaces 37, a space 37 having a smallest width (G1) is a smallest space (37a). The width (G1) of the smallest space (37a) is 1 μm or more and 3 m or less.
Among the multiple connection wirings 36, a connection wiring 36 having a largest width (W2) is a largest connection wiring (36b). The width (W2) of the largest connection wiring (36b) is 5 μm or less. The width (W2) of the largest connection wiring (36b) is preferably 3 μm or less. Among the multiple spaces 37, a space with a largest width (G2) is a largest space (37b). The width (G2) of the largest space (37b) is 5 μm or less. The width (G2) of the largest space (37b) is preferably 3 μm or less.
The connection wirings 36 preferably each have a width of 1 μm or more and 3 μm or less. The spaces 37 preferably each have a width of 1 μm or more and 3 μm or less.
The connection wirings 36 each have an aspect ratio (thickness/width). The aspect ratio is 2.0 or more and 4.0 or less. The connection wirings 36 preferably each have a thickness of 3 μm or more and 7 μm or less.
The connection conductor layer 30 is mainly formed of copper. The connection conductor layer 30 is formed of a seed layer (30a) on the first surface (20a) of the resin insulating layer 20 and an electrolytic plating layer (30b) on the seed layer (30a). The seed layer (30a) is formed by sputtering. The seed layer (30a) is formed of a first layer (31a) on the first surface (20a) of the resin insulating layer 20 and a second layer (31b) on the first layer (31a). The first layer (31a) is in contact with the first surface (20a) of the resin insulating layer 20. For example, the first layer (31a) of the seed layer (30a) is formed of a copper alloy, and the second layer (31b) is formed of copper. The first layer (31a) and the second layer (31b) are formed by sputtering. Both are sputtering films.
The first layer (31a) is formed of an alloy containing copper, aluminum, and a specific metal. Examples of the specific metal include nickel, zinc, gallium, silicon, and magnesium. The alloy preferably contains one type of specific metal, or two types of specific metals, or three types of specific metals. A content of aluminum in the alloy is 1.0 at % or more and 15.0 at % or less. An example of the specific metal is silicon. A content of the specific metal in the alloy is 0.5 at % or more and 10.0 at % or less. The first layer (31a) may contain impurities. Examples of the impurities include oxygen and carbon. The first layer (31a) can contain oxygen or carbon. The first layer (31a) can contain oxygen and carbon. In the embodiment, the alloy further contains carbon. A content of carbon in the alloy is 50 ppm or less. The alloy further contains oxygen. A content of oxygen in the alloy is 100 ppm or less. The values of the contents of the elements described above are examples. Among the elements forming the first layer (31a), copper has the largest content. The content of aluminum is the next largest. The content of the specific metal is less than the content of aluminum. Therefore, copper is a primary metal, aluminum is a first secondary metal, and the specific metal is a second secondary metal. A content of the impurities is smaller than the content of the specific metal.
The second layer (31b) is formed of copper. A content of copper forming the second layer (31b) is 99.9 at % or more. The content of copper in the second layer (31b) is preferably 99.95 at % or more. The electrolytic plating layer (30b) is formed of copper. A content of copper forming the electrolytic plating layer (30b) is 99.9 at % or more. The content of copper in the electrolytic plating layer (30b) is preferably 99.95 at % or more.
A width of the seed layer (30a) of each of the connection wirings 36 is smaller than a width of the electrolytic plating layer (30b). The width of each of the connection wirings 36 is smallest at a boundary portion (B) between the seed layer (30a) and the electrolytic plating layer (30b). A width (D2) of the first layer (31a) is larger than a width (D3) of the second layer (31b), and a width (D1) of the electrolytic plating layer (30b) is larger than the width (D2) of the first layer (31a). The widths (D1, D2, D3) are measured using a cross-sectional view such as
The width (D1) is a distance between two surfaces of the electrolytic plating layer (30b), the two surfaces extending from an upper surface of the electrolytic plating layer (30b) toward the first surface (20a). The upper surface of the electrolytic plating layer (30b) is a surface that is away from the seed layer (30a). The surfaces used for measuring the width (D1) form side surfaces (sidewalls) of the electrolytic plating layer (30b). The width of each of the connection wirings 36 may be represented by the width (D1). The width (D1) is measured near the upper surface of the conductor circuit. The width (D2) is measured on the first surface (20a). The width (D3) is measured at an interface between the second layer (31b) and the electrolytic plating layer (30b).
As illustrated in
By making the width (D3) of the second layer (31b) smaller than the width (D1) of the electrolytic plating layer (30b) and the width (D2) of the first layer (31a), sidewalls of each of the connection wirings 36 each have a recess 38. The two sidewalls (side surfaces) of each of the connection wirings 36 each have the recess 38. A region surrounded by a side surface of the electrolytic plating layer (30b), the first surface (20a), and an actual side surface of the each of the connection wirings 36 forms the recess 38. The actual side surface includes a side surface of the seed layer (30a). The recess 38 is filled with the resin insulating layer 120. Similar to the resin insulating layer 20, the resin insulating layer 120 is formed of a resin 80 and inorganic particles 90 (first inorganic particles 91 and second inorganic particles 92) (
Other conductor circuits (such as pads (32, 34)) in the connection conductor layer 30 and the connection wirings 36 are similar. Conductor circuits (such as the first electrode 131 and the second electrodes 132) in the mounting conductor layer 130 and the connection wirings 36 are similar. Conductor circuits other than the connection wirings 36 may have recesses 38 as shown in
In the embodiment, an adhesive layer 100 can be formed on a surface (including upper and side surfaces) of the connection conductor layer 30. The surface of the connection conductor layer 30 is formed of a first surface and a second surface. Of the surface, the first surface is a portion that is exposed by the via conductor openings. The second surface is a portion other than the first surface. The first surface is not covered by the adhesive layer 100, and the second surface is covered by the adhesive layer 100. The adhesive layer 100 is in contact with the connection conductor layer 30. The adhesive layer 100 is in contact with the second surface of the connection conductor layer 30. The adhesive layer 100 is formed of resin. The adhesive layer 100 is formed of an organic material (organic resin). An example of the organic material is a nitrogen-based organic compound. The nitrogen-based organic compound is, for example, a tetrazole compound. Examples of the nitrogen-based organic compound are described in Japanese Patent Application Laid-Open Publication No. 2015-54987. The adhesive layer 100 does not cover the first surface (20a) of the resin insulating layer 20 exposed from the connection conductor layer 30. The adhesive layer 100 is formed between the connection conductor layer 30 and the second resin insulating layer 120. The adhesive layer 100 is sandwiched between the connection conductor layer 30 and the resin insulating layer (second resin insulating layer) 120. The adhesive layer 100 adheres the connection conductor layer 30 and the resin insulating layer 120. The connection wirings 36 can have only the second surface.
The smooth film 102 has a substantially uniform thickness (T). The thickness (T) of the smooth film 102 is 10 nm or more and 120 nm or less. A ratio (S1/S2) of an area (S1) of the smooth film 102 exposed from the protruding parts 104 to an area (S2) of the adhesive layer 100 is 0.1 or more and 0.5 or less. The smooth film 102 on the second surface of the connection conductor layer 30 is formed substantially along a shape of the second surface of the connection conductor layer 30. When undulations are formed on the upper surface and the side surface of the connection conductor layer 30, the smooth film 102 follows the undulations.
The protruding parts 104 are each formed of multiple protrusions 106. Due to the multiple protrusions 106, unevenness is formed on upper surfaces of the protruding parts 104. The number of the protrusions 106 per 1 mm2 is 5 or more and 15 or less. The protruding parts 104 have heights (H1, H2) between the upper surface of the smooth film 102 and top parts of the protruding parts 104. A maximum value of the heights (H1, H2) is 10 times or more and 30 times or less the thickness (T) of the smooth film 102. The heights (H1, H2) are 200 nm or more and 450 nm or less.
As illustrated in
The resin insulating layer (second resin insulating layer) 120, which has a first surface (120a) and a second surface (120b) on the opposite side with respect to the first surface (120a), is formed on the connection conductor layer 30 and the resin insulating layer 20 via the adhesive layer 100. The resin insulating layer 120 is adhered to the connection conductor layer 30 by the adhesive layer 100. The resin insulating layer 120 is in contact with the adhesive layer 100. The second surface (120b) of the resin insulating layer 120 faces the connection conductor layer 30. A material of the resin insulating layer (second resin insulating layer) 120 and a material of the resin insulating layer (first resin insulating layer) 20 are similar. The first surface (120a) of the resin insulating layer 120 is similar to the first surface (20a) of the resin insulating layer 20.
The resin insulating layer 120 has openings (via conductor openings) (121, 122, 123, 124). The openings 121 are first openings 121 exposing the first pads 32. The openings 122 are second openings 122 exposing the second pads 34. The first openings 121 and the openings 123 are formed directly below the first mounting region (A1). The second openings 122 and the openings 124 are formed directly below the second mounting region (A2). The first openings 121 and the second openings 122 extend to the pads (32, 34), which are directly connected to the connection wirings 36. Such openings (the first openings 121, the second openings 122, and the like) may be referred to as connection via conductor openings. The first openings 121 positioned directly below the first electronic component (E1) are first connection via conductor openings, and the second openings 122 positioned directly below the second electronic component (E2) are second connection via conductor openings. The first openings 121, the second openings 122, and the openings (123, 124) are similar to the opening 21 illustrated in
The mounting conductor layer 130 is formed on the first surface (120a) of the resin insulating layer 120. The resin insulating layer 120 supporting the mounting conductor layer 130 is an uppermost resin insulating layer. The mounting conductor layer 130 is in contact with the first surface of the uppermost resin insulating layer. The mounting conductor layer 130 includes the multiple first electrodes 131 and the multiple second electrodes 132. The mounting conductor layer 130 includes the electrodes (133, 134) in addition to the first electrode 131 and the second electrode 132. The first electrode 131 and the electrode 133 are formed in the first mounting region (A1). The first electronic component (E1) is mounted on the printed wiring board 2 via the first electrodes 131 and the electrodes 133. The second electrodes 132 and the electrodes 134 are formed in the second mounting region (A2). The second electronic component (E2) is mounted on the printed wiring board 2 via the second electrodes 132 and the electrodes 134. The mounting conductor layer 130 may further include multiple connection wirings (second connection wirings). In this case, the second connection wirings each have a one-end and an other-end on the opposite side with respect to the one-end. The one-end of each of the second connection wirings is directly connected to one of the first electrodes 131. The other-end of each of the second connection wirings is directly connected to one of the second electrodes 132. The second connection wirings electrically connect the first electrodes 131 and the second electrodes 132. Data is transmitted from the first electronic component (E1) to the second electronic component (E2) via the second connection wirings. The connection wirings in the mounting conductor layer 130 can include the first electrodes 131 and the second electrodes 132.
The mounting conductor layer 130 and the connection conductor layer 30 are similar. Therefore, the mounting conductor layer 130 is formed of a seed layer (130a) and an electrolytic plating layer (130b) on the seed layer (130a). The seed layer (130a) is formed of a first layer (131a) and a second layer (131b) on the first layer (131a). The seed layer (130a) forming the mounting conductor layer 130 and the seed layer (30a) forming the connection conductor layer 30 are similar. The first layer (131a) forming the mounting conductor layer 130 and the first layer (31a) forming the connection conductor layer 30 are similar. The second layer (131b) forming the mounting conductor layer 130 and the second layer (31b) forming the connection conductor layer 30 are similar. The electrolytic plating layer (130b) forming the mounting conductor layer 130 and the electrolytic plating layer (30b) forming the connection conductor layer 30 are similar.
When the mounting conductor layer 130 includes the connection wirings, the connection wirings in the mounting conductor layer 130 and the connection wirings 36 in the connection conductor layer 30 are similar. Therefore, the widths (W1, G1, W2, G2) of the connection wirings in the mounting conductor layer 130 are respectively similar to the widths (W1, G1, W2, G2) of the connection wirings 36 in the connection conductor layer 30. The connection wirings in the mounting conductor layer 130 each have an aspect ratio (thickness/width) of 2.0 or more and 4.0 or less. The widths (D1, D2, D3) of the connection wirings in the mounting conductor layer 130 are respectively similar to the widths (D1, D2, D3) of the connection wirings 36 in the connection conductor layer 30.
In the embodiment, an adhesive layer 150 can be formed on a surface (including upper and side surfaces) of the mounting conductor layer 130. The surface of the mounting conductor layer 130 is formed of a third surface and a fourth surface. Of the surface, the third surface is a portion that is exposed by openings. An example of the openings is bump formation openings. The fourth surface is a portion other than the third surface. The third surface is not covered by the adhesive layer 150, and the fourth surface is covered by the adhesive layer 150. The adhesive layer 150 covering the fourth surface of the mounting conductor layer 130 is similar to the adhesive layer 100 covering the second surface of the connection conductor layer 30. Therefore, the adhesive layer 150 is formed of a smooth film 102, which is substantially smooth, and protruding parts 104 protruding from the smooth film 102 (see
The via conductors (141, 142, 143, 144) are respectively formed in the openings (via conductor openings) (121, 122, 123, 124) that penetrate the resin insulating layer 120. The via conductors 141 formed in the first openings 121 are the first connection via conductors 141. The first connection via conductors 141 connect to the first pads 32 extending from the one-ends of the connection wirings 36. The via conductors 142 formed in the second openings 122 are the second connection via conductors 142. The second connection via conductors 142 connect to the second pads 34 extending from the other-ends of the connection wirings 36. The first connection via conductors 141 and the second connection via conductor 142 electrically connect the connection conductor layer 30 and the mounting conductor layer 130. The first connection via conductors 141 electrically connect the first pads 32 and the first electrodes 131. The second connection via conductors 142 electrically connect the second pads 34 and the second electrodes 132. The first connection via conductors 141 electrically connect the first electrodes 131 and the connection wirings 36. The second connection via conductors 142 electrically connect the second electrodes 132 and the connection wirings 36. The inner wall surfaces (125, 126) of the openings (121, 122) for the connection via conductors (141, 142) are each formed of the exposed surfaces (91b) of the first inorganic particles 91 and the surface (80a) of the resin 80. The exposed surfaces (91b) of the first inorganic particles 91 and the surface (80a) of the resin 80 form a substantially common surface. The inner wall surface of each of the connection via conductor openings is substantially flat. Therefore, when data from the first electrodes 131 to the second electrodes 132 passes through the connection via conductors (141, 142), the data is unlikely to degrade. The connection via conductors of the embodiment are suitable as via conductors for transmitting high-speed data. The printed wiring board 2 of the embodiment can transmit a large amount of data via the connection via conductors.
The connection via conductors are each formed of a seed layer (130a) and an electrolytic plating layer (130b) on the seed layer (130a). The first connection via conductors 141 and the second connection via conductors 142 are examples of the connection via conductors. The seed layer (130a) forming the connection via conductors (141, 142) and the seed layer (130a) forming the mounting conductor layer 130 are common. The first layer (131a) forming the connection via conductors (141, 142) and the first layer (131a) forming the mounting conductor layer 130 are common. The second layer (131b) forming the connection via conductors (141, 142) and the second layer (131b) forming the mounting conductor layer 130 are common. The electrolytic plating layer (130b) forming the connection via conductors (141, 142) and the electrolytic plating layer (130b) forming the mounting conductor layer 130 are common. The seed layer (130a) forming the connection via conductors (141, 142) is formed of a first layer (131a), which is formed on the inner wall surfaces (125, 126) of the connection via conductor openings (121, 122) and on the pads (32, 34) exposed from the connection via conductor openings (121, 122), and a second layer (131b) on the first layer (131a). The first layer (131a) is in contact with the inner wall surfaces (125, 126) and the pads (32, 34). The via conductors (143, 144) are formed in the openings (123, 124) other than the connection via conductor openings (121, 122).
The mounting conductor layer is formed directly on the resin insulating layer (mounting resin insulating layer) that supports the mounting conductor layer. The mounting conductor layer is in contact with the mounting resin insulating layer. The seed layer forming the mounting conductor layer and the seed layer forming the via conductors penetrating the mounting resin insulating layer are common. The two are formed at the same time. The first layer forming the mounting conductor layer and the first layer forming the via conductors penetrating the mounting resin insulating layer are common. The two are formed at the same time. The second layer forming the mounting conductor layer and the second layer forming the via conductors penetrating the mounting resin insulating layer are common. The two are formed at the same time. The first layer and the second layer form the seed layer. The electrolytic plating layer forming the mounting conductor layer and the electrolytic plating layer forming the via conductors penetrating the mounting resin insulating layer are common. The two are formed at the same time. The inner wall surface of each of the via conductor openings penetrating the mounting resin insulating layer and the inner wall surface 23 of the opening 21 illustrated in
The insulating layer 220, which has a first surface (220a) and a second surface (220b) on the opposite side with respect to the first surface (220a), is formed on the mounting conductor layer 130 and on the first surface (120a) of the resin insulating layer 120. In the embodiment, the adhesive layer 150 can be formed on the mounting conductor layer 130. In this case, the insulating layer 220 is formed on the mounting conductor layer 130 via the adhesive layer 150. The adhesive layer 150 formed on the mounting conductor layer 130 and the adhesive layer 100 formed on the connection conductor layer 30 are similar. The insulating layer 220 is adhered to the mounting conductor layer 130 by the adhesive layer 150. The second surface (220b) of the insulating layer 220 faces the mounting conductor layer 130. The insulating layer 220 functions as a solder resist layer. A material of the insulating layer 220 is preferably different from the material of the resin insulating layers (20, 120). The insulating layer 220 is formed, for example, using an epoxy resin or polyimide resin containing a photosensitizer.
The insulating layer 220 has openings (bump openings) (221, 222, 223, 224) that expose the electrodes (131, 132, 133, 134). The openings 221 are first openings (first bump openings) 221 that expose the first electrodes 131. The openings 222 are second openings (second bump openings) 222 that expose the second electrodes 132. The first openings 221 and the openings 223 are formed directly above the first mounting region (A1). The second openings 222 and the openings 224 are formed directly above the second mounting region (A2).
The bumps (241, 242, 243, 244) are formed on the electrodes (131, 132, 133, 134) exposed from the openings (bump openings) (221, 222, 223, 224). The bumps 241 formed on the first electrodes 131 exposed from the first openings (first bump openings) 221 are first bumps 241. The bumps 242 formed on the second electrodes 132 exposed from the second openings (second bump openings) 222 are second bumps 242. The bumps (241, 242, 243, 244) are examples of bumps for mounting electronic components (such as the first electronic component (E1) and the second electronic component (E2)) on the printed wiring board 2. The first bumps 241 and the bumps 243 are positioned in the first mounting region (A1), and the first electronic component (E1) is mounted on the printed wiring board 2 via these bumps (241, 243). The second bumps 242 and the bumps 244 are positioned in the second mounting region (A2), and the second electronic component (E2) is mounted on the printed wiring board 2 via these bumps (242, 244).
The bumps (241, 242, 243, 244) are formed of a portion (first portion) that fills the openings (221, 222, 223, 224) and a second portion (land) on the first portion. The second portion is formed directly on the first portion and on the first surface (220a) of the insulating layer 220 around the openings (221, 222, 223, 224). The first portion and the second portion are integrally formed. The first portion and the second portion are continuously formed. The second portion protrudes from the first surface (220a) of the insulating layer 220. The first bumps 241 electrically connect the first electronic component (E1) and the first electrodes 131. The second bumps 242 electrically connect the second electronic component (E2) and the second electrodes 132. The first electronic component (E1) and the second electronic component (E2) are connected via the first bumps 241, the first connection via conductors 141, the connection wirings 36, the second connection via conductors 142, and the second bumps 242. When data is transmitted from the first electronic component (E1) to the second electronic component (E2), the data is transmitted via a path that includes the connection via conductors and the connection wirings. Since the connection via conductors and the connection wirings include a sputtered seed layer that is formed on a substantially flat surface, the printed wiring board 2 of the embodiment can transmit a large amount of data at a high speed from the first electronic component (E1) to the second electronic component (E2). When data is transmitted, data degradation is unlikely to occur.
The bumps (241, 242, 243, 244) are formed of a seed layer (230a) and an electrolytic plating layer (230b) on the seed layer (230a). The seed layer (230a) is formed of a first layer (231a) and a second layer (231b) on the first layer (231a). The seed layer (230a) forming the bumps (such as the first bumps 241 and the second bumps 242) and the seed layer (30a) forming the connection conductor layer 30 are similar. The first layer (231a) forming the bumps and the first layer (31a) forming the connection conductor layer 30 are similar. The second layer (231b) forming the bumps and the second layer (31b) forming the connection conductor layer 30 are similar. The electrolytic plating layer (230b) forming the bumps and the electrolytic plating layer (30b) forming the connection conductor layer 30 are similar. In a modified example, the bumps (241, 242, 243, 244) may be formed of solder.
A functional layer 260 is formed on tops of the bumps (241, 242, 243, 244). The functional layer 260 is, for example, a plating film of nickel, tin, palladium, gold, or the like.
An example of the base material 5 is a substrate containing a reinforcing material such as glass, silicon, or glass fiber. The base material 5 has a higher rigidity than the printed wiring board 2. Therefore, in the modified example printed wiring board 3, connection reliability between the printed wiring board and the electronic components (such as the first electronic component (E1) and the second electronic component (E2)) can be increased.
As illustrated in
As illustrated in
By irradiating the resin insulating layer 20 with the laser (L), some of the second inorganic particles 92 embedded in the resin 80 form the inner wall surface (23b) after the laser irradiation. The second inorganic particles 92 forming the inner wall surface (23b) after the laser irradiation are each formed of a protruding portion (P) protruding from the resin 80 and a portion (E) embedded in the resin 80. The inner wall surface (23b) after the laser irradiation is treated. For example, the inner wall surface (23b) is treated with plasma of a gas containing tetrafluoromethane. The protruding portions (P) are selectively removed, and the inner wall surface 23 of the embodiment is formed. The first inorganic particles 91 are formed from the second inorganic particles 92. By selectively removing the protruding portions (P), the first inorganic particles 91 having the flat parts (91a) are formed. The flat parts (91a) are flat surfaces. When the second inorganic particles 92 having spherical shapes are cut along a flat surface, the shapes of the first inorganic particles 91 are obtained. The inner wall surface 23 is formed of the flat parts (91a) and the surface (80a) of the resin 80, and the exposed surfaces (91b) of the flat parts (91a) and the surface (80a) of the resin 80 are substantially positioned on the same flat surface. For example, when the seed layer (30a) is formed on the inner wall surface (23b) by sputtering, the protruding portions (P) inhibit growth of a sputtering film (sputtering-deposited film). For example, a continuous seed layer (30a) is not formed on the inner wall surface (23b). Or, the seed layer (30a) is increased in thickness. When the protruding portions (P) exist, it becomes difficult to form fine conductor circuits. In the embodiment, the protruding portions (P) are removed. In the embodiment, the seed layer (30a) formed by sputtering can be reduced in thickness. Even when the seed layer (30a) formed by sputtering is thin, a continuous seed layer (30a) can be obtained. The widths of the connection wirings 36 satisfy target values. In the embodiment, the width (D1), the width (D2) and the width (D3) can be easily controlled. The width (D1), the width (D2), and the width (D3) are formed as intended. The widths of the spaces 37 between adjacent connection wirings 36 satisfy target values. A via conductor formed on the inner wall surface (23b) having the protruding portions (P) is a via conductor of a reference example. When the via conductor of the reference example exists in a path, data transmitted from the first electronic component (E1) to the second electronic component (E2) must pass through the via conductor of the reference example. In this case, it is thought that data may degrade due to influence of the protruding portions (P). In the embodiment, the protruding portions (P) are removed. The embodiment can suppress data degradation.
Forming the openings (via conductor openings) includes forming the inorganic particles 90 (the second inorganic particles 92) having the protruding portions (P). The opening 21 is a representative example of the openings (via conductor openings). The protruding portions (P) protrude from the resin 80 that forms the inner wall surface (23b) of the opening 21. The first inorganic particles 91 are formed by removing the protruding portions (P) of the inorganic particles 90 (the second inorganic particles 92). The inner wall surface 23 of the opening 21 includes the exposed surfaces (91b) of the first inorganic particles 91. The exposed surfaces (91b) of the first inorganic particles 91 are formed by removing the protruding portions (P).
Obtaining the shapes of the first inorganic particles 91 by cutting the second inorganic particles 92 having spherical shapes along a flat surface includes removing the protruding portions (P) of the inorganic particles 90. The actual inner wall surface 23 of the opening 21 is a substantially curved surface. Since the flat parts (91a) are formed by removing the protruding portions (P), the exposed surfaces (91b) of the flat parts (91a) each include a curved surface. That is, forming a common surface with the flat parts (91a) and the resin 80 includes forming the inner wall surface 23 formed with a substantially curved surface.
No unevenness is formed on the inner wall surface 23. The inner wall surface 23 is formed smooth. By controlling the conditions for treating the inner wall surface (23b) after the laser irradiation, a size of unevenness is controlled.
The inside of the opening 21 is cleaned. By cleaning the inside of the opening 21, resin residues generated when the opening 21 is formed are removed. The cleaning of the inside of the opening 21 is performed using plasma. That is, the cleaning is performed with a dry process. The cleaning includes a desmear treatment.
When the inside of the opening 21 is cleaned, the first surface (20a) of the resin insulating layer 20 is covered by the protective film 50. The first surface (20a) is not affected by the plasma. The first surface (20a) is formed only of the resin 80. No inorganic particles 90 are exposed from the first surface (20a). The first surface (20a) does not include surfaces of the inorganic particles 90. The first surface (20a) has no unevenness. The first surface (20a) is formed smooth.
When treating the inner wall surface (23b) after the laser irradiation includes cleaning the inside of the opening 21, in the embodiment, cleaning the inside of the opening 21 can be omitted.
As illustrated in
As illustrated in
The first layer (31a) is formed of a copper alloy. The first layer (31a) of the seed layer (30a) is formed of an alloy containing copper, aluminum and silicon. Aluminum has high ductility and high malleability. Therefore, adhesion between resin insulating layer 20 and the first layer (31a) is high. It is thought that, even when the resin insulating layer 20 expands and contracts due to heat cycles, the seed layer (30a) containing aluminum can follow the expansion and contraction. Even when the first surface (20a) of the resin insulating layer 20 is smooth, the seed layer (30a) is unlikely to peel off from the resin insulating layer 20. It is thought that aluminum is easily oxidized. It is thought that, when the first inorganic particles 91 are inorganic particles 90 containing oxygen (oxygen elements), the first layer (31a) formed on the inner wall surfaces (23, 24) adheres to the first inorganic particles 91 via the oxygen in the inorganic particles 90 forming the inner wall surfaces (23, 24). The first layer (31a) and each of the inner wall surfaces (23, 24) are strongly bonded to each other. In the embodiment, adhesion between each of the inner wall surfaces (23, 24) and the first layer (31a) can be increased. The seed layer (30a) is unlikely to peel off from the inner wall surfaces (23, 24). The inorganic particles 90 forming the inner wall surfaces (23, 24) preferably contain oxygen elements.
The thickness of the seed layer (30a) is 0.02 μm or more and 1.0 μm or less. A more preferable example is 0.03 μm or more and 0.5 μm or less. An even more preferable example is 0.05 μm or more and 0.3 μm or less. The first surface (20a) has an arithmetic mean roughness (Ra) of 0.02 μm or more and 0.06 μm or less. When the thickness of the seed layer (30a) is less than 0.02 μm, it is difficult to uniformly form the seed layer (30a) over the entire first surface (20a) of the first resin insulating layer 20. When the thickness is larger than 1.0 μm, it is difficult to control the width of the electrolytic plating layer (30b) when the seed layer (30a) is removed. The thickness of the first layer (31a) is 0.01 μm or more and 0.5 μm or less. A more preferable example is 0.02 am or more and 0.3 μm or less. An even more preferable example is 0.03 μm or more and 0.1 μm or less. When the thickness of the first layer (31a) is less than 0.01 μm, the adhesion between the first layer (31a) and the resin insulating layer 20 decreases. When the thickness of the first layer (31a) is larger than 0.5 μm, resistance of the connection wirings 36 increases. The thickness of the second layer (31b) is 0.01 μm or more and 0.9 μm or less. A more preferable example is 0.02 μm or more and 0.3 μm or less. An even more preferable example is 0.03 μm or more and 0.2 μm or less. When the thickness of the second layer (31b) is less than 0.01 μm, the resistance of the connection wirings 36 increases. When the thickness of the second layer (31b) is larger than 0.9 μm, it is difficult to control the width of the electrolytic plating layer (30b) when the seed layer (30a) is removed. The seed layer (30a) is formed along a surface shape of the first surface (20a). The seed layer (30a) that forms the connection wirings 36 in the connection conductor layer 30 does not extend to an inner side of the resin insulating layer 20. When the seed layer (30a) is removed, in the embodiment, an etching amount can be reduced. The connection wirings 36 are unlikely to be excessively removed. The widths of the connection wirings 36 have values close to design values.
A plating resist is formed on the seed layer (30a). The plating resist has openings for forming the via conductors (41, 42), the connection wirings 36, and the pads (32, 34) extending from the connection wirings 36.
The electrolytic plating layer (30b) is formed on the seed layer (30a) exposed from the plating resist. The electrolytic plating layer (30b) fills the openings of the plating resist. The electrolytic plating layer (30b) fills the openings (21, 22). A portion of the electrolytic plating layer (30b) protrudes above an upper surface of the plating resist. In this case, the electrolytic plating layer (30b) partially covers the upper surface of the plating resist. Or, the electrolytic plating layer (30b) completely covers the upper surface of the plating resist.
The electrolytic plating layer (30b) is polished. By the polishing, the electrolytic plating layer (30b) is reduced in thickness. A combined thickness of the electrolytic plating layer (30b) and the seed layer (30a) reaches a predetermined value. The plating resist is also polished along with the electrolytic plating layer (30b). An example of a polishing method is CMP. After the polishing, the upper surface of the electrolytic plating layer (30b) has an arithmetic mean roughness (Ra) of 0.3 μm or less.
After the polishing of the electrolytic plating layer (30b), the plating resist is removed. The seed layer (30a) exposed from the electrolytic plating layer (30b) is removed. As illustrated in
An etching rate (R2) of the second layer (31b) is higher than an etching rate (R1) of the first layer (31a). The etching rate (R1) of the first layer (31a) is higher than an etching rate (RE) of the electrolytic plating layer (30b). An etching rate (RS) of the seed layer (30a) is higher than the etching rate (RE) of the electrolytic plating layer (30b). For example, a ratio (R2/RE) of the etching rate (R2) of the second layer (31b) to the etching rate (RE) of the electrolytic plating layer (30b) is 1.2 or more and 1.5 or less. A ratio (R1/RE) of the etching rate (R1) of the first layer (31a) to the etching rate (RE) of the electrolytic plating layer (30b) is 1.1 or more and 1.4 or less. A ratio (R2/R1) of the etching rate (R2) of the second layer (31b) to the etching rate (R1) of the first layer (31a) is 1.1 or more and 1.5 or less. Therefore, as illustrated in
The layers (31a, 31b, 30b) forming the connection conductor layer 30 have different etching rates. It is speculated that structural ratios ((amorphous structure)/(crystalline structure)) of the layers (31a, 31b, 30b) are related to the differences in the etching rates. This is because an amorphous structure is likely to have lattice defects. Therefore, a layer with a large structural ratio is likely to have a large etching rate. Examples of devices for determining structural ratios include transmission electron microscopy and X-ray diffraction. For example, a structural ratio is calculated using volumes of the two. Or, a structural ratio is calculated using areas of the two included in a cross section. When areas are used, an area ratio ((area of amorphous structure)/(area of crystalline structure)) is used as a representative value of the structural ratio.
It is thought that the higher the structural ratio, the higher the etching rate. Therefore, the structural ratio of the second layer (31b) is expected to be larger than that of the first layer (31a). The structural ratio of the first layer (31a) is expected to be larger than that of the electrolytic plating layer (30b). It is thought that factors such as amount of heat, composition, thickness, time, formation method, density, and crystallinity affect the structural ratio. The amount of heat applied to the first layer (31a) is larger than the amount of heat applied to the second layer (31b). The thickness of the first layer (31a) and the thickness of the second layer (31b) are substantially equal. The thickness of the electrolytic plating layer (30b) is significantly larger than the thickness of the first layer (31a). The second layer (31b) and the electrolytic plating layer (30b) are formed of copper, and the first layer (31a) is formed of a copper alloy. The first layer (31a) is formed on a resin. The second layer (31b) is formed on the first layer (31a), which is formed of a copper alloy. The electrolytic plating layer (30b) is formed on the second layer (31b), which is formed of copper. Among the first layer (31a), the second layer (31b), and the electrolytic plating layer (30b), the first layer (31a) is formed first. The first layer (31a) and the second layer (31b) are formed by sputtering. The electrolytic plating layer (30b) is formed by electrolytic plating. There are commonalities and differences among the layers (31a, 31b, 30b) that form the connection conductor layer 30. It is thought that the etching rates of the layers (31a, 31b, 30b) can be controlled by controlling factors affecting the structural ratios.
Since the flat parts (91a) of the first inorganic particles 91 form the inner wall surfaces (23, 24), in the embodiment, the thickness of the first layer (31a) can be reduced. The thickness of the first layer (31a) is sufficiently smaller than the thickness of the electrolytic plating layer (30b). Therefore, orientation of the particles forming the first layer (31a) tends to be lower than orientation of the particles forming the electrolytic plating layer (30b). Or, a density of the first layer (31a) tends to be smaller than a density of the electrolytic plating layer (30b). Or, crystallinity of the first layer (31a) tends to be lower than crystallinity of the electrolytic plating layer (30b). Since the flat parts (91a) of the first inorganic particles 91 form the inner wall surfaces (23, 24), in the embodiment, the thickness of the second layer (31b) can be reduced. The thickness of the second layer (31b) is sufficiently smaller than the thickness of the electrolytic plating layer (30b). Therefore, orientation of the particles forming the second layer (31b) tends to be lower than the orientation of the particles forming the electrolytic plating layer (30b). Or, a density of the second layer (31b) tends to be smaller than the density of the electrolytic plating layer (30b). Or, crystallinity of the second layer (31b) tends to be lower than the crystallinity of the electrolytic plating layer (30b). Therefore, the etching rates of the first layer (31a) and the second layer (31b) are higher than the etching rate of the electrolytic plating layer (30b). When the seed layer (30a) exposed from the electrolytic plating layer (30b) is removed, the width (D1) of the electrolytic plating layer (30b) is larger than the width (D2) of the first layer (31a). The width (D1) of the electrolytic plating layer (30b) is larger than the width (D3) of the second layer (31b). The etching rate of the electrolytic plating layer (30b) is smaller than the etching rate of the seed layer (30a). Therefore, an amount of a dissolution component in an etching solution consumed for dissolving the electrolytic plating layer (30b) is small. According to the embodiment, a dissolution component sufficiently reaches the seed layer (30a). The seed layer (30a) efficiently dissolves. In the embodiment, the connection wirings 36 each having a width of a target value can be formed. The first layer (31a) is covered by the second layer (31b). A dissolution component is consumed for dissolving the second layer (31b). Therefore, a dissolution amount of the first layer (31a) can be smaller than a dissolution amount of the second layer (31b). When the seed layer (30a) exposed from the electrolytic plating layer (30b) is removed, the width (D2) of the first layer (31a) is larger than the width (D3) of the second layer (31b).
The first layer (31a) forming the connection wirings 36 is formed on an insulating layer, and the second layer (31b) is formed on a metal layer. The first layer (31a) is formed of a copper alloy, and the second layer (31b) is formed of copper. The first layer (31a) forming the connection wirings 36 is formed at the same time as the first layer (31a) on the inner wall surface 23 illustrated in
As illustrated in
The resin insulating layer (second resin insulating layer) 120, the mounting conductor layer 130, and the via conductors (141, 142, 143, 144) are formed on the connection conductor layer 30 and the resin insulating layer 20. The via conductors include connection via conductors. Examples of the connection via conductors are the first connection via conductor 141 and the second connection via conductor 142. The resin insulating layer 120 and the resin insulating layer 20 are formed using similar methods. The mounting conductor layer 130 and the connection conductor layer 30 are formed using similar methods. The via conductors (141, 142, 143, 144) and the via conductors (41, 42) are formed using similar methods. When the via conductor openings (121, 122, 123, 124) are formed in the resin insulating layer 120 using the laser (L), the laser (L) removes the adhesive layer 100 covering the connection conductor layer 30. Or, the adhesive layer 100 is not completely removed by the laser (L). In this case, the adhesive layer 100 at bottoms of the via conductor openings (121, 122, 123, 124) is removed by cleaning the insides of the via conductor openings (121, 122, 123, 124). The via conductor openings (121, 122, 123, 124) expose the connection conductor layer 30. The via conductor openings include connection via conductor openings. Examples of connection via conductor openings are the first openings (first connection via conductor openings) 121 and the second openings (second connection via conductor openings) 122.
In the embodiment, the first layer forming the connection via conductors can be reduced in thickness. In the embodiment, the second layer forming the connection via conductors can be reduced in thickness. The first layer and the second layer form the seed layer. In the embodiment, a volume of each of the connection via conductor openings after the formation of the seed layer can be increased. The connection via conductor openings after the formation of the seed layer can be referred to as post-seed layer formation openings. By forming the electrolytic plating layer in the post-seed layer formation openings, the connection via conductors formed of the seed layer and the electrolytic plating layer are formed. Even when the connection via conductor openings have small diameters, an electrolytic plating solution can easily enter the connection via conductor openings after the formation of the seed layer. The electrolytic plating layer forming the connection via conductors is unlikely to contain voids. Low resistance connection via conductors are formed. Even when a path includes connection via conductors, the printed wiring board 2 of the embodiment can transmit high-speed data. An example of post-seed layer formation openings (210, 211) is illustrated in
The adhesive layer 150 is formed on the upper and side surfaces of the mounting conductor layer 130. The adhesive layer 150 and the adhesive layer 100 are similar. The insulating layer 220 is formed on the mounting conductor layer 130 and the resin insulating layer 120. The insulating layer 220 has the openings (221, 222, 223, 224) that expose the electrodes (such as the first electrodes 131 and the second electrodes 132). The bumps (such as the first bumps 241 and the second bumps 242) are formed on the electrodes (131, 132, 133, 134) exposed by the openings (221, 222, 223, 224). The functional layer 260 is formed on the bumps (241, 242, 243, 244). The printed wiring board 3 of the modified example is obtained.
The support 4 is removed. For example, by heating or ultraviolet irradiation, the release layer 7 of the support 4 softens or becomes brittle. The first metal layer 6 and the second metal layer 8 are separated from each other. After that, the second metal layer 8 is removed by etching. The lower surface (2b) of the printed wiring board 2 is exposed. The printed wiring board 2 of the embodiment is obtained.
By making the width (D3) of the second layer (31b) smaller than the width (D1) of the electrolytic plating layer (30b) and the width (D2) of the first layer (31a), sidewalls of each of the connection wirings 36 each have a recess 38 (
A surface of the connection conductor layer 30 facing the first surface (20a) is formed along a surface shape of the first surface (20a). The seed layer (30a) forming the connection wirings 36 in the connection conductor layer 30 does not extend to an inner side of the first surface (20a) of the first resin insulating layer 20. A thin seed layer (30a) is formed. Variation in the thickness of the seed layer (30a) is small. When the seed layer (30a) is removed, the etching amount is small. The connection wirings 36 are unlikely to be excessively removed. The widths of the connection wirings 36 are substantially close to design values.
The connection wirings 36 have small widths. The connection wirings 36 have small thicknesses. The spaces 37 between the connection wirings 36 have small widths. Therefore, the resin insulating layer 120 formed between adjacent connection wirings 36 is likely to peel off from the connection wirings 36. The connection wirings 36 are densely formed. Therefore, a crack along a side surface of the connection wirings 36 is likely to occur in the first resin insulating layer 20, which supports the connection wirings 36. However, in the embodiment, since the connection wirings 36 have the recesses 38, the second resin insulating layer 120 filling the spaces between the connection wirings 36 is unlikely to peel off from the connection wirings 36. The second resin insulating layer 120 covering the connection wirings 36 is unlikely to peel off from the connection wirings 36. A crack along a side surface of the connection wirings 36 is unlikely to occur in the first resin insulating layer 20, which supports the connection wirings 36. Since the connection wirings 36 have the recesses 38, in the embodiment, the connection wirings 36 can be formed at a high density.
For example, by making the width (D2) smaller than the width (D1) and the width (D3), the sidewalls of the connection wirings can each have a recess. In this case, a contact area between the first layer (31a) and the first surface (20a) is small. Therefore, the connection wirings 36 are likely to peel off from the first surface (20a). However, in the embodiment, the width (D1) and the width (D2) are greater than the width (D3). Therefore, in the embodiment, the connection wirings 36 are unlikely to peel off from the first surface (20a).
Among the multiple connection wirings 36, a connection wiring formed at one end is a first connection wiring (36F). The first connection wiring (36F) is illustrated in
In the printed wiring board 2 of the embodiment, the inner wall surface of each of the via conductor openings is formed by the flat parts (91a) of the first inorganic particles 91 and the resin 80. The flat parts (91a) and the surface (80a) of the resin 80 that forms the inner wall surface form a substantially common surface. The inner wall surface is formed smooth. Therefore, the seed layer (30a) having a uniform thickness is formed on the inner wall surface of each of the openings. The seed layer (30a) is formed thin. When the seed layer (30a) is removed, an etching amount is small. Therefore, an etching amount of the electrolytic plating layer (30b) is small. Conductor circuits in the connection conductor layer 30 and the mounting conductor layer 130 have widths as designed. A high quality printed wiring board 2 is provided.
Data is transmitted from the first electronic component (E1) to the second electronic component (E2) via the connection wirings 36. When data is transmitted, low loss is preferred. When the connection conductor layer is an inner-layer conductor layer, a path for data transmission between the first electronic component (E1) and the second electronic component (E2) includes via conductors connected to the connection wirings. The via conductors forming the path are connection via conductors. Even when the path includes the via conductors (connection via conductors), the inner wall surface of each of the openings for the connection via conductors of the printed wiring board 2 of the embodiment is formed of the exposed surfaces (91b) of the first inorganic particles 91 and the surface (80a) of the resin 80. The inner wall surface is substantially flat. According to the embodiment, when data passes through the via conductors, the printed wiring board 2 of the embodiment can suppress losses. The inner-layer conductor layer is sandwiched between adjacent resin insulating layers. When there are multiple connection conductor layers (connection inner conductor layers) formed of inner-layer conductor layers, the number of the connection inner conductor layers (CI) is preferably three or more. The number of the connection inner conductor layers (CI) is preferably seven or less. Further, the number of the connection inner conductor layers (CI) is preferably five or less. An example of a printed wiring board 200 having three connection inner conductor layers (CI) is illustrated in
The connection inner conductor layers are preferably each sandwiched between resin insulating layers containing the first inorganic particles 91 and the second inorganic particles 92. The resin insulating layers sandwiching a connection inner conductor layer both have via conductor openings. And, an inner wall surface of each of the via conductor openings is formed of the exposed surfaces (91b) of the first inorganic particles 91 and the surface (80a) of the resin 80. The connection wirings forming the connection inner conductor layers have widths close to design values. In the embodiment, high-density connection wiring groups can be formed.
Since the inner wall surfaces of the via conductor openings are each formed of the exposed surfaces (91b) of the first inorganic particles 91 and the surface (80a) of the resin 80, inner wall surfaces of the via conductors have substantially the same shape. Even when there are multiple paths that include the connection via conductors, in the embodiment, a difference in transmission speed between the paths can be reduced.
In the printed wiring board 2 of the embodiment, the first surface (20a) of the resin insulating layer 20 is formed of the resin 80. No inorganic particles 90 are exposed on the first surface (20a). No unevenness is formed on the first surface (20a). An increase in standard deviation of a relative permittivity in a portion near the first surface (20a) of the resin insulating layer 20 is suppressed. The relative permittivity of the first surface (20a) of the resin insulating layer 20 does not significantly vary depending on a location. Even when the multiple connection wirings 36 are in contact with the first surface (20a) of the resin insulating layer 20, in the embodiment, a difference in electrical signal propagation speed between the connection wirings 36 can be reduced. Therefore, in the printed wiring board 2 of the embodiment, noise is suppressed. Even when a logic IC is mounted on the printed wiring board 2 of the embodiment, data transmitted via the connection wirings 36 reaches the logic IC substantially simultaneously. In the embodiment, malfunction of the logic IC can be suppressed. Even when the connection wirings 36 each have a length of 5 mm or more, in the embodiment, the difference in propagation speed can be reduced. Even when the connection wirings 36 have lengths of 10 mm or more and 20 mm or less, in the embodiment, malfunction of the logic IC can be suppressed. The first surface (120a) of the resin insulating layer 120 is also similar to the first surface (20a) of the resin insulating layer 20. Therefore, the connection wirings in the mounting conductor layer 130 also have similar effects to the connection wirings 36 in the connection conductor layer 30. A high quality printed wiring board 2 is provided.
The printed wiring board 2 of the embodiment has the adhesive layer 100 between the connection conductor layer 30 and the resin insulating layer 120. The adhesive layer 100 adheres the connection conductor layer 30 and the resin insulating layer 120. Therefore, even when the upper and side surfaces of the connection wirings 36 are smooth, the resin insulating layer 120 is unlikely to peel off from the connection wirings 36. Preferably, the upper and side surfaces of the connection wirings 36 are not roughened. The adhesive layer 100 is formed of the smooth film 102, which is substantially smooth, and the protruding parts 104 protruding from the smooth film 102. The adhesive layer 100 has unevenness formed by the protruding parts 104 and the smooth film 102. The adhesive layer 100 has unevenness formed by the multiple protrusions 106. Therefore, the connection conductor layer 30 and the resin insulating layer 120 are sufficiently adhered to each other via the adhesive layer 100. A high quality printed wiring board 2 is provided. For example, even when each side of the printed wiring board 2 has a length of 50 mm or more, the resin insulating layer 120 is unlikely to peel off from the connection conductor layer 30. Even when each side of the printed wiring board 2 has a length of 100 mm or more, a crack caused by the adhesive layer 100 is unlikely to occur in the resin insulating layer 120. Even when the connection conductor layer 30 includes a conductor circuit having a width of 5 μm or less, the resin insulating layer 120 is unlikely to peel off from the connection conductor layer 30. Even when the connection conductor layer 30 includes a conductor circuit having a width of 3 μm or less, a crack caused by the adhesive layer 100 is unlikely to occur in the resin insulating layer 120. The adhesive layer 150 formed between the mounting conductor layer 130 and the insulating layer 220 also has similar effects to the adhesive layer 100. A high quality printed wiring board 2 is provided.
When the first layer contains silicon as the specific metal and the inorganic particles are glass particles, the first layer and the first inorganic particles on the inner wall surface contain silicon. It is thought that the two are strongly bonded to each other via silicon. The seed layer is unlikely to peel off from the inner wall surface.
When the first layer contains aluminum and the inorganic particles contain oxygen, it is thought that the first layer and the first inorganic particles (inorganic particles containing oxygen such as glass particles) are strongly bonded. When the first layer contains aluminum and the inorganic particles contain oxygen, the first layer does not need to contain the specific metal. In this case, the first layer is formed of copper, aluminum, and impurities.
In a first alternative example of the embodiment, the specific metal contained in the alloy forming the first layer is at least one of nickel, zinc, gallium, silicon, and magnesium.
In a second alternative example of the embodiment, the alloy forming the first layer does not contain carbon.
In a third alternative example of the embodiment, the alloy forming the first layer does not contain oxygen.
In the present specification, the term “flat surface” is used with respect to the shape of the inner wall surface, the shapes of the flat parts (91a), and the shapes of the first inorganic particles 91. The meaning of the “flat surface” used with respect to these is illustrated in
Japanese Patent Application Laid-Open Publication No. 2000-114719 describes that adhesion between a conductor circuit and an interlayer resin insulating layer formed on the conductor circuit can be ensured by a needle-like alloy formed of Cu—Ni—P on the conductor circuit. A width of the conductor circuit is small. Or, when a thickness of the conductor circuit is small, it is thought that it is difficult to ensure adhesion between the conductor circuit and the interlayer resin insulating layer formed on the conductor circuit using only the roughened layer. When a high-speed signal is transmitted, it is preferable that the conductor circuit has a small surface roughness. The surface roughness of the conductor circuit is small. Or, when the surface of the conductor circuit is smooth, it is thought that it is difficult to ensure adhesion between the conductor circuit and the interlayer resin insulating layer formed on the conductor circuit.
A printed wiring board according to an embodiment of the present invention includes: a mounting conductor layer that has at least one first electrode for mounting a first electronic component and at least one second electrode for mounting a second electronic component; a connection conductor layer that is positioned below the mounting conductor layer and has at least one connection wiring electrically connecting the at least one first electrode and the at least one second electrode; a second resin insulating layer that is formed between the mounting conductor layer and the connection conductor layer and has multiple openings including at least one first opening and at least one second opening; a first resin insulating layer that is positioned below the connection conductor layer and supports the connection conductor layer; at least one first connection via conductor that is formed in the at least one first opening and electrically connects the at least one first electrode and the at least one connection wiring; and at least one second connection via conductor that is formed in the at least one second opening and electrically connects the at least one second electrode and the at least one connection wiring. The connection conductor layer is formed of a seed layer and an electrolytic plating layer on the seed layer, the seed layer consisting of a first layer formed on the first resin insulating layer and a second layer on the first layer. In a cross section of the at least one connection wiring, a width of the first layer is larger than a width of the second layer, and a width of the electrolytic plating layer is larger than the width of the first layer.
In the printed wiring board according to an embodiment of the present invention, in the cross section of the connection wiring, the width of the second layer is smaller than the width of the first layer and the width of the electrolytic plating layer. The sidewalls of the connection wiring are not formed straight. The sidewalls each have a recess. A stress due to heat cycles is unlikely to propagate to the first resin insulating layer along the sidewalls of the connection wiring. It is thought that the stress is dispersed by the recess portion. A crack along an extension line of an interface between a sidewall of the connection wiring and the second resin insulating layer is unlikely to occur in the first resin insulating layer. Since the sidewalls of the connection wiring have the recesses, a contact area between the sidewalls of the connection wiring and the second resin insulating layer is large. The second resin insulating layer is unlikely to peel off from the sidewalls of the connection wiring. The embodiment can provide a high quality printed wiring board.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-102916 | Jun 2023 | JP | national |
