Patent Application
20220359208
Embodiments of the present disclosure generally relate to semiconductor devices, and more specifically, to nanosheet field-effect transistor device structures.
Transistors are circuit components or elements that are often formed on semiconductor devices. Many transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, depending on the circuit design. Integrated circuits incorporate planar field-effect transistors (FETs) in which current flows through a semiconducting channel between a source and a drain, in response to a voltage applied to a control gate. As device dimensions have shrunk, new device geometries and structures and materials have experienced difficulty maintaining switching speeds without incurring failures.
Several new technologies emerged that have allowed chip designers to continue shrinking gate lengths. One particularly far-reaching technology change entailed re-designing the structure of the FET from a planar device to a three-dimensional device in which the semiconducting channel was replaced by a fin that extends out from the plane of the substrate. In such a device, commonly referred to as a FinFET, the control gate wraps around three sides of the fin so as to influence current flow from three surfaces instead of one. The improved control achieved with a 3-D design results in faster switching performance and reduced current leakage.
The FinFET concept was extended by development of a gate all-around FET (GAA FET), in which the gate fully wraps around the channel for maximum control of the current flow therein. In the GAA FET, the channel can take the form of a cylindrical nanowire that is isolated from the substrate. Existing GAA FETs are oriented horizontally, such that the nanowire extends in a direction that is parallel to the surface of the semiconductor substrate.
The FinFET concept was further extended by development of a nanosheet FET device, which is similar to the cylindrical nanowire concept except the device channel comprises one or more nanosheet layers in a stacked configuration where each nanosheet layer has a width that is substantially greater than a thickness of the nanosheet layer. A common gate structure is formed above and below each nanosheet layer and the increased width, as compared to a nanowire structure, facilitates an increase in drive current for a given footprint area. However, as 3-D devices continue to shrink in size, contact resistance of source/drain regions of nanosheet device structures may be too high due to limited contact surface area between source/drain regions and corresponding metal contacts.
Accordingly, the inventors have provided herein embodiments of nanosheet FET devices with reduced source/drain contact resistance and methods of forming such devices.
Methods of forming a nanosheet field effect transistor (FET) device with reduced source/drain contact resistance are provided herein. In some embodiments, a method of forming an FET device includes: etching a nanosheet stack of the nanosheet FET device to form a plurality of first source/drain regions and a plurality of second source/drain regions, the nanosheet stack comprising alternating layers of a plurality of nanosheet channel layers and a plurality of sacrificial nanosheet layers; depositing a silicide layer in the plurality of first source/drain regions at sidewalls of the plurality of nanosheet channel layers via a selective silicidation process to control a channel length of the plurality of nanosheet channel layers between adjacent first source/drain regions; and performing a metal fill process to fill the plurality of first source/drain regions, wherein the metal fill extends from a lowermost nanosheet channel layer of the plurality of nanosheet channel layers to above an uppermost nanosheet channel layer of the plurality of nanosheet channel layers to facilitate the reduced source/drain contact resistance.
In some embodiments, a method of forming a nanosheet field effect transistor (FET) device with reduced source/drain contact resistance, includes: forming a nanosheet stack on a substrate, the nanosheet stack comprising alternating layers of nanosheet channel layers and sacrificial nanosheet layers; etching the nanosheet stack of the nanosheet FET device to form a plurality of first source/drain regions and a plurality of second source/drain regions; applying a hard mask on the plurality of second source/drain regions; depositing a silicide layer in the plurality of first source/drain regions at sidewalls of the nanosheet channel layers via a selective silicidation process to control a channel length of the nanosheet channel layers between the first source/drain regions; performing a metal fill process to fill the plurality of first source/drain regions, wherein the metal fill extends from a lowermost nanosheet channel layer to above an uppermost nanosheet channel layer to facilitate the reduced source/drain contact resistance; applying a hard mask over the metal fill in the plurality of first source/drain regions; depositing a silicide layer in the plurality of second source/drain regions at sidewalls of the nanosheet channel layers exposed to the plurality of second source/drain regions via a selective silicidation process to control a length of the nanosheet channel layers between adjacent second source/drain regions; and performing a second metal fill process to fill the plurality of second source/drain regions, wherein the second metal fill extends from the lowermost nanosheet channel layer to above the uppermost nanosheet channel layer to facilitate the reduced source/drain contact resistance.
In some embodiments, a nanosheet field effect transistor (FET) device includes: a nanosheet stack comprising a plurality of nanosheet channel layers; and a source/drain region in contact with end portions of the plurality of nanosheet channel layers, wherein the source/drain region is filled with a metal fill extending below an uppermost one of the plurality of nanosheet channel layers and a silicide layer disposed between the metal fill and sidewalls of the plurality of nanosheet channel layers.
Other and further embodiments of the present disclosure are described below.
Embodiments of the present disclosure, briefly summarized above and discussed in greater detail below, can be understood by reference to the illustrative embodiments of the disclosure depicted in the appended drawings. However, the appended drawings illustrate only typical embodiments of the disclosure and are therefore not to be considered limiting of scope, for the disclosure may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
Embodiments of nanosheet FET devices with reduced source/drain contact resistance and methods of forming such devices are provided herein. The methods provided herein increase a contact area between source/drain regions of the nanosheet FET devices and respective metal contacts to advantageously lower contact resistance therebetween, improving device performance. The methods provided herein also advantageously facilitate tuning a channel length via controlled deposition techniques for optimizing device performance.
At 104, the method 100 optionally includes applying a hard mask (e.g., hard mask 238) on the plurality of second source/drain regions. In some embodiments, the hard mask is deposited on the plurality of second source/drain regions prior to any deposition or fill processes conducted in the plurality of first source/drain regions, such as depositing a silicide layer in the plurality of first source/drain regions. In some embodiments, the method 100 includes forming inner spacers (e.g., inner spacers 226) in the plurality of first source/drain regions adjacent the plurality of nanosheet channel layers. In some embodiments, the spacers are formed of a dielectric material, for example, silicon nitride (SiN) or any suitable dielectric material.
For example,
The device 200 generally comprises a plurality of nanosheet channel layers 206 alternating with a plurality of sacrificial nanosheet layers 212 deposited or disposed on a substrate 218 (e.g., in a stacked configuration, or stacked layers). In some embodiments, the plurality of nanosheet channel layers 206 have a thickness of about 5 to about 15 nanometers per layer. In some embodiments, the plurality of sacrificial nanosheet layers 212 have a thickness of about 5 to about 15 nanometers per layer. In some embodiments, the substrate 218 may be a semiconductor substrate that is formed of silicon (Si), silicon germanium (SiGe), or any other suitable semiconductor substrate material. In some embodiments, the plurality of nanosheet channel layers 206 include exactly three channel layers that are stacked, a first channel layer 220, a second channel layer 222, and a third channel layer 224, separated by layers of the plurality of sacrificial nanosheet layers 212. However, the device 200 may include more or less than three nanosheet channel layers. In some embodiments, the plurality of nanosheet channel layers 206 and the plurality of sacrificial nanosheet layers 212 are sequentially grown in an alternating manner via an epitaxial growth process.
In some embodiments, the plurality of nanosheet channel layers 206 consist essentially of silicon (Si), and the plurality of sacrificial nanosheet layers 212 consist essentially of silicon germanium (SiGe) with a desired Ge concentration. In some embodiments, the plurality of nanosheet channel layers 206 consist essentially of silicon germanium (SiGe) with a desired Ge concentration, and the plurality of sacrificial nanosheet layers 212 consist essentially of silicon (Si). In some embodiments, the desired Ge concentration is about 15 to about 40 percent by volume. In some embodiments, the plurality of nanosheet channel layers 206 and the plurality of sacrificial nanosheet layers 212 comprise single crystal semiconductor materials, such as single crystal silicon. In some embodiments, the plurality of sacrificial nanosheet layers 212 may be subsequently etched away selective to the material of the plurality of nanosheet channel layers 206 to release the plurality of nanosheet channel layers 206 for subsequent metal fill. The plurality of first source/drain regions 202 may include inner spacers 226 adjacent the plurality of sacrificial nanosheet layers 212
Referring back to
In some embodiments, prior to depositing the silicide layer in the plurality of first source/drain regions, as depicted in
In some embodiments, the plurality of nanosheet channel layers 206 may be isolated from gate electrodes 348 disposed above the plurality of nanosheet channel layers 206 via respective upper spacers 320. In some embodiments, the upper spacers 320 are formed of the same material as the inner spacers 226. In some embodiments, a conformal layer of dielectric material may form both the inner spacers 226 and the upper spacers 320.
In some embodiments, epitaxial material 306 is grown from and extends from the sidewalls 350 of the plurality of nanosheet channel layers 206, for example, the first channel layer 220, the second channel layer 222, and the third channel layer 224. The epitaxial material 306 may also be grown from a lower surface 338 of the trench 304. In some embodiments, the epitaxial material 306 is grown from the lower surface 338 to a location vertically below an uppermost one of the plurality of nanosheet channel layers 206. In some embodiments, the epitaxial material 306 is grown from the lower surface 338 to a location vertically below a lowermost one of the plurality of nanosheet channel layers 206. In some embodiments, the epitaxial material 306 grown from the sidewalls 350 of the plurality of nanosheet channel layers 206 form bulbous shapes. In some embodiments, the epitaxial material 306 adjacent one of the plurality of nanosheet channel layers 206 does not merge with the epitaxial material 306 extending from any of the remaining channels of the plurality of nanosheet channel layers 206. In some embodiments, the epitaxial material 306 may comprise epitaxial silicon (Si) or silicon germanium (SiGe) doped with a suitable dopant for form nMOS or pMOS areas.
In some embodiments, a silicide layer 322 is disposed on the epitaxial material 306 and conforms with the epitaxial material 306. A metal fill 310 is disposed in the remainder of the trench 304 not occupied by one or more of the epitaxial material 306 and the silicide layer 322. A contact interface 380 between the metal fill 310 and the epitaxial material 306 or the silicide layer 322 is larger than conventional interfaces, advantageously resulting in lower contact resistance therebetween.
In some embodiments, gate spacers 312 may be disposed about the metal fill 310 in the gate regions 242. The gate spacers 312 may be made of a dielectric material. In some embodiments, second gate spacers 314 are disposed between the gate spacers 312 and the gate electrodes 348 to aid in modulating the conductance of the device 200. In some embodiments, the gate spacers 312 are made of a different material than the second gate spacers 314. In some embodiments, the gate spacers 312 are made of a low-K material and the second gate spacers 314 are made of a higher-K material. In some embodiments, the second gate spacers 314 may be consumed during processing, creating a larger volume for the gate electrodes 348.
Returning back to
In some embodiments, the method 100 includes applying a hard mask over the metal fill in the plurality of first source/drain regions. In some embodiments, the method 100 includes performing similar process steps for the plurality of second source/drain regions after applying the hard mask over the metal fill in the plurality of first source/drain regions. For example, in some embodiments, the method includes performing a controlled epitaxial growth process to deposit silicon or silicon germanium on exposed sidewalls of the nanosheet channel layers in the plurality of second source/drain regions and only partially fill the plurality of second source/drain regions. In some embodiments, a silicide layer is deposited in the plurality of second source/drain regions followed by a metal fill. In some embodiments, the second metal fill extends from a lowermost nanosheet channel layer to above an uppermost nanosheet channel layer to facilitate the reduced source/drain contact resistance. In some embodiments, the inner spacers are formed in the plurality of second source/drain regions prior to depositing the silicide layer in the plurality of second source/drain regions. In some embodiments, after the method fill process, a suitable middle end of line (MEOL) or back end of line (BEOL) process may be performed on the device 200.
While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof. For ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in the accompanying drawings. Any such layers, structures, and/or regions not explicitly shown may be present in the actual semiconductor device structures. Further, with respect to semiconductor processing techniques, the descriptions provided herein are not intended to encompass all of the processing procedures that may be required to form a functional semiconductor integrated circuit device.
This application claims benefit of U.S. provisional patent application Ser. No. 63/185,766, filed May 7, 2021, and provisional patent application Ser. No. 63/324,615, filed Mar. 28, 2022, both of which are herein incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| 63324615 | Mar 2022 | US | |
| 63185766 | May 2021 | US |
