The present invention relates to a package-then-etch three-dimensional package structure electrically connected by plated copper pillars and belongs to the field of semiconductor packaging technologies.
In order to meet the demand for small and light semiconductor packaging, nowadays, packaging of a metal lead frame or an organic substrate is working in two directions: 1, reduction of the package size; and 2, functional integration. For reduction of the package size, there is a limited space for improvement. Thus, the packaging industry is focused on improvement of functional integration. That is, part of functional components or other electronic devices are integrated inside a substrate by means of embedding to improve the functional integration level of an entire package. However, since the substrate with the components embedded therein has more complicated and diversified interlayer materials and different materials have significantly different thermal expansion coefficients, the whole substrate is serious in warping and aggravated in layering, and even, delamination may be caused.
The present invention aims to solve the technical problem by providing a package-then-etch three-dimensional package structure electrically connected by plated copper pillars and a process thereof for the prior art. The three-dimensional package structure allows components to be embedded therein so as to improve the functional integration level of an entire package. A circuit layer prepared by the process is encapsulated at one side of a metal carrier. The metal carrier is reserved in the process flow, such that the product reliability can be improved.
The present invention adopts the following technical solution to solve the problem: a process of a package-then-etch three-dimensional package structure electrically connected by plated copper pillars includes:
step 1, taking a metal carrier;
step 2, preplating a surface of the metal carrier with a copper layer;
step 3, forming an outer metal pin by means of electroplating:
forming the outer metal pin on the front side of the metal carrier by means of electroplating;
step 4, performing plastic packaging with epoxy resin:
performing plastic packaging on a peripheral region of the outer metal pin with epoxy resin for protection, and enabling the top end of the outer metal pin to be exposed outside a surface of a molding compound by means of surface grinding;
step 5, forming a metal circuit layer by means of electroplating:
forming the metal circuit layer on the surface of the molding compound in step 4 by means of chemical plating or electroplating;
step 6, forming a conductive metal pillar by means of electroplating:
forming the conductive metal pillar on a surface of the metal circuit layer by means of electroplating;
step 7, surface-mounting a chip:
mounting the chip on the surface of the metal circuit layer;
step 8, performing plastic packaging:
performing plastic packaging on peripheral regions of the metal circuit layer, the conductive metal pillar and the chip by means of a molding compound, and enabling the top end of the conductive metal pillar to be exposed outside a surface of the molding compound by means of surface grinding;
step 9, surface-mounting a passive device:
surface-mounting the passive device at the top end of the conductive metal pillar exposed in step 8;
step 10, performing plastic packaging:
performing plastic packaging on a peripheral region of the passive device by a molding compound;
step 11, etching and windowing the carrier:
etching and windowing the back side of the metal carrier to expose the back side of the outer metal pin;
step 12, forming an anti-oxidant metal layer by means of electroplating:
forming the anti-oxidant metal layer on the exposed back side of the outer metal pin by means of electroplating; and
step 13, performing cutting to obtain a finished product:
cutting a semi-finished product electroplated with the anti-oxidant metal layer in step 12, such that plastic package modules which are originally integrated by means of array aggregation are independently cut off to produce the finished product of the package-then-etch three-dimensional package structure electrically connected by the plated copper pillars.
The copper layer in step 2 has a thickness of 2-10 microns.
The copper layer in step 2 is prepared by means of chemical deposition, electro-deposition or vapor deposition.
The outer metal pin and the metal circuit layer are made of copper, aluminum or nickel, and the anti-oxidant metal layer is made of gold, nickel-gold, nickel-palladium-gold or tin.
The plastic package adopts glue filling by a mold, spray-coating by a spraying device, filming or brush coating.
The etching in step 11 adopts an etching process using copper chloride or ferric chloride.
A package-then-etch three-dimensional package structure electrically connected by plated copper pillars includes a metal circuit layer. A conductive metal pillar is disposed on the front side of the metal circuit layer. A outer metal pin is disposed on the back side of the metal circuit layer. A peripheral region of the outer metal pin is encapsulated with a pre-encapsulating material. A chip is disposed on the metal circuit layer. Peripheral regions of the metal circuit layer, the conductive metal pillar and the chip are encapsulated with a first molding compound. The top end of the conductive metal pillar is exposed outside the first molding compound. A first passive device is disposed at the top end of the conductive metal pillar through a welding flux. A peripheral region of the first passive device is encapsulated with a second molding compound.
The chip is a face-up chip or a flip chip.
A second passive device is disposed at one side of the chip.
A plurality of chips is provided.
Compared with the prior art, the present invention has the following advantages.
1. According to the three-dimensional package structure provided by the present invention, objects are embedded during manufacture of intermediate interlayers of a substrate. An active or passive component may be embedded into a required position or region according to system or functional demands. A packaged and integrated system has more functions. Thus, a component module with the same function takes up less space on a PCB. Thus, the cost is lowered and the packaging integration level is improved.
2. According to three-dimensional package structure provided by the present invention, all pin circuit layers are designed at one side of the metal carrier and encapsulated inside a product, such that oxidation caused by outside exposure is prevented. Accordingly, the packaging reliability is improved.
3. According to the three-dimensional package structure provided by the present invention, as packaging is performed at one side of the metal carrier and the metal carrier is reserved in the package process flow, a holding-back effect can be achieved when the molding compounds contract with cold. Thus, the entire package structure can be effectively prevented from warping and product breakage is reduced.
Reference numbers in the drawings are described as below: metal carrier—1; locating hole—2; copper layer—3; pre-encapsulating material—4; outer metal pin—5; conductive layer—6; metal circuit layer—7; metal bump—8; conductive metal pillar—9; first molding compound—10; flip chip—11; first passive device—12; second molding compound—13; face-up chip—14; metal wire—15; and second passive device—16.
The present invention will be further described in detail below with reference to the accompanying drawings.
As shown in
A process thereof includes the following steps.
In step 1, a metal carrier is taken.
Referring to
In step 2, a surface of the metal carrier is preplated with a copper layer.
Referring to
In step 3, photoetching is performed.
Referring to
In step 4, the outer metal pin is formed by electroplating.
Referring to
In step 5, the photoresist material is removed.
Referring to
In step 6, plastic package is performed with epoxy resin.
Referring to
In step 7, surface grinding is performed.
Referring to
In step 8, a conductive layer is prepared on the surface of the epoxy resin.
Referring to
In step 9, photoetching is performed.
Referring to
In step 10, the metal circuit layer is formed by electroplating.
Referring to
In step 11, photoetching is performed.
Referring to
In step 12, the conductive metal pillar is formed by electroplating.
Referring to
In step 13, the photoresist material is removed.
Referring to
In step 14, rapid etching is performed.
Referring to
In step 15, a chip is inversely mounted.
Referring to
In step 16, plastic package is performed.
Referring to
In step 17, surface grinding is performed.
Referring to
In step 18, a passive device is surface-mounted.
Referring to
In step 19, plastic package is performed.
Referring to
In step 20, photoetching is performed.
Referring to
In step 21, the carrier is etched.
Referring to
In step 22, the photoresist material is removed.
Referring to
In step 23, an anti-oxidant metal layer is formed by electroplating.
Referring to
In step 24, cutting is performed to obtain a finished product.
Referring to
Referring to
Referring to
Embodiment 4: single circuit layer, a plurality of flip chips and stacked passive device
Referring to
Embodiment 5: single circuit layer, a plurality of face-up chips and stacked passive device
Referring to
Embodiment 6: single circuit layer and face-up chip+passive device and stacked passive device
Referring to
Embodiment 7: single circuit layer and flip chip+passive device and stacked passive device
Referring to
Embodiment 8: single circuit layer, a plurality of passive devices and stacked passive device
Referring to
In addition to the above-described embodiments, the present invention further includes other embodiments, and any technical solution formed by equivalent transformations or equivalent substitutions should fall within the protection scope defined by the claims of the present invention.
Number | Date | Country | Kind |
---|---|---|---|
201611192921.8 | Dec 2016 | CN | national |
The present application is the Continuation application of U.S. Ser. No. 16/471,904 filed on Jun. 20, 2019, which is the U.S. national phase application of PCT Application No. PCT/CN2017/116053 filed on Dec. 14, 2017, which claims priority to Chinese Patent Application No. 201611192921.8, filed on Dec. 21, 2016 and entitled “Process of Package-before-Etch Three-dimensional Package Structure Electrically Connected by Plated Copper Pillars”, the entire contents of which are incorporated herein by reference in their entireties.
Number | Date | Country | |
---|---|---|---|
Parent | 16471904 | Jun 2019 | US |
Child | 17537335 | US |