This patent application is based upon and claims priority to Japanese Patent Application No. 2018-210072 filed on Nov. 7, 2018, the entire contents of which are incorporated herein by reference.
The present disclosure relates to a processing method and a substrate processing apparatus.
For example, Patent Document 1 proposes a technique for reducing irregularity of a pattern, which includes a step of depositing deposits on a recess of a hole or line pattern and a step of etching off protuberances.
For example, Patent Document 2 proposes a method including a step of providing a patterned photoresist mask, a step of depositing a coating on the photoresist mask, a step of etching features in the etching layer, and a step of removing the photoresist mask.
[Patent Document 1] U.S. Pat. No. 9,922,839
[Patent Document 2] Japanese National Publication of International Patent Application Publication No. 2010-516059
The present disclosure provides a technique for suppressing variation in mask patterns.
According to one aspect of the present disclosure, there is provision of a processing method including a) depositing deposits on a patterned mask layer formed over an etching film; b) removing a part of the mask layer, a part of the deposits, or both the part of the mask layer and the part of the deposits; and c) repeating a) and b) at least once, thereby causing a taper angle of a side surface of a pattern formed in the mask layer to be a desired angle.
In the following, embodiments of the present invention will be described with reference to the drawings. Note that in the following descriptions and the drawings, elements having substantially identical features are given the same reference symbols and overlapping descriptions may be omitted.
First, an example of a substrate processing apparatus 1 will be described with reference to
A stage 3 is provided inside the processing vessel 2, to mount a wafer W, which is an example of a substrate. The stage 3 is formed of, for example, aluminum (Al), titanium (Ti), silicon carbide (SiC), or the like. The stage 3 is fixed at a bottom of the processing vessel 2, and also functions as a bottom electrode.
The stage 3 includes a base 12 and an electrostatic chuck 10 on the base 12. The electrostatic chuck 10 is configured such that a chuck electrode 10a is embedded in an insulator 10b. A direct current (DC) power supply 30 is connected to the chuck electrode 10a via a switch 31. When the switch 31 is turned on, DC voltage is applied from the DC power source 30 to the chuck electrode 10a. When the switch 31 is turned off, applying of DC voltage to the chuck electrode 10a is stopped. When DC voltage is applied to the chuck electrode 10a, the wafer W is attracted to the electrostatic chuck 10 by Coulomb force.
An edge ring 11 (may also be referred to as a “focus ring”) is circular, and is provided around the wafer W on an outer periphery of the electrostatic chuck 10. The edge ring 11 is formed of silicon for example, and functions to improve efficiency of a plasma process by making the plasma converge above the wafer W.
A coolant passage 12a is formed within the base 12. For example, a cooling medium (hereinafter, referred to as “coolant”) such as cooling water or brine is output from a chiller 36, flows from a coolant inlet pipe 12b to a coolant outlet pipe 12c through the coolant passage 12a, and returns to the chiller 36. As a result, heat is released from the stage 3, and the stage 3 is cooled.
A heat transmitting gas supply source 37 supplies heat transmitting gas, such as helium gas (He), between a surface of the electrostatic chuck 10 and a back surface of the wafer W through a heat transmitting gas supply line 16. A temperature of the electrostatic chuck 10 is controlled by the coolant circulating in the coolant passage 12a and the heat transmitting gas supplied to the back surface of the wafer W. As a result, the wafer W can be maintained in a predetermined temperature.
A high frequency power supply 34 (may also be referred to as a radio frequency power supply 34) is connected to the stage 3 via a matching device 35 to apply, to the stage 3, radio frequency electric power LF of a second frequency for generating bias voltage. The second frequency may be, for example, 13.56 MHz. The matching device 35 causes a load impedance to match internal impedance (output impedance) of the radio frequency power supply 34.
A showerhead 20 is mounted to occlude an opening in the ceiling of the processing vessel 2 via a shield ring 21 covering its outer edge. The showerhead 20 may be formed of silicon. A high frequency power supply 32 (may also be referred to as a radio frequency power supply 32) is connected to the showerhead 20 via a matching device 33, to apply, to the showerhead 20, radio frequency electric power HF for plasma generation of a first frequency higher than the second frequency. The first frequency may be, for example, 60 MHz. The radio frequency power HF may also be applied to the stage 3.
A variable DC power supply 26 is connected to the showerhead 20, and applies negative DC voltage to the showerhead 20. The showerhead 20 also functions as a counter-electrode (upper electrode) facing the stage 3 (lower electrode). The matching device 33 caused a load impedance to match an internal impedance (or output impedance) of the high frequency power supply 32.
A gas supply source 23 supplies gas used for a plasma process to a diffusion chamber 24a in a center of the showerhead 20 and a diffusion chamber 24b on an outer side of the showerhead 20, through a gas inlet 22. The gas diffused inside the diffusion chamber 24a on the center side and the diffusion chamber 24b on the outer side is introduced into the stage 3 from gas supply holes 25.
An exhaust port 18 is formed at a bottom of the processing vessel 2. An exhaust device 38 is connected to the exhaust port 18, and evacuates an interior of the processing vessel 2. This maintains the inside of the processing vessel 2 at a predetermined quality of vacuum. A gate valve 17 opens and closes a conveyance port 19 at a side wall of the processing vessel 2, to load an unprocessed wafer W into the processing vessel 2, or to unload the wafer W from the processing vessel 2.
A controller 40 controls an entire operation of the substrate processing apparatus 1. The controller 40 includes a CPU 41, a ROM 42, and a RAM 43. The CPU 41 controls a plasma process, such as etching and deposition, using plasma according to a recipe stored in the ROM 42 or the RAM 43. The recipe includes control information of the substrate processing apparatus 1 for a certain process condition, such as a process time, pressure (gas exhaust), magnitude of radio frequency electric power or voltage, flow rates of various gases, a temperature inside the processing vessel 2 (upper electrode temperature, side wall temperature of the processing vessel, wafer W temperature, electrostatic chuck temperature, etc.), and a coolant temperature. The recipe may be stored in a hard disk drive or a semiconductor memory. Alternatively, the recipe may be recorded in a removable storage medium such as a CD-ROM or a DVD, and the removable storage medium may be loaded in a predetermined place in an accessible state.
In performing a plasma process, the controller 40 opens the gate valve 17, loads the wafer W through the conveyance port 19, and mounts the wafer W on the stage 3. The controller 40 causes DC voltage of positive or negative polarity to be applied to the chuck electrode 10a, so that the wafer W is attracted to the electrostatic chuck 10.
The controller 40 supplies a desired gas from the gas supply source 23 into the processing vessel 2, causes radio frequency electric power HF and negative DC voltage to be applied to the showerhead 20, and causes high frequency electric power LF to be applied to the stage 3. By the above-described operation being performed, the gas is dissociated and a plasma is generated above the wafer W. By an effect of the plasma, the wafer W is plasma processed.
After the plasma process, by control of the controller 40, DC voltage having an opposite polarity to the polarity when the wafer W is attracted is applied to the chuck electrode 10a, to remove electric charge on the wafer W. After the removal of the electric charge, the controller 40 causes the wafer W to be removed from the electrostatic chuck 10, opens the gate valve 17, and unloads the wafer W from the conveyance port 19 to an outside of the processing vessel 2.
As die shrink progresses, wiring resistance or contact resistance increases. Thus, because variation in wiring resistance or contact resistance tends to affect variation in device performance, suppressing variation in wiring resistance or contact resistance has become important.
Accordingly, in a substrate processing method according to one embodiment to be described below, local critical dimension uniformity (hereinafter, may also be referred to as “L-CDU”) of a contact hole pattern is improved. The L-CDU represents variation in critical dimension (CD) of adjacent contact holes. Examples of measures indicating pattern variation in line patterns include LWR (line width roughness) and LER (line edge roughness).
Referring to
The resist film 108 is an organic film having a pattern of contact holes (hereinafter, also may be referred to as a “mask pattern”) formed thereon, and functions as a patterned mask layer. The SOG film 106, the SOC film 104, and the silicon oxide film 102 are examples of films to be etched (may also be referred to as “etching target films”).
In step S1 of
Next, in step S2, the controller 40 performs treatment of the resist film 108 with an H2 gas plasma or an HBr gas plasma.
Referring back to
Next, in step S4 of
The controller 40 repeats the above cycle step one or more times to control the taper angle of the side surface of the mask pattern of the resist film 108 to a desired angle, to eliminate variation in CD size. As a result, as illustrated in
Next, in step S5 of
Next, if it is determined that the cycle step has not been repeated the predetermined number of times, the controller 40 repeats execution of steps S3 to S5. This controls the taper angle of the side surface of the mask pattern of the resist film 108 to a desired angle. The predetermined number of times is a value greater than zero.
If it is determined in step S5 that the predetermined number of the cycle steps has been executed repeatedly, the controller 40 etches the SOG film 106 in step S6. As a result, as illustrated in
The wafer W unloaded from the processing vessel 2 is transported to an ashing device or a wet cleaning device, and the SOC film 104 on the silicon oxide film 102 or a residue on the wafer W is removed, but is not limited thereto. For example, after the end of step S6 and during step S7, the controller 40 may perform a step of removing the SOC film 104 by ashing.
Process conditions of each of the steps in the above-described substrate processing method will be described.
First, the process condition of the treatment step in step S2 of
Type of gas: H2 gas, Ar gas
However, types of gas used in the treatment step are not limited to the above-mentioned gases. For example, HBr gas or Ar gas may be supplied.
Next, the process condition of the deposition step of step S3 is as follows.
Type of gas: CH4 gas, H2 gas, Ar gas
However, types of gas used in the deposition step are not limited to the above-mentioned gases. For example, instead of the CH4 gas, a gas containing at least one of other hydrocarbon (CH) gases, a hydrofluorocarbon (CHF) gas, and a fluorocarbon (CF) gas may be used. In the following, a gas used in the deposition step may be referred to as a first gas. In the deposition step, a plasma process is performed using the first gas. The first gas does not necessarily contain H2 gas. Alternatively, N2 gas or other inert gas may be used instead of Ar gas.
Next, the process condition of the removal step of step S4 is as follows.
Gas type: CO2 gas, CH4 gas
However, types of gas used in the removal step are not limited to the above-described gases. For example, O2 gas, CO gas, N2 gas, or H2 gas may be used instead of CO2 gas. Also, instead of CH4 gas, other hydrocarbon (CH) gas, hydrofluorocarbon (CHF) gas, or fluorocarbon (CF) gas may be used.
Next, the process conditions of the etching step of step S6 is as follows.
Type of gas: CHF3 gas and CF4 gas
However, types of gas used in the etching step are not limited to the above-described gases.
In the deposition step, deposits are caused to adhere to the side surface of the contact hole. At this time, the deposits tend to adhere more to a larger hole than to a smaller hole (loading effect). In the present embodiment, this loading effect of deposits is utilized.
In the removal step, deposits that have adhered to the side surface of the contact holes during the deposition step are removed evenly. By repeating the set of the deposition step and the removal step, the CD size of each of the contact holes can become uniform, and L-CDU improves.
As illustrated in
As the cycle steps were repeated and the cycle count increased, the maximum difference in the CD value decreased, as illustrated in
As illustrated in the middle of
A graph in
A curve Y in
In order to reduce L-CDU(3σ)/CD, it is desirable to adjust the taper angle of the mask pattern to 85° to 90° after the cycle step(s) (see the area in the rounded corner rectangle (labeled as “O”) in
In addition, from the experimental result in
As described above, in the deposition step, deposits can be deposited on the side surface of the contact hole to increase the taper angle. Also, in the removal step, a portion of the deposits on the side surface of the contact hole can be removed to reduce the taper angle. Thus, the taper angle of the mask pattern can be controlled by repeating the deposition and removal steps. In addition, by controlling the number of cycles (cycle count) in which the deposition and removal steps are repeated, time for the deposition and removal steps can be controlled, thereby improving L-CDU by adjusting the taper angle to a range between 85° and 95°.
That is, by repeating the deposition step and the removal step, the controller 40 controls a processing time of the cycle step, and can adjust a shape of the mask such that the taper angle after the cycle step(s) becomes 85° to 95°. This can improve L-CDU. By performing the process of eliminating variation in the CD size of the resist film 108 as described above, variation in the CD size when etching the SOG film 106 can be suppressed. Further, it is possible to suppress the CD size variation when etching the SOC film 104 and the silicon oxide film 102 sequentially by using the SOG film 106 as a mask. This allows an etched shape in the silicon oxide film 102 to be vertical while eliminating variation in CD of the etched shape, thereby improving device performance.
Next, the gas dependence of the deposition step will be described with reference to
A curve E of the graph of
According to the result in
A graph in
In particular, a set of Ar gas, H2 gas, and CH4 gas used in the experiment corresponding to the curve E, a set of Ar gas and CH4 gas used in the experiment corresponding to the curve F, and a set of Ar gas and CH3F gas used in the experiment corresponding to the curve G, could reduce L-CDU(3σ)/CD as compared to a set of Ar gas and CH2F2 gas used in the experiment corresponding to the curve H, or a set of Ar gas and C4F8 gas used in the experiment corresponding to the curve I. According to the above-described results, it was found that an amount of H atoms in the first gas used in the deposition step is preferably greater than an amount of F atoms, and that adjusting the taper angle to a range between 85° and 95° is more preferable. For example, it has been found that CH4 gas and CH3F gas is more preferable for a gas used in the deposition step, as compared to CH2F2 or C4F8 gas.
Next, pressure dependence in the deposition step will be described with reference to
Curves J illustrated in
According to the experimental results in
Next, temperature dependence in the deposition step will be described with reference to
According to the experimental results in
Next, adjustment of the taper angle in the cycling step of the substrate processing method will be described with reference to
Let the taper angle of the side surface of the resist film 108 in an initial state (before executing a cycle step) be θ0. In the substrate processing method according to the embodiment, the deposition step and the removal step are respectively repeated N times (note: N is a predetermined integer value not less than 0, and N corresponds to a cycle count). Let an increase amount of the taper angle in the n-th (n≤N) deposition step be ΔθD,n, and an amount of decrease of the taper angle in the n-th removal step be ΔθT,n. The controller 40 adjusts process conditions of the deposition step and the removal step (such as a processing time, gas type, pressure, and a temperature) so that the following formula (1) can be satisfied.
In
Formula (1) illustrates a condition in which the taper angle becomes between 85° and 95°, in a case in which a change amount of the taper angle differs in each step (deposition step and removal step), as illustrated in
Formula (2) illustrates a condition in which the taper angle is between 85° and 95° in a case in which the amount of increase of the taper angle in each of the deposition step is the same and the amount of decrease of the taper angle in each of the removal step is the same (that is, ΔθD,1=ΔθD,2=ΔθD,3= . . . =ΔθD,N=ΔθD and ΔθT,1=ΔθT,2=ΔθT,3 . . . =ΔθT,N=ΔθT are established), as illustrated in
85°≤(ΔθD−ΔθT)×N+θ0≤95° (2)
The process condition to be adjusted is a processing time of the deposition step, a processing time of the removal step, a type of gas used in the deposition step, pressure during the deposition step, a temperature during the deposition step, or combinations thereof. For example, in order to adjust the processing time of the deposition step and the processing time of the removal step, data indicating a relationship between a processing time (time of deposition step, time of removal step) and a taper angle (as illustrated in the graphs in
Also, for example, with respect to the type of gas used in the deposition step, data indicating a relationship between a processing time (time of deposition step) and a taper angle may be obtained in advance for each type of gas, as illustrated in the graph of
Also, for example, with respect to the pressure during the deposition step, data indicating a relationship between pressure and a taper angle, as illustrated in the graph of
Also, for example, with respect to the temperature during the deposition step, data indicating a relationship between a temperature and a taper angle, as illustrated in the graph of
As examples of adjustment of process conditions, adjustment of a processing time of the deposition step and/or the removal step, a type of gas used in the deposition step, pressure during the deposition step, and a temperature during the deposition step, are described above. However, adjustment of process conditions is not limited to the above examples. For example, data indicating a relationship between a taper angle and a gas type used in the removal step, pressure during the removal step, a temperature during the removal step, or other process parameters may be stored in the ROM 42 or the RAM 43 in advance, and the CPU 41 may adjust process conditions based on the data.
In this case, in a case in which a cycle count (the number of times the deposition and removal steps are repeated) is two or more, the process conditions of the n-th deposition step and the (n+1)-th deposition step may be the same, or may be different.
Furthermore, in a case in which a cycle count is two or more, the process conditions of the n-th removal step and the (n+1)-th removal step may be the same, or may be different, regardless of whether the n-th deposition step and the (n+1)-th deposition step have the same or different process conditions.
In the above-described processing method, the deposition step is performed first, the removal step is then performed, and the deposition step and the removal step are repeated several times. However, the present invention is not limited thereto. For example, as illustrated in
Formula (3) illustrates a condition in which the taper angle becomes between 85° and 95°, in a case in which the change amount of the taper angle differs in each step, as illustrated in
In the above description, in a case in which the deposition step and the removal step are repeated, both the deposition step and the removal step are executed the same number of times, but the above is not limited thereto. For example, in a case in which the deposition step is performed first and the removal step is performed next as illustrated in
Formula (4) illustrates a condition in which the taper angle becomes between 85° and 95°, in a case in which the change amount of the taper angle differs in each step, as illustrated in
where ΔθT,N=0.
In a case in which the removal step is performed first and the deposition step is performed next, the removal step may be performed N times while the deposition step is performed (N−1) times.
Also, in the above-described embodiment, while performing a certain deposition step (n-th deposition step, for example) or while performing a certain removal step (n-th removal step, for example), the step (deposition step or removal step) is performed under a single process condition, but is not limited thereto. For example, a deposition step may be composed of multiple sub-steps, and parameters such as a gas type, pressure, or a temperature may be switched or changed in each of the multiple sub-steps during the deposition step. Alternatively, a removal step may be composed of multiple sub-steps, and parameters such as a gas type, pressure, or a temperature may be switched or changed in each of the multiple sub-steps.
In addition, the controller 40 may divide the multiple cycle steps, each of which is composed of the deposition step and the removal step, into two groups as illustrated in
ΔθD−ΔθT≅0° (5)
Thus, the side surface of the resist film 108 can be adjusted to be substantially vertical in the phase P, and in the phase Q, irregularities of the pattern surface can be reduced and the pattern surface can be made to be smooth while maintaining the vertical shape of the side surface of the resist film 108. That is, in the first phase (phase P), the taper angle can be controlled. Further, in the second phase (phase Q), deposits are deposited preferentially on a recess of the pattern surface in the deposition step, and the removal step causes etching to proceed from a protuberance of the pattern surface. This can reduce irregularities on the surface of the pattern while maintaining the taper angle in a substantially vertical shape.
The processing method and the substrate processing apparatus according to the present embodiment disclosed herein are to be considered exemplary in all respects and not limiting. The above embodiment may be modified and enhanced in various forms without departing from the appended claims and gist thereof. Matters described in the above embodiment may take other configurations to an extent not inconsistent, and may be combined to an extent not inconsistent.
The substrate processing apparatus of the present disclosure is applicable to any types of substrate processing apparatuses, such as a capacity coupled plasma (CCP) type, an inductively coupled plasma (ICP) type, a radial line slot antenna (RLSA) type, an electron cyclotron resonance plasma (ECR) type, and a helicon wave plasma (HWP) type.
In the present specification, a wafer W has been described as an example of a substrate. However, the substrate may not be limited thereto, and may be various types of substrates used in a flat panel display (FPD), a printed circuit board, or the like.
Number | Date | Country | Kind |
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JP2018-210072 | Nov 2018 | JP | national |
Number | Name | Date | Kind |
---|---|---|---|
8592327 | Ranjan | Nov 2013 | B2 |
9922839 | Wise et al. | Mar 2018 | B2 |
20070181530 | Huang | Aug 2007 | A1 |
20100068885 | Cirigliano | Mar 2010 | A1 |
20130267097 | Srivastava | Oct 2013 | A1 |
20150037943 | Park | Feb 2015 | A1 |
Number | Date | Country |
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2010-516059 | May 2010 | JP |
2008086361 | Jul 2008 | WO |
Number | Date | Country | |
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20200144051 A1 | May 2020 | US |