Patent Grant
11725270
Integrated circuits, used in advanced electronics devices, enable applications such as high-speed computing and data storage. Nanoscale transistors and metal interconnects form the two essential building blocks of an integrated circuit. The transistors perform the logic functions. Generally, after a transistor is formed, electrical contacts are made to connect a source region, a drain region, and/or a gate region of the transistor to make the transistor fully functional. Subsequently, metal interconnects provide the wiring between transistors are formed.
The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not necessarily to scale. On the contrary, the dimensions and spatial relationship(s) of the various features may be arbitrarily enlarged or reduced for clarity. Like reference numerals denote like features throughout specification and drawings.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
For formation of electrical contacts for a transistor, lithographic techniques are used to define contact openings in a dielectric layer that overlies the source, drain, and gate regions of the transistor. The contact openings are then filled with a metal filling material (e.g., copper) to form electrical contacts.
For formation of metal interconnects, single and/or dual-damascene processes are typically used. In these processes, contact openings includes trenches or combinations of trenches and vias are first etched in a dielectric layer, followed by deposition of a diffusion barrier layer. The contact openings are then filled with a metal filling material (e.g., copper) to form the metal interconnects.
As circuits are scaled to smaller dimensions in a continual effort to provide increased density and performance, the interconnect linewidth becomes increasingly narrow, which in turn renders the metal interconnects more susceptible to deleterious effects such as electromigration. Electromigration is caused by transfer of conductive metals to the adjacent dielectric layer(s) through diffusion of ions or atoms. Electromigration decreases the reliability of integrated circuits, and eventually may cause degradation or failure of a semiconductor device.
Accordingly, a diffusion barrier layer with improved electromigration properties becomes increasingly important to the reliability of integrated circuits. The diffusion barrier layer may be formed from a metal containing material. Suitable examples of the metal containing material include, but are not limited to, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON), tantalum oxynitride (TaON), and combinations thereof.
The material of the diffusion barrier layer is deposited by a conformal deposition process such as, for example, physical vapor deposition (PVD) process. The PVD process is carried out under high vacuum in a deposition chamber containing a substrate (e.g., a semiconductor wafer) and a sputtering source composed of material to be deposited on the substrate, e.g., a PVD target. In the PVD process, the PVD target is negatively biased and exposed to plasma of an inert gas having relatively heavy atoms such as argon (Ar) gas or a gas mixture comprising such inert gas. Bombardment of the PVD target by ions of the inert gas results in ejection of atoms of the PVD target source material. The ejected atoms accumulate as a deposited film on the substrate.
In the PVD process, the compositions of the deposited diffusion barrier layer are restricted by the composition of the PVD target. In embodiments of the present disclosure, to help to avoid device performance degradation due to electromigration of the contact metal, dopants such as nickel (Ni) and the like are introduced into the source material of the PVD target to be deposited on the substrate during the PVD process. Because nickel has a lower metal point than the sputtering source material, the dopants in the sputtering source material of the PVD target affects target material deposition rate, which in turn changes PVD process window and improve wafer accept test yield. Further, the resulting diffusion barrier layer contains the sputtering source material as well as the dopants intentionally introduced in the PVD target. The dopants in the diffusion barrier layer helps to reduce the electromigration effect, which in turns helps to increase the lifetime of the integrated circuits.
The backing plate 110 is composed of or made from a conductive material, such as copper, copper alloys, zinc, copper-zinc alloys, steel, stainless steel, iron, nickel, chromium, copper-chromium alloys, aluminum, lead, silicon, alloys thereof, derivatives thereof, or combinations thereof. In some embodiments, the backing plate 110 contains copper or a copper alloy. In some embodiments, the backing plate 110 includes a copper alloy having a copper concentration a range from about 50% by weight to about 99.9% by weight, such as from about 55% by weight to about 95% by weight. In some other embodiments, the backing plate 110 includes a copper alloy having a copper concentration in a range from about 50% by weight to about 70% by weight. In some embodiments, the backing plate 110 includes a copper-zinc alloy. In some embodiments, the copper-zinc alloy has a copper concentration in a range from about 58% by weight to about 62% by weight and a zinc concentration in a range from about 38% by weight to about 42% by weight. In a specific example, the copper-zinc alloy of the backing plate 110 contains about 60.8% copper by weight and about 39.3% zinc by weight. In other embodiments, the copper-zinc alloy has a copper concentration in a range from about 75% by weight to about 85% by weight and a zinc concentration in a range from about 15% by weight to about 25% by weight. In one specific example, the copper-zinc alloy of the backing plate 110 contains about 80% copper by weight and about 20% zinc by weight.
In some embodiments, the backing plate 110 includes a copper-chromium alloy having a copper concentration a range from about 95% by weight to about 99.5% by weight and a chromium concentration in a range from about 0.5% by weight to about 5% by weight. In a specific example, the copper-chromium alloy of the backing plate 110 contains about 99% copper by weight and about 1% chromium by weight.
The target plate 120 includes a front surface (i.e., sputterable surface) 122 that is sputtered during the PVD process. The materials in the target plate 120 are, thus, deposited onto a substrate (e.g., a semiconductor wafer), e.g., substrate 402 (
The dopant 126 is introduced into the sputtering source material 124 in different manners. In some embodiments, the dopant 126 is introduced into the sputtering source material 124 with a uniform distribution. In some other embodiments, the dopant 126 is introduced into the sputtering source material 124 with a gradient distribution. In some embodiments, the centration of the dopant 126 in the target plate 120 decreases gradually from front to the back with the highest concentration near the front surface 122. In some embodiments, the centration of the dopant 126 in the target plate 120 increases gradually from front to the back with the lowest concentration near the front surface 122. In some embodiments, the dopant 126 is introduced into the sputtering source material 124 in a locally delimited manner such that the dopant is only present in localized regions of the target plate 120.
In some embodiments, the target plate 120 is diffusion bonded to the backing plate 110. In other embodiments, the targeting plate 120 is bonded to the backing plate 110 by an interlayer (not shown) disposed therebetween. The optional interlayer helps to increase the adhesion between the backing plate 110 and the target plate 120. In some embodiments, the interlayer contains a metal, such as aluminum, copper, nickel, derivatives thereof, or alloys thereof and may be in the form of a metallic insert, film, plate, or solder.
As in
During the PVD process, only the first target component 120 is sputtered, while the second target components 230 are intact. Consequently, using a material (i.e., the target base material 232) having a lower purity or a lower cost than the material to be sputtered (i.e., the sputtering source material 124) in the second target components 230 helps to reduce the cost of the PVD target 200, which also helps to reduce the fabrication cost costs and increase profitability.
As in
The second target component 330 is over the first target component 120. In some embodiments, the second target component 330 has a same dimension as that of the first target component 120. In some embodiments, the second target components 330 includes a first target base material (Ti) 332. The first target base material 332 may be the same as, or different from, the sputtering source material 124. In some embodiments, the first target base material 332 is the same as the sputtering source material 124, but with a lower purity. For example, in some embodiments, when the sputtering source material 124 is Ti having a purity of about 99.9995% (5N5) or greater, the first target base material 332 is also Ti but with a purity of less than 99.9995% (5N5). In some embodiments, the first target base material 332 in the second target component 330 has a purity of about 99.999% (5N). In some embodiments, the first target base material 332 is a metal having a cost lower than that of the sputtering source material 124.
The third target component 340 is over the second target component 330 adjacent to the plating plate 110. In some embodiments, the third target component 340 has a same dimension as that of the second target component 330. In some embodiments, the third target components 340 includes a second target base material (B2) 342. The second target base material 342 may be the same as, or different from, the first target base material 332. In some embodiments, the second target base material 342 is the same as the first target base material 332, but with a lower purity. For example, in some embodiments, when the first target base material 332 is Ti having a purity of about 99.999% (5N), the second target base material 342 is also Ti but with a purity of less than 99.999% (5N). In some embodiments, the second target base material 342 in the third target component 340 has a purity of about 99.995% (4N5). In some embodiments, the second target base material 342 has a metal having a cost lower than that of first second target base material 332. The third target component 340 is optional and is omitted in some embodiments.
During the PVD process, only the first target component 120 is sputtered, while the second target component 330 and the third target component 340 are intact. Such target configuration helps to reduce the cost of the PVD target 300, which also helps to reduce the fabrication costs and increase profitability.
In some embodiments, the PVD system 400 is a magnetron PVD system including a chamber body 412 which encloses a processing region or a plasma zone 414.
A substrate support 420 is disposed within the chamber body 412. The substrate support 420 has a substrate receiving surface 422 that receives and supports the substrate 402 during the PVD process, so that a surface of the substrate 402 is opposite to the front surface 122 of the PVD target 404 that is exposed to the processing region 414. The substrate support 420 is electrically conductive and is coupled to ground (GND) so as to define an electrical field between the PVD target 404 and the substrate 402. In some embodiments, the substrate support 420 is composed of aluminum, stainless steel, or ceramic material. In some embodiments, the substrate support 420 is an electrostatic chuck that includes a dielectric material.
A shield 430, also referred to as a dark space shield, is positioned inside the PVD chamber body 412 and proximate sidewalls 405 of the PVD target 404 to protect inner surfaces of the chamber body 412 and sidewall (i.e., target sidewall 405) of the PVD target 404 from unwanted deposition. The shield 430 is positioned very close to the target sidewall 405 to minimize re-sputtered material from being deposited thereon. The shield 430 has a plurality of apertures (not shown) defined therethrough for admitting a plasma-forming gas such as argon (Ar) from the exterior of the shield 430 into its interior.
A power supply 440 is electrically coupled to the backing plate 110 of the PVD target 404. The power supply 440 is configured to negatively bias the PVD target 404 with respect to the chamber body 412 to excite a plasma-forming gas, for example, argon, into a plasma. In some embodiments, the power supply 440 is a direct current (DC) power supply source. In other embodiments, the power supply 440 is a radio frequency (RF) power supply source.
A magnet assembly 450 is disposed above the PVD target 404. The magnet assembly 450 is configured to project a magnetic field parallel to the front surface 122 of the PVD target 404 to trap electrons, thereby increasing the density of the plasma and increasing the sputtering rate. In some embodiments, the magnet assembly 450 is configured to scan about the back of the PVD target 404 to improve the uniformity of deposition. In some embodiments, the magnet assembly 450 includes a single magnet disposed above the PVD target 404 (not shown). In some embodiments, the magnet assembly 450 includes an array of magnets. In some embodiments and as shown in
A gas source 460 is in fluidic combination with the chamber body 412 via a gas supply pipe 464. The gas source 460 is configured to supply a plasma-forming gas to the process region 414 via the gas supply pipe. The plasm-forming gas in an inert gas and do not react with the materials in the PVD target 404. In some embodiments, the plasma-forming gas includes argon, xenon, neon, or helium, which is capable of energetically impinging upon and sputtering source material and the dopant from the PVD target 404. In some embodiments, the gas source 460 is also configured to supply a reactive gas into the PVD system 400. The reactive gas includes one or more of an oxygen-containing gas, a nitrogen-containing gas, a methane-containing gas, that is capable of reacting with the sputtering source material in the PVD target 404 to form a layer on the substrate 402.
A vacuum device 470 is in fluidic communication with the PVD system 400 via an exhaust pipe 474. The vacuum device 470 is used to create a vacuum environment in the PVD system 400 during the PVD process. In some embodiments, the PVD system 400 has a pressure in a range from about 1 mtorr to about 10 torr. The spent process gases and byproducts are exhausted from the PVD system 400 through the exhaust pipe 474.
Referring to
In some embodiments, the substrate 602 is a bulk semiconductor substrate including silicon. Alternatively or additionally, in some embodiments the bulk semiconductor substrate includes another elementary semiconductor such as germanium, a compound semiconductor including gallium arsenide, gallium, phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor including SiGe, GaAsP, AlinAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In some embodiments, the substrate 602 includes an epitaxial layer. For example, the substrate 602 has an epitaxial layer overlying a bulk semiconductor substrate. Furthermore, in some embodiments, the substrate 602 is a semiconductor on insulator (SOI) substrate. For example, the substrate 602 includes a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable techniques, such as wafer bonding and grinding.
In some embodiments, the substrate 602 further includes active devices such as p-type field effect transistors (PFET), n-type FET (NFET), metal-oxide semiconductor (MOS) transistors, complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, and/or high frequency transistors. In some embodiments, the transistors are planar transistors or three-dimensional fin-type transistors. In some embodiments, the substrate 602 further includes passive devices such as resistors, capacitors, and/or inductors. The substrate 602 further includes isolation structures such as shallow trench isolation (STI) structures to separate various active and/or passive devices from one another.
The dielectric layer 610 is deposited over the substrate 602. In some embodiments and as in
In some embodiments, the dielectric layer 610 includes silicon oxide. In some embodiments, the dielectric layer 610 includes a low-k dielectric material having a dielectric constant (k) less than 4. In some embodiments, the low-k dielectric material has a dielectric constant from about 1.2 to about 3.5. In some embodiments, the dielectric layer 610 includes tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicate glass such as borophosphosilicate glass (BPSG), fluorosilica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. In some embodiments, the dielectric layer 610 is deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), PVD, or spin coating. In some embodiments, the dielectric layer 610 is planarized by a planarization process or otherwise recessed to provide a planar top surface. In some embodiments, the top surface of the dielectric layer 610 is planarized using a CMP process.
The dielectric layer 610 is subsequently etched to form a contact opening 612 therein. The contact opening 612 is a trench opening, a via opening, or a combination of a trench opening and a via opening with the via opening enclosed by the trench opening. In some embodiments and as in
The dielectric layer 610 is etched with one or more lithography and etching processes. In some embodiments, the lithography process includes applying a photoresist layer (not shown) over the dielectric layer 610, exposing the photoresist layer to a pattern, performing post-exposure baking, and developing the resist to form a patterned photoresist layer (not shown). The patterned photoresist layer exposes a portion of the dielectric layer 610 where the contact opening 612 is to be formed. Next, the portion of the dielectric layer 610 exposed by the patterned photoresist layer is etched to form the contact opening 612. In some embodiments, the dielectric layer 610 is etched using a dry etch such as, for example, a reactive ion etch (RIE) or a plasma etch. In some embodiments, the dielectric layer 610 is etched using a wet etch. After formation of the contact opening 612 in the dielectric layer 610, the patterned photoresist layer is removed, for example, by wet stripping or plasma ashing. Alternatively, in some embodiments, a hard mask is used such that the contact opening pattern is transferred from the pattered photoresist layer to the hard mask by a first etch and then transferred to the dielectric layer 610 by a second etch.
Referring to
The diffusion barrier layer 614 includes a doped diffusion barrier material that prevents the metal in a conductive material layer subsequently formed from diffusing into the dielectric layer 610. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ru, TiN, TaN, and WN. In some embodiments, the diffusion barrier layer 614 includes a stack of the above-mentioned diffusion barrier materials such as, for example, Ti/TiN or Ta/TaN. Example dopants include, but are not limited to, Ni and F. In some embodiments, the diffusion barrier layer 614 includes Ni doped Ti. In some embodiments, the diffusion barrier layer 614 is deposited utilizing a PVD process using a PVD target, e.g., PVD target 100, 200, or 300 described above, during which the substrate 602 is placed into the PVD system 400 (
Referring to
In some embodiments, the conductive material layer 616 includes Cu, Al, W, Co, alloys thereof, or other suitable conductive metals. In some embodiments, the conductive material layer 616 is deposited by a suitable deposition process such as, for example, CVD, PECVD, PVD, or plating. In some embodiments, especially when Cu or a Cu alloy is employed in the conductive material layer 616, an optional plating seed layer (not shown) is formed over the diffusion barrier layer 614 prior to the formation of the conductive material layer 616. In some embodiments, the optional plating seed layer is formed by a deposition process including, for example, CVD, PECVD, or PVD.
Referring to
A planarization process is performed to remove portions of the conductive material layer 616 and the diffusion barrier layer 614 from the top surface of the dielectric layer 610. In some embodiments, a chemical mechanical polishing (CMP) process is performed to removing portions of the conductive material layer 616 and the diffusion barrier layer 614 from the top surface of the dielectric layer 610. After the planarization, a remaining portion of the conductive material layer 616 in the contact opening 612 constitute a conductive plug 616P, and a remaining portion of the diffusion barrier layer 614 on sidewalls and bottom surface of the contact opening 612 constitute a diffusion barrier 614P. The diffusion barrier 614P and the conductive plug 616P together provide the contact structure 620. In some embodiments, the contact structure 620 is a source/drain contact for providing electrical contact to a source/drain region of a field effect transistor. In some embodiments, the contact structure 620 is an interconnect structure for providing electrical connection among different transistors.
One aspect of this description relates to a PVD target. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a sputtering source material and a dopant. The dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material.
Another aspect of this description relates to a PVD system. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a first target component and a second target component adjacent to the back plate. The first target component includes a sputtering source material and a dopant, and the second target component includes a target base material.
Still another aspect of this description relates to a method of forming a semiconductor device. The method includes forming a contact opening in a dielectric layer over a substrate. The method further includes positioning the substrate into a physical vapor deposition (PVD) chamber facing a PVD target including a target plate. The target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material. The method further includes sputtering the PVD target to deposit a diffusion barrier layer on sidewall and bottom surfaces of the contact opening. The diffusion barrier layer includes the sputtering source material and the dopant.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims the benefit of U.S. Provisional Patent Application No. 62/968,078, filed Jan. 30, 2020, which is incorporated by reference herein.
| Number | Name | Date | Kind |
|---|---|---|---|
| 6187682 | Denning et al. | Feb 2001 | B1 |
| 8729702 | Niu | May 2014 | B1 |
| 10017849 | Bellman et al. | Jul 2018 | B2 |
| 20040141870 | Michaluk et al. | Jul 2004 | A1 |
| 20050185454 | Brown | Aug 2005 | A1 |
| 20100266804 | Fery | Oct 2010 | A1 |
| 20140138832 | Niu | May 2014 | A1 |
| 20140306271 | Wu | Oct 2014 | A1 |
| 20150333012 | Chang et al. | Nov 2015 | A1 |
| 20170148739 | Roberts | May 2017 | A1 |
| 20200335331 | Xiao | Oct 2020 | A1 |
| 20210111300 | Fessehatzion | Apr 2021 | A1 |
| Number | Date | Country |
|---|---|---|
| 101473059 | Jul 2009 | CN |
| 105593399 | May 2016 | CN |
| S63161164 | Jul 1988 | JP |
| H07278804 | Oct 1995 | JP |
| H0959770 | Mar 1997 | JP |
| 2001262331 | Sep 2001 | JP |
| 2002060934 | Feb 2002 | JP |
| 2002294440 | Oct 2002 | JP |
| 201425624 | Jul 2014 | TW |
| Number | Date | Country | |
|---|---|---|---|
| 20210238731 A1 | Aug 2021 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62968078 | Jan 2020 | US |
