SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE COMPRISING THE SAME

Abstract

A semiconductor chip and a semiconductor package are provided. The semiconductor chip includes a substrate, a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer stacked on the substrate, lower pads on the second interlayer insulating layer and having a first thickness in a vertical direction, third and fourth interlayer insulating layers stacked on the lower pads and the second interlayer insulating layer, an upper pad on the fourth interlayer insulating layer and having a second thickness in the vertical direction greater than the first thickness, and via structures in the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connecting the lower pads and the upper pad. Each of the via structures includes a first via in the third interlayer insulating layer and a second via in the fourth interlayer insulating layer and overlapping the first via in the vertical direction.

Description

REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0143183, filed on Oct. 24, 2023, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The inventive concept relates to a semiconductor chip and a semiconductor package including the same.

A semiconductor package is configured to easily use an integrated circuit chip as a part of an electronic product. Conventionally, the semiconductor package includes a printed circuit board (PCB) and a semiconductor chip die, which is mounted on the PCB and is electrically connected to the PCB using bonding wires or bumps. With development of the electronics industry, many studies are being conducted to improve reliability and durability of semiconductor packages.

SUMMARY

An object of the inventive concept is to provide a semiconductor chip with improved reliability.

An object of the inventive concept is to provide a semiconductor package with improved reliability.

A semiconductor chip according to some embodiments of the inventive concept includes a substrate, a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer sequentially stacked on the substrate, lower pads on the second interlayer insulating layer and having a first thickness in a vertical direction, third and fourth interlayer insulating layers sequentially stacked on the lower pads and the second interlayer insulating layer, an upper pad on the fourth interlayer insulating layer and having a second thickness in the vertical direction greater than the first thickness, and via structures in the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connecting the lower pads and the upper pad, wherein each of the via structures includes a first via in the third interlayer insulating layer and a second via in the fourth interlayer insulating layer and overlapping the first via in the vertical direction.

A semiconductor chip according to some embodiments of the inventive concept includes a substrate, a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer sequentially stacked on the substrate, a through via in the first interlayer insulating layer and the substrate, a via insulating layer interposed between the through via and the substrate, wirings in the porous insulating layer, a contact plug in the first interlayer insulating layer and in contact with one of the wirings, lower pads on the second interlayer insulating layer and having a first thickness in a vertical direction, third and fourth interlayer insulating layers sequentially stacked on the lower pads and the second interlayer insulating layer, an upper pad on the fourth interlayer insulating layer and having a second thickness in the vertical direction greater than the first thickness, and via structures in the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connecting the lower pads and the upper pad, wherein the third interlayer insulating layer includes a first silicon oxide layer, a hydrogen barrier layer, and a second silicon oxide layer that are sequentially stacked, each of the via structures includes a first via that is in the third interlayer insulating layer and a second via that is in the fourth interlayer insulating layer and overlaps the first via in the vertical direction, and each of the via structures has a height of 1.0 μm to 10 μm in the vertical direction.

A semiconductor package according to some embodiments of the inventive concept includes a package substrate, a first semiconductor chip on the package substrate and a second semiconductor chip and a third semiconductor chip on the first semiconductor chip, wherein the second semiconductor chip and the third semiconductor chip are spaced apart from each other in a lateral direction, wherein the third semiconductor chip includes a buffer die and memory dies sequentially stacked, the first semiconductor chip and one of the memory dies each include a substrate, a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer sequentially stacked on the substrate, lower pads on the second interlayer insulating layer and having a first thickness in a vertical direction, a third interlayer insulating layer on the lower pads and the second interlayer insulating layer, an upper pad on the third interlayer insulating layer and having a second thickness in the vertical direction greater than the first thickness, and via structures electrically connecting the lower pads and the upper pad through the third interlayer insulating layer, each of the via structures of the first semiconductor chip has a first height in the vertical direction, and each of the via structures of the one of the memory dies has a second height in the vertical direction that is smaller than the first height.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein.

FIG. 1 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

FIGS. 2A to 2C show plan views of a landing pad and an upper pad according to embodiments of the inventive concept.

FIG. 3 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

FIG. 4 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

FIG. 5 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

FIG. 6 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

FIG. 7 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

FIG. 8 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

FIG. 9A is a cross-sectional view of a semiconductor package according to embodiments of the inventive concept.

FIG. 9B is an enlarged view of portion ‘P2’ of FIG. 9A.

FIGS. 10A to 10G are views sequentially showing a method of manufacturing the semiconductor chip of FIG. 1.

DETAILED DESCRIPTION

Hereinafter, to explain the inventive concept in detail, embodiments according to the inventive concept will be described with reference to the accompanying drawings. Herein, terms indicating order such as first, second, etc. are used to distinguish components that perform the same/similar functions, and their numbers may change depending on the order in which they are mentioned.

FIG. 1 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

Referring to FIG. 1, a semiconductor chip 100 according to the present example may include a substrate 1. In this specification, ‘semiconductor chip’ may also be referred to as ‘semiconductor die’. The substrate 1 may include, for example, a semiconductor material. The substrate 1 may be a silicon single crystal substrate. The substrate 1 may include a first region DR and a second region ER. For example, the first region DR may be a device region where integrated circuits and through vias are disposed. The second region ER may be a dummy region or an edge region.

Transistors TR may be disposed on a front surface of the substrate 1 in the first region DR. Although not shown, shallow device isolation patterns, memory cells, capacitors, etc. may be disposed on the front surface of the substrate 1 in the first region DR. The memory cells may include word lines and bit lines.

The front surface of the substrate 1 may be covered with a first interlayer insulating layer 3. The first interlayer insulating layer 3 may cover the transistors TR, memory cells, capacitors, etc. For example, the first interlayer insulating layer 3 may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. First contacts (e.g., contact plugs) 5c electrically connected to the transistors TR may be disposed in the first interlayer insulating layer 3 on the first region DR. For example, a first contact 5c may be in contact with a first wiring 11. Second contacts 5g may be disposed in the first interlayer insulating layer 3 on the second region ER. According to one example, each of the second contacts 5g may be a dummy pattern, a guard ring pattern, a chipping dam pattern, or a test pattern. The guard ring pattern or chipping dam pattern may serve to protect the first region DR from moisture or physical cracks. The guard ring pattern or chipping dam pattern may have a closed curve shape surrounding the first region DR when viewed in a plan view.

Multilayer porous insulating layers 10 are stacked on the first interlayer insulating layer 3. Each of the porous insulating layers 10 may be formed of a low-k material having a dielectric constant smaller than that of silicon oxide. Each of the porous insulating layers 10 may have a density less than that of the first interlayer insulating layer 3. A mechanical strength of each of the porous insulating layers 10 may be less than a mechanical strength of the first interlayer insulating layer 3. Each of the porous insulating layers 10 may include carbon. Each of the porous insulating layers 10 may include SiOCH. Although not shown, a silicon nitride layer or SiCN layer may be interposed between the porous insulating layers 10.

First vias 9 and first wirings 11 are disposed in the porous insulating layers 10 in the first region DR. Second vias 9g and second wirings 11g are disposed in the porous insulating layers 10 in the second region ER. Each of the first vias 9, first wirings 11, second vias 9g, and second wirings 11g may include copper. Side surfaces and a lower surface of each of the first vias 9, first wirings 11, second vias 9g, and second wirings 11g may be covered with a diffusion barrier layer. The diffusion barrier layer may include at least one of titanium, tantalum, titanium nitride, and tantalum nitride. At least one of the first vias 9, first wirings 11, second vias 9g, and second wirings 11g may have a dual damascene pattern structure.

Each of the second vias 9g and the second wirings 11g may be a dummy pattern, a guard ring pattern, a chipping dam pattern, or a test pattern. The guard ring pattern or chipping dam pattern may serve to protect the first region DR from moisture or physical cracks. The guard ring pattern or chipping dam pattern may have a closed curve shape surrounding the first region DR when viewed in a plan view.

The back surface of the substrate 1 is covered with a lower passivation layer 40. The lower passivation layer 40 may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, SiCN, and polyimide.

In the first region DR, a through via TV may penetrate the substrate 1, the lower passivation layer 40, and the first interlayer insulating layer 3 and may be in contact with one of the first wirings 11. As used herein, the term “contact” refers to direct, physical contact. The through via TV may be electrically connected to at least one of the transistors TR by some of the first wirings 11.

The through via TV may include copper or tungsten. A side surface of the through via TV may be covered with a diffusion barrier layer. The diffusion barrier layer may include at least one of titanium, tantalum, titanium nitride, and tantalum nitride. A via insulating layer TL may be interposed between the through via TV and the substrate 1. The via insulation layer TL may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The via insulating layer TL may include an air gap region therein.

A lower conductive bump 46 is disposed below the lower passivation layer 40 and is in contact with the through via TV. The lower conductive bump 46 may include at least one of copper, aluminum, nickel, and gold.

The uppermost one of the porous insulating layers 10 may be covered with a second interlayer insulating layer 13. The second interlayer insulating layer 13 may be formed of silicon oxide. Third vias 12 may be disposed in the second interlayer insulating layer 13. The third vias 12 may include copper or tungsten.

Lower pads BP are disposed on the second interlayer insulating layer 13. The lower pads BP may include first lower pads BP(R) and second lower pads BP(D). Each of the lower pads BP may also be called a ‘lower wiring’. Each of the lower pads BP may have a first thickness TH1 in a vertical direction (e.g., a direction perpendicular to an uppermost surface of the substrate 1). The first thickness TH1 may be, for example, 0.1 micrometers (μm) to 1 μm. Each of the lower pads BP may have a wider width in a lateral direction (e.g., a direction parallel to an uppermost surface of the substrate 1) as the lower pad BP goes downward in the vertical direction. A lower surface of each of the lower pads BP may have a first width WT1 in the lateral direction. A distance between the lower pads BP in the lateral direction may be the same. In another example, a distance between the first lower pads BP(R) may be different from a distance between the second lower pads BP(D). A width of the first lower pads BP(R) may be different from a width of the second lower pads BP(D).

An actual electrical signal may be applied to the first lower pads BP(R). A dummy pattern of the second lower pads BP(D) may be electrically floating. Each of the second lower pads BP(D) may be a dummy pattern, a guard ring pattern, a chipping dam pattern, or a test pattern. Each of the lower pads BP may include a first metal portion MP1 and a first anti-reflection layer AR1 that are sequentially stacked. The first metal portion MP1 may be formed of aluminum, for example. The first anti-reflection layer AR1 may be formed as a single layer or a multilayer of at least one of, for example, titanium, titanium nitride, tantalum, or tantalum nitride.

The lower pads BP and the second interlayer insulating layer 13 may be covered with a third interlayer insulating layer 20. The third interlayer insulating layer 20 may include a first silicon oxide layer 15, a hydrogen barrier layer 17, and a second silicon oxide layer 19 that are sequentially stacked. The hydrogen barrier layer 17 may be formed of, for example, silicon nitride. The first silicon oxide layer 15 may fill a space between the lower pads BP. An upper surface of the first silicon oxide layer 15 may have a concavo-convex structure. The hydrogen barrier layer 17 may have a conformal thickness. An upper surface of the hydrogen barrier layer 17 may also have a concavo-convex structure. An upper surface of the second silicon oxide layer 19 may be flat. The hydrogen barrier layer 17 may impede/prevent hydrogen from diffusing into the transistors or the memory cells, thereby improving reliability of the semiconductor chip.

A fourth interlayer insulating layer 21 is disposed on the third interlayer insulating layer 20. The fourth interlayer insulating layer 21 may have a single-layer or multi-layer structure of at least one of silicon oxide and silicon nitride. The fourth interlayer insulating layer 21 may have a flat upper surface.

An upper pad UP is disposed on the fourth interlayer insulating layer 21. The upper pad UP may have a second thickness TH2 in the vertical direction. The second thickness TH2 is greater than the first thickness TH1. The second thickness TH2 may be 2 to 5 times the first thickness TH1. The second thickness TH2 may be, for example, 2 μm to 2.5 μm.

The upper pad UP may include a conductive material. The upper pad UP may include a third metal portion MP3 and a third anti-reflection layer AR3 that are sequentially stacked. The third metal portion MP3 may be formed of aluminum, for example. The third anti-reflection layer AR3 may be formed as a single layer or a multilayer of at least one of, for example, titanium, titanium nitride, tantalum, or tantalum nitride. The upper pad UP may have a wider width as the upper pad UP goes downward.

A first via structure VST1 extends in (e.g., penetrates) the third interlayer insulating layer 20 and the fourth interlayer insulating layer 21 to electrically connect the first lower pads BP(R) to the upper pad UP. The first via structure VST1 may have a first height HE1 in the vertical direction. The first height HE1 is a vertical distance from a lowermost surface of the first via structure VST1 to an uppermost surface of the first via structure VST1. The first height HE1 may be equal to or greater than the second thickness TH2. The first height HE1 may be, for example, 1.0 μm to 10 μm. Accordingly, the upper pad UP may be spaced apart from the first lower pads BP(R) by a certain (e.g., predetermined) distance, thereby reducing parasitic capacitance between the first wirings 11 by a voltage applied to the upper pad UP and improving resistance capacitance (RC) delay characteristics.

A plurality of first via structures VST1 may be provided. Each of the first via structures VST1 may include a first via VA1, a first landing pad LP(R), and a second via VA2 that are sequentially stacked. The first via VA1 extends in (e.g., penetrates) the third interlayer insulating layer 20 and is in contact with the first lower pad BP(R). The second via VA2 extends in (e.g., penetrates) the fourth interlayer insulating layer 21 to electrically connect the first landing pad LP(R) to the upper pad UP. The second via VA2 may overlap the first landing pad LP(R) and the first via VA1 in the vertical direction. Accordingly, a vertical axis may pass through the second via VA2, the first landing pad LP(R), and the first via VA1. The first via VA1 and the second via VA2 may include tungsten. A side surface and a lower surface of each of the first via VA1 and the second via VA2 may be covered with a diffusion barrier layer.

Second landing pads LP(D) may be disposed on the third interlayer insulating layer 20 in the second region ER. The second landing pads LP(D) may also be called ‘dummy pads.’ The second landing pads LP(D) may be a dummy pattern that is not electrically connected to any first via VA1 or second via VA2 of any of the first via structures VST1. The second landing pads LP(D) may impede/prevent a loading effect to help the first landing pads LP(R) be formed accurately.

The first landing pads LP(R) and the second landing pads LP(D) may constitute pads LP. Each of the landing pads LP may have a wider width as the landing pad LP goes downward. Each of the landing pads LP may include a second metal portion MP2 and a second anti-reflection layer AR2 that are sequentially stacked. The second metal portion MP2 may be formed of aluminum, for example. The second anti-reflection layer AR2 may be formed of, for example, a single layer or a multilayer of at least one of titanium, titanium nitride, tantalum, or tantalum nitride. Each of the landing pads LP may have the same first thickness TH1 as the lower pads BP. Alternatively, a thickness of each of the landing pads LP may be greater than the first thickness TH1. A lower surface of each of the landing pads LP may have the first width WT1 in the lateral direction.

The landing pads LP may be spaced apart from each other by the same first distance DS1 in the lateral direction. That is, the first landing pads LP(R) may be spaced apart from each other by the same first distance DS1. The second landing pads LP(D) may be spaced apart from each other by the same first distance DS1. Among the first landing pads LP(R), the outermost first landing pad LP(R1) closest to the second landing pads LP(D) may be spaced apart from the outermost second landing pad LP(D1) adjacent thereto by the first distance DS1. Accordingly, the second landing pads LP(D) may be formed with the same size and spacing-distance as the first landing pads LP(R), thereby impeding/preventing loading effect. In another example, the distance between the first landing pads LP(R) may be different from the distance between the second landing pads LP(D). A width of the first landing pads LP(R) may be different from a width of the second landing pads LP(D).

The fourth interlayer insulating layer 21 and the upper pad UP may be overlapped by (e.g., covered with) an upper passivation layer 23. The upper passivation layer 23 may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, SiCN, and polyimide.

An upper conductive bump CB may penetrate the upper passivation layer 23 and may be in contact with the upper pad UP. The upper conductive bump CB may include copper. A solder layer SB is bonded on the upper conductive bump CB. The solder layer SB may include SnAg, for example.

FIGS. 2A to 2C show plan views of a landing pad and an upper pad according to embodiments of the inventive concept.

Referring to FIGS. 1 and 2A, the first landing pads LP(R) may have a shape of islands (e.g., circles) spaced apart from each other.

Referring to FIGS. 1 and 2B, the first landing pads LP(R) may be electrically connected to each other to collectively have a grid (e.g., perforated, rectangular) shape.

Alternatively, referring to FIGS. 1 and 2C, the first landing pads LP(R) may be electrically connected to each other and collectively have a plate (e.g., non-perforated, rectangular) shape.

FIG. 3 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

Referring to FIG. 3, a semiconductor chip 101 according to the present example may exclude (i.e., omit) the second landing pads LP(D) of FIG. 1. Other structures may be the same as those in FIG. 1.

FIG. 4 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

Referring to FIG. 4, in a semiconductor chip 102 according to the present example, a third interlayer insulating layer 20 may be formed of a single layer of silicon oxide (and thus may not have the hydrogen barrier layer 17 between first and second silicon oxide layers 15 and 19). A fourth interlayer insulating layer 21 may also be formed of a single layer of silicon oxide, and there is no second landing pad LP(D) of FIG. 1 formed therein. The third interlayer insulating layer 20 and the fourth interlayer insulating layer 21 may be formed of the same silicon oxide layer, and thus an interface therebetween may not be distinguished. The silicon oxide layer may have a lower dielectric constant than that of silicon nitride and the structure of FIG. 4 may be reduce parasitic capacitance between the upper pad UP and the lower pads BP, thereby improving RC delay characteristics. Other structures may be the same/similar to those of FIG. 3.

FIG. 5 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

Referring to FIG. 5, in a semiconductor chip 103 according to the present example, the first via structure VST1 may exclude (i.e., omit) the first landing pad LP(R). In the present example, the first via structure VST1 includes only the first via VA1 and the second via VA2. The first via VA1 and the second via VA2 are in contact with each other. There may be no interface between the first via VA1 and the second via VA2. The first via VA1 and the second via VA2 may be formed integrally with each other. The first via VA1 and the second via VA2 may have a width in the lateral direction that narrows downward. A portion of an upper surface of the first via VA1 may protrude in the lateral direction beyond a lower surface of the second via VA2, and may be vertically overlapped by (e.g., covered and/or in contact with) the fourth interlayer insulating layer 21. Other structures may be the same/similar to those of FIG. 3.

FIG. 6 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

Referring to FIG. 6, a semiconductor chip 104 according to the present example may further include a fifth interlayer insulating layer 25 interposed between the fourth interlayer insulating layer 21 and the upper passivation layer 23. The fifth interlayer insulating layer 25 may be formed of silicon oxide. The first via structure VST1 extends in (e.g., penetrates) the third to fifth interlayer insulating layers 20, 21, and 25. The first via structure VST1 may exclude the first landing pad LP(R). In the present example, the first via structure VST1 includes a first via VA1, a second via VA2, and a third via VA3 that are sequentially stacked. The third via VA3 extends in (e.g., penetrates) the fifth interlayer insulating layer 25. The first via VA1 and the second via VA2 are in contact with each other. The second via VA2 and the third via VA3 are in contact with each other. There may be no interface between the first via VA1 and the second via VA2. There may be no interface between the second via VA2 and the third via VA3. The first via VA1, the second via VA2, and the third via VA3 may be formed integrally with each other. The first via VA1, the second via VA2, and the third via VA3 may have a width that narrows downward. A portion of an upper surface of the first via VA1 may be vertically overlapped by (e.g., covered with) the fourth interlayer insulating layer 21. A portion of an upper surface of the second via VA2 may be vertically overlapped by (e.g., covered with) the fifth interlayer insulating layer 25. Other structures may be the same/similar to those of FIG. 3.

FIG. 7 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

Referring to FIG. 7, a semiconductor chip 105 according to the present example may further include a fifth interlayer insulating layer 25 interposed between the fourth interlayer insulating layer 21 and the upper passivation layer 23. The fifth interlayer insulating layer 25 may be formed of silicon oxide. The first via structure VST1 extends in (e.g., penetrates) the third to fifth interlayer insulating layers 20, 21, and 25. In the present example, the first via structure VST1 includes a first via VA1, a first landing pad LP(R), a second via VA2, and a third via VA3 that are sequentially stacked. The third via VA3 penetrates the fifth interlayer insulating layer 25. The second via VA2 and the third via VA3 are in contact with each other. There may be no interface between the second via VA2 and the third via VA3. The second via VA2 and the third via VA3 may be formed integrally with each other. The first via VA1, the second via VA2, and the third via VA3 may have a width that narrows downward. A portion of an upper surface of the second via VA2 may be vertically overlapped by (e.g., covered with) the fifth interlayer insulating layer 25. Other structures may be the same/similar to those of FIG. 6. In this example, the first via structure VST1 includes vias in a three-tier structure, but is not limited thereto and may include vias in four or more tiers.

In another example, the first via structure VST1 may further include a first landing pad LP(R) interposed between the second via VA2 and the third via VA3. Accordingly, the first via structure VST1 may include a first via VA1, a first landing pad LP(R), a second via VA2, a first landing pad LP(R), and a third via VA3 that are sequentially stacked. Alternatively, the first via structure VST1 may include a first via VA1, a second via VA2, a first landing pad LP(R), and a third via VA3 that are sequentially stacked.

FIG. 8 is a cross-sectional view of a semiconductor chip according to embodiments of the inventive concept.

Referring to FIG. 8, a semiconductor chip 106 according to the present example further includes first residual test patterns 11t, first residual test vias 9t, and second residual test patterns TP. The first residual test patterns 11t and the first residual test vias 9t may be disposed in the porous insulating layers 10 in the second region ER. The first residual test patterns 11t may have the same thickness and the same material as the first wirings 11. The first residual test vias 9t may have the same thickness and the same material as the first vias 9. The second residual test pattern TP may have the same first thickness TH1 as the lower pad BP. A first thickness TH1 may be smaller than a second thickness TH2 of the upper pad UP. A lower surface of the second residual test pattern TP may have a width WT2 in the lateral direction that is wider than the first width WT1 of a lower surface of the lower pad BP.

The second residual test pattern TP may include a first metal portion MP1 and a first anti-reflection layer AR1 that are sequentially stacked. The first metal portion MP1 may be formed of aluminum, for example. The first anti-reflection layer ARI may be formed of, for example, titanium nitride.

A portion of an upper surface of the second residual test pattern TP may be vertically overlapped by (e.g., covered with) a third interlayer insulating layer 20, a fourth interlayer insulating layer 21, a capping layer 22, and an upper passivation layer 23 that are sequentially stacked. Another portion of the upper surface of the second residual test pattern TP may be exposed. Sidewalls of the third interlayer insulating layer 20, the fourth interlayer insulating layer 21, the capping layer 22, and the upper passivation layer 23 may be aligned with each other. A trench 24 is formed in the porous insulating layers 10, the third interlayer insulating layer 20, and the fourth interlayer insulating layer 21 between the second residual test pattern TP and the lower pads BP.

A capping layer 22 may extend to cover an inner wall and a bottom surface of the trench 24. The capping layer 22 may extend to be interposed between the fourth interlayer insulating layer 21 and the upper passivation layer 23, and may cover side surfaces and a portion of the upper surface of the upper pad UP. The capping layer 22 may be formed of silicon oxide with a relatively higher density than that of the porous insulating layers 10. The capping layer 22 may penetrate the porous insulating layers 10 to impede/prevent physical cracks or moisture propagating from the outside of the semiconductor chip 106. A portion of the upper passivation layer 23 may be inserted into the trench 24 to fill the trench 24. Other structures may be the same/similar to those described with reference to FIG. 3.

FIG. 9A is a cross-sectional view of a semiconductor package according to embodiments of the inventive concept. FIG. 9B is an enlarged view of portion ‘P2’ of FIG. 9A.

Referring to FIGS. 1, 9A, and 9B, a semiconductor package 1000 according to the present example may include a package substrate PS, a first semiconductor chip 100, a second semiconductor chip 200, and a third semiconductor chip 300. The second semiconductor chip 200 and the third semiconductor chip 300 may be spaced apart from each other in a lateral direction, and may be on the first semiconductor chip 100. The package substrate PS may be a printed circuit board. The package substrate PS may include upper substrate pads PUP, lower substrate pads PBP, and internal substrate wirings IT electrically connecting them. External connection terminals OSB may be bonded to the lower substrate pads PBP.

The first semiconductor chip 100 may be mounted on the package substrate PS using first internal connecting members IB1. An underfill layer UF may be interposed between the package substrate PS and the first semiconductor chip 100. The first semiconductor chip 100 may also be called an ‘interposer substrate’ or an ‘interposer chip.’ The first semiconductor chip 100 may have the same structure as the semiconductor chip described with reference to FIG. 1. When portion ‘P1’ of the first semiconductor chip 100 is enlarged, the first semiconductor chip 100 may be the same as that in FIG. 1. The first semiconductor chip 100 may have the structure of the semiconductor chips described with reference to FIGS. 2A to 8 instead of the structure of FIG. 1. The first semiconductor chip 100 may include upper conductive bumps CB, lower conductive bumps 46, and through vias TV electrically connecting them. The first semiconductor chip 100 may further include an upper connection wiring CBT that electrically connects some of the upper conductive bumps CB.

The second semiconductor chip 200 and the third semiconductor chip 300 are mounted on the first semiconductor chip 100 by second internal connecting members IB2. An underfill layer UF may be interposed between the first semiconductor chip 100 and the second semiconductor chip 200 and between the first semiconductor chip 100 and the third semiconductor chip 300.

The underfill layer UF may be formed of a non-conductive film (NCF). The underfill layer UF may also be referred to as a ‘non-conductive layer.’ The underfill layer UF may independently include a thermosetting resin or a photocurable resin. Additionally, the underfill layer UF may further include an organic filler or an inorganic filler independently of each other. The organic filler may include, for example, a polymer material. The inorganic filler may include, for example, silicon oxide (SiO₂).

The second semiconductor chip 200 may be one selected from a system large scale integration (LSI) chip, a logic circuit chip, a microelectromechanical system (MEMS) device chip, or an application-specific integrated circuit (ASIC) chip. The third semiconductor chip 300 may be a high bandwidth memory (HBM) chip or a hybrid memory cubic (HMC) chip. The second semiconductor chip 200 and the third semiconductor chip 300 may be electrically connected to each other by the upper connection wiring CBT.

The third semiconductor chip 300 may include a buffer die BF and first to fourth memory dies ME1 to ME4 that are sequentially stacked. The third semiconductor chip 300 may further include a mold layer MD. For example, the mold layer MD may include an insulating resin such as epoxy-based molding compound (EMC). The mold layer MD may further include a filler, and the filler may be dispersed in the insulating resin.

Each of the first to fourth memory dies ME1 to ME4 may be, for example, a DRAM chip, SRAM chip, EEPROM chip, PRAM chip, MRAM chip, or ReRAM chip. Each of the buffer die BF and the first to fourth memory dies ME1 to ME4 may have the structure shown in FIG. 9B.

Specifically, referring to FIG. 9B, the buffer die BF and the first to fourth memory dies ME1 to ME4 may each have a structure similar to that of FIG. 1. To describe a structure different from that in FIG. 1, each of the buffer die BF and the first to fourth memory dies ME1 to ME4 excludes (i.e., omits) the fourth interlayer insulating layer 21 and includes a second via structure VST2 electrically connecting the first lower pads BP(R) and the upper pad UP.

The second via structure VST2 has a second height HE2 in the vertical direction. The second height HE2 is a vertical distance from a lowermost surface of the second via structure VST2 to an uppermost surface of the second via structure VST2. The second height HE2 may be equal to or smaller than a second thickness TH2 of the upper pad UP. The second height HE2 may be smaller than the first height HE1 of the first via structure VST1 of FIG. 1 belonging to the first semiconductor chip 100. The lower conductive bump 46 may be disposed in the lower passivation layer 40, and a lower surface of the lower conductive bump 46 may be coplanar with a lower surface of the lower passivation layer 40. An upper surface of the upper conductive bump CB may be coplanar with an upper surface of the upper passivation layer 23. Other structures may be the same/similar to those described with reference to FIG. 1.

The buffer die BF and the first to fourth memory dies ME1 to ME4 may each be bonded to each other using a Cu-to-Cu bonding manner. That is, the upper conductive bump CB of a lower one of the buffer die BF and the first to fourth memory dies ME1 to ME4 may be in contact with the lower conductive bump 46 of an upper one of the buffer die BF and the first to fourth memory dies ME1 to ME4.

In the semiconductor package 1000 according to the inventive concept, a first height HE1 of the first via structure VST1 in the first semiconductor chip 100 corresponding to the interposer chip may be 1.0 μm to 10 μm. When testing performance of the third semiconductor chip 300, which is an HBM chip, using the interposer chip, resistance capacitance (RC) delay characteristics may be improved.

A heat dissipation member HS may be disposed on the second semiconductor chip 200 and the third semiconductor chip 300. The heat dissipation member HS may be a material with excellent thermal conductivity and may include, for example, metal. A thermal boundary material layer TM may be interposed between the heat dissipation member HS and the second semiconductor chip 200 and between the heat dissipation member HS and the third semiconductor chip 300. The thermal boundary material layer TM may include a thermosetting resin layer. The thermal boundary material layer TM may further include filler particles dispersed in the thermosetting resin layer. The filler particles may include at least one of silica, alumina, zinc oxide, and nitrogen boride.

FIGS. 10A to 10G are views sequentially showing a method of manufacturing the semiconductor chip of FIG. 1.

Referring to FIG. 10A, transistors TR, first interlayer insulating layer 3, first contacts 5c, second contacts 5g, and first wirings 11, first vias 9, second wirings 11g, second vias 9g, porous insulating layers 10, through vias TV, via insulating layer TL, third vias 12 and a second interlayer insulating layer 13 are formed on a substrate 1 using a typical process. After the first metal layer and the first anti-reflection layer ARI are sequentially deposited on the second interlayer insulating layer 13, an etching process is performed to form lower pads BP.

Referring to FIG. 10B, a first silicon oxide layer 15, a hydrogen barrier layer 17, and a second silicon oxide layer 19 are sequentially deposited on the lower pads BP to form a third interlayer insulating layer 20. A chemical mechanical polishing (CMP) process is performed to flatten an upper surface of the second silicon oxide layer 19.

Referring to FIG. 10C, first via holes are formed in the third interlayer insulating layer 20. A conductive layer is deposited on the third interlayer insulating layer 20 to fill the first via holes, and an etch-back or CMP process is performed to form first vias VA1 in the third interlayer insulating layer 20.

Referring to FIG. 10D, a second metal layer and a second anti-reflection layer AR2 are sequentially deposited on the third interlayer insulating layer 20 and etched to form landing pads LP. In this case, first landing pads LP(R) and second landing pads LP(D) may be formed simultaneously. The first landing pads LP(R) may be formed without defects by reducing/minimizing loading effect by using the second landing pads LP(D).

Referring to FIG. 10E, a fourth interlayer insulating layer 21 is formed on the third interlayer insulating layer 20. An upper surface of the fourth interlayer insulating layer 21 may be planarized by performing a CMP process. Second vias VA2 are formed in the fourth interlayer insulating layer 21. As a result, first via structures VST1 may be formed.

Referring to FIG. 10F, a third metal layer and a third antireflection layer AR3 are sequentially deposited on the fourth interlayer insulating layer 21 and then etched to form an upper pad UP.

Referring to FIG. 10G, an upper passivation layer 23 is formed to cover the fourth interlayer insulating layer 21 and the upper pad UP. The upper passivation layer 23 is etched to form a hole HL exposing the upper pad UP. A conductive bump CB is formed in the hole HL and a solder layer SB is formed on the conductive bump CB.

Subsequently, referring to FIG. 1, a back grinding process is performed on a back surface of the substrate 1 to expose the through via TV. A lower passivation layer 40 and a lower conductive bump 46 are formed on the back surface of the substrate 1. Accordingly, the semiconductor chip 100 of FIG. 1 may be manufactured.

In the semiconductor chip according to embodiments of the inventive concept, the via structure electrically connecting the lower pad and the upper pad may have the height greater than the thickness of the upper pad, thereby improving the RC delay characteristics. Additionally, when testing the HBM chip using the interposer chip with the above-described structure, it may be very effective in improving the RC delay characteristics.

While example embodiments are described above, a person skilled in the art may understand that many modifications and variations can be made without departing from the scope of the inventive concept defined in the following claims. Accordingly, the example embodiments of the inventive concept should be considered in all respects as illustrative and not restrictive, with the scope of the inventive concept being indicated by the appended claims. The embodiments of FIGS. 1 to 9B may be combined with each other.

Claims

1. A semiconductor chip comprising: a substrate;a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer sequentially stacked on the substrate;lower pads on the second interlayer insulating layer and having a first thickness in a vertical direction;third and fourth interlayer insulating layers sequentially stacked on the lower pads and the second interlayer insulating layer;an upper pad on the fourth interlayer insulating layer and having a second thickness in the vertical direction greater than the first thickness; andvia structures in both the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connecting the lower pads and the upper pad,wherein each of the via structures includes a first via in the third interlayer insulating layer and a second via in the fourth interlayer insulating layer and overlapping the first via in the vertical direction.

2. The semiconductor chip of claim 1, wherein each of the via structures has a height of 1.0 micrometers (μm) to 10 μm in the vertical direction that is greater than the second thickness.

3. The semiconductor chip of claim 1, wherein each of the via structures further includes a landing pad interposed between the first via and the second via.

4. The semiconductor chip of claim 3, wherein the landing pads of the via structures are spaced apart from each other and have circular shapes, orwherein the landing pads of the via structures are electrically connected to each other to collectively have a perforated or non-perforated rectangular shape.

5. The semiconductor chip of claim 3, further comprising dummy pads on the third interlayer insulating layer and spaced apart from the landing pads, wherein the dummy pads are not electrically connected to the first via and the second via of any of the via structures.

6. The semiconductor chip of claim 5, wherein a first distance in a lateral direction between the landing pads is equal to a second distance in the lateral direction between the dummy pads.

7. The semiconductor chip of claim 6, wherein the landing pads include an outermost landing pad adjacent to the dummy pads,wherein the dummy pads include an outermost dummy pad adjacent to the outermost landing pad, andwherein a third distance in the lateral direction between the outermost landing pad and the outermost dummy pad is equal to the first distance.

8. The semiconductor chip of claim 6, wherein a first width in the lateral direction of each of the landing pads is equal to a second width in the lateral direction of each of the dummy pads.

9. The semiconductor chip of claim 1, wherein the third interlayer insulating layer includes a first silicon oxide layer, a hydrogen barrier layer, and a second silicon oxide layer that are sequentially stacked, andwherein the first via is in the first silicon oxide layer, the hydrogen barrier layer, and the second silicon oxide layer.

10. The semiconductor chip of claim 1, wherein the second via is in contact with the first via,wherein a lower width in a lateral direction of each of the first via and the second via is narrower than an upper width in the lateral direction of each of the first via and the second via,wherein a portion of an upper surface of the first via protrudes in the lateral direction beyond a lower surface of the second via, andwherein the fourth interlayer insulating layer is on the portion of the upper surface of the first via.

11. The semiconductor chip of claim 1, wherein each of the via structures further includes a third via on the second via.

12. The semiconductor chip of claim 11, wherein each of the via structures further includes a landing pad, andwherein the landing pad is between the first via and the second via, or is between the second via and the third via.

13. The semiconductor chip of claim 1, further comprising: wirings in the porous insulating layer;first residual test patterns in the porous insulating layer and spaced apart in a lateral direction from the wirings; anda second residual test pattern on the second interlayer insulating layer, electrically connected to the first residual test patterns, and spaced apart in the lateral direction from the lower pads,wherein the second residual test pattern has the first thickness, andwherein a width in the lateral direction of the second residual test pattern is greater than a width in the lateral direction of each of the lower pads.

14. The semiconductor chip of claim 13, further comprising: a capping layer on the fourth interlayer insulating layer and on side and upper surfaces of the upper pad; anda passivation layer on the capping layer,wherein a portion of the capping layer is in the fourth interlayer insulating layer, the third interlayer insulating layer, the second interlayer insulating layer, and the porous insulating layer, and is in contact with the first interlayer insulating layer.

15. The semiconductor chip of claim 14, further comprising a conductive bump that is in the passivation layer and the capping layer, and is in contact with the upper pad.

16. A semiconductor chip comprising: a substrate;a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer sequentially stacked on the substrate;a through via in the first interlayer insulating layer and the substrate;a via insulating layer interposed between the through via and the substrate;wirings in the porous insulating layer;a contact plug in the first interlayer insulating layer and in contact with one of the wirings;lower pads on the second interlayer insulating layer and having a first thickness in a vertical direction;third and fourth interlayer insulating layers sequentially stacked on the lower pads and the second interlayer insulating layer;an upper pad on the fourth interlayer insulating layer and having a second thickness in the vertical direction greater than the first thickness; andvia structures in the fourth interlayer insulating layer and the third interlayer insulating layer and electrically connecting the lower pads and the upper pad,wherein the third interlayer insulating layer includes a first silicon oxide layer, a hydrogen barrier layer, and a second silicon oxide layer that are sequentially stacked,wherein each of the via structures includes a first via that is in the third interlayer insulating layer and a second via that is in the fourth interlayer insulating layer and overlaps the first via in the vertical direction, andwherein each of the via structures has a height in the vertical direction of 1.0 micrometers (μm) to 10 μm.

17. A semiconductor package comprising: a package substrate;a first semiconductor chip on the package substrate; anda second semiconductor chip and a third semiconductor chip on the first semiconductor chip, wherein the second semiconductor chip and the third semiconductor chip are spaced apart from each other in a lateral direction,wherein the third semiconductor chip includes a buffer die and memory dies sequentially stacked,wherein the first semiconductor chip and the memory dies each include:a substrate;a first interlayer insulating layer, a porous insulating layer, and a second interlayer insulating layer sequentially stacked on the substrate;lower pads on the second interlayer insulating layer and having a first thickness in a vertical direction;a third interlayer insulating layer on the lower pads and the second interlayer insulating layer;an upper pad on the third interlayer insulating layer and having a second thickness in the vertical direction greater than the first thickness; andvia structures electrically connecting the lower pads and the upper pad through the third interlayer insulating layer,wherein each of the via structures of the first semiconductor chip has a first height in the vertical direction, andwherein each of the via structures of the memory dies has a second height in the vertical direction that is smaller than the first height.

18. The semiconductor package of claim 17, wherein the first height is 1.0 micrometers (μm) to 10 μm.

19. The semiconductor package of claim 17, wherein each of the via structures of the first semiconductor chip includes a first via and a second via sequentially stacked.

20. The semiconductor package of claim 19, wherein each of the via structures of the first semiconductor chip further includes a landing pad between the first via and the second via.