This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2018-033567, filed on Feb. 27, 2018, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor device and dicing method.
Power devices formed on a silicon substrate undergo dicing after a pre-process, and the power device is packaged with its rear surface being connected using solder, eutectic metal or metal, or conductive resin or nonconductive resin. The metal or the like on the rear surface plays a role of electric connection, barrier metal for a connection material, a connection material, heat dissipation, or the like. Peeling of the metal or the like on the rear surface leads to an open failure to deteriorate electric properties. Further, a large crack in the metal or the like on the rear surface becomes a chip crack (fissure-shaped damage in a chip) when the metal or the like undergoes heat cycle, drop impact, mounting impact, or the like, and may lead to defective properties. In a case where a die attach film of nonconductive resin is used, the peeling of the rear surface or the presence of a large crack in the rear surface lowers the stability of die bonding. Therefore, avoiding a defect of the metal or the like on the rear surface caused by the cutting is an important thing leading to an improvement in reliability.
According to an embodiment, a semiconductor device includes a silicon substrate, device layer, and a lower layer. The device layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.
An embodiment of the present invention will be hereinafter described with reference to the drawings. This embodiment does not limit the present invention. Note that, though the description in this embodiment uses up and down relations such as an upper side, a lower side, an upper surface, and a lower surface, these up and down relations are determined for convenience' sake and do not necessarily indicate up and down relations in terms of the gravitational direction during the manufacture, during the use, and so on. Further, the expression “having a curvature” does not necessarily mean that a portion in question constitutes part of the circumference, but is used to mean that a portion in question has a curved shape.
Further, “vertical” does not necessarily mean strictly vertical, and for example, may include “substantially vertical” like the side surface of the semiconductor device 1 illustrated in
The semiconductor device according to this embodiment has a device layer, a metal layer, and so on formed in its front surface by a semiconductor pre-process. After the completion of the pre-process, a rear surface of a silicon substrate is thinned using a back grinder, and by subsequent chemical polishing of the rear surface, fractured surfaces and/or adherent matter caused by the back grinding are removed, and thereafter rear metal is formed using a sputtering device, and the resultant is blade-diced into chips. Thereafter, the chip is encapsulated in a package using a die bonder.
First, as illustrated in
Next, as illustrated in
Thereafter, the lower surface 10b of the silicon substrate 10 is further lightly etched using a HF (hydrogen fluoride)-based chemical. The etching used is not limited to the etching using a chemical solution, but may be dry etching using gas. Alternatively, the light etching may be replaced by a step of removing only a necessary amount of a fractured surface of the rear surface by grinding or polishing.
Next, as illustrated in
The metal may be formed by, for example, depositing Ti (titanium) and thereafter forming a Ni (nickel) film and an Au (gold) film so as to cover Ti. The metal of the metal layer 14 is not limited to Ti, but may be any metal as long as it can be the rear metal, and another example of the metal layer 14 is a metal film containing at least one of Ti, Cu (copper), Zn (zinc), Pd (palladium), Ni, Ag (silver), and Au.
Next, as illustrated in
As the dicing blade 30, one having a blade portion 32 suitable both for cutting metal and for cutting silicon is used. In the dicing, the blade portion 32 cuts the metal layer 14 and the silicon. As described above, in this cutting, the upper surface 16a of the dicing tape 16 is also superficially cut.
As illustrated in
A side surface of the blade portion 32 of the dicing blade 30 has such a curvature as to depict a curve from the middle of the height of the silicon substrate 10. This curvature is smooth as illustrated in
In the dicing blade 30, the blade portion 32 has diamond particles selected so as to be suitable both for cutting the metal and for cutting the silicon substrate 10, for instance.
As another example, instead of the dicing blade 30 being used so as to reach the middle of the dicing tape 16 as in the typical method, by adjusting the height of the dicing blade 30 so that up to the lower surface 14b of the metal layer 14 is cut and the vicinity of the upper surface of the dicing tape 16 is cut by the edge of the blade portion 32, it is possible for the lower portion of the semiconductor device 1 to have a curvature as illustrated in
As described above, in this embodiment, the dicing may be single-cut dicing that achieves the cutting up to the metal layer 14 and the transfer of the curvature that the side surface of the blade portion 32 has to the curvature of the side surface of the semiconductor device 1.
The semiconductor device 1 in
In the formed semiconductor device 1, the length of the lower surface 14b of the metal layer 14 is longer than the length of the upper surface 12a of the device layer 12 in the sectional view. Three-dimensionally speaking, for example, the chip is rectangular and is formed so as to have a larger area in the lower surface 14b of the metal layer 14 than in the upper surface 12a of the device layer 12. Further, in the formed semiconductor device 1, the length of each side of the lower surface 14b of the metal layer 14 is longer than the length of a corresponding side of the upper surface 12a of the device layer 12.
Thus making the lower surface larger in area than the upper surface makes it possible to keep a sufficient distance between chip front surfaces (that is, the upper surfaces 12a) in such a case where they are transported in a side-by-side arrangement after the dicing, to thereby reduce a possibility of the mutual contact of the front surfaces of the chips. Accordingly, the chips are unlikely to get chipped or surface chipping is unlikely to occur, due to the collision of the chips, leading to a quality improvement of the chips. As a result, it is possible to reduce a bonding failure or to prevent a decrease in flexural strength.
What chipping means here is that a surface is superficially cracked, has a fissure, or gets chipped. The chipping deteriorates the performance of the semiconductor device 1 when it is transported, processed, or used.
Further, owing to the presence of the curvature as illustrated in
However, if a length by which the lower surface 14b of the metal layer 14 is longer than the upper surface 12a of the device layer 12 is over about 25% of the thickness of the semiconductor device 1, the area necessary as the chip becomes large and the curvature of the side surface becomes gentle, and moreover, the dicing blade 30 comes to have an unusual shape, which is not preferable. More preferably, the length by which the lower surface 14b of the metal layer 14 protrudes from the upper surface 12a of the device layer 12 is desirably about 5% to about 25% of the thickness of the semiconductor device 1.
As described above, according to this embodiment, the semiconductor device 1 has a shape whose side surface has the curvature from the upper surface toward the lower surface and which has a larger area in the lower surface than in the upper surface, making it possible to improve the die-bonding strength while reducing the leakage current. Further, since the distance to the front surface is long, a short circuit on the side surface is unlikely to occur. Preventing the short circuit between the metal layer 14 and the side surface also makes it possible to prevent the short circuit between the metal layer 14 and the front surface such as a wiring layer of the semiconductor device 1 and the short circuit between the side surface and the front surface of the semiconductor device 1. In addition, since it is possible to keep the distance between the chip front surfaces long, the collision of the chips is unlikely to occur during the transport after the dicing, making it possible to improve the qualities of the chips.
In many cases, typically, silicon and metal are separately cut, but in this embodiment, one dicing blade is used for the cutting. This as a result can increase the throughput in the dicing step. Dual cutting enables a further increase in this throughput.
Incidentally, in the above, the lower layer of the semiconductor device 1 is the metal layer 14, but may be a die attach film. The die attach film may be a conductive die attach film, for instance. Forming the semiconductor device 1 using the die attach film enables stacking without processing the semiconductor device 1 when the semiconductor package is manufactured by the stacking.
In the above-described embodiment, the dicing is the single-cut dicing, but is not limited to this and may be step-cut dicing
Specifically, in this modification example, a dicing blade for cutting the silicon substrate 10 and a dicing blade for cutting the metal layer 14 are separately prepared, and these layers are cut using the dicing blades more suitable for the respective layers. That is, the silicon substrate 10 may be cut by a blade portion 32 of a dicing blade 30 for cutting silicon, and the metal layer 14 may be cut by a blade portion 32 of a dicing blade 30 for cutting metal.
After the first cutting is finished, second cutting is performed to the metal layer 14 exposed to a first cut surface, using a second dicing blade narrower in blade width than the first dicing blade, so as to cut up to the lower surface 14b of the metal layer 14. The second cutting may superficially cut the upper surface 16a of the dicing tape 16 as in the above-described embodiment.
In the first cutting, the cutting is performed so as to cause a side surface 20c to have a curvature as in the semiconductor device 1 according to the above-described embodiment. This is because up to the silicon substrate 10 is cut into the same sectional shape as that of the dicing blade. In the subsequent second cutting, the metal layer 14 is cut vertically. Alternatively, in this modification example as well, the cutting is performed so as to cause an exposed side surface 20d to have a cross section having a curvature as in the above-described embodiment, as illustrated in
As described above, according to these modification examples, owing to the curvature that the side surface 20c has, the lower surface 14b is larger in area than the upper surface 12a, and in a case where the chip shape, that is, the shape of the semiconductor device 1 is rectangular, the length of each side of the lower surface 14b is longer than the length of the corresponding side of the upper surface 12a, as in the semiconductor device 1 according to the above-described embodiment. This difference in length makes it possible to reduce the collision of the upper surfaces 12 of the semiconductor devices 1. The step cutting permits the selection of the blades for metal and for silicon, leading to a further quality improvement, compared with the aforesaid single cutting.
Specifically, since the blades for cutting the silicon substrate 10 and for cutting the metal layer 14 are different, the chipping of the front surface and the side surface of the silicon substrate 10 and the rear chipping in the lower surface 14b of the metal layer 14 are prevented in the dicing step, leading to an improvement in deflective strength and making it possible to improve a yield of the chips. Further, even if a crack such as a fissure occurs in the lower portion of the silicon substrate 10, since the lower surface 10b of the silicon substrate 10 suffering the chipping physically connects to the upper surface 14a of the metal layer 14 and the portion suffering the chipping is fixed to the metal layer 14 on at least its lower surface, the portion suffering the chipping does not easily peel off, making it possible to prevent the generation of dust in a post-process.
Further, in the case where the side surface 20d is vertical, in the side surface 20d, an effect on a bonding agent such as the solder or the die bonding resin is the same as the conventional effect, but owing to the curvature that the side surface 20c has, a force pressing a side of the side surface 20c from above is applied from the bonding agent as in the above-described embodiment, making it possible to obtain the same effects. In a case where the bonding agent is a conductive bonding agent such as solder, it is also possible to further reduce the leakage of a current in the side surface or the front surface as in the above-described embodiment
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
For example, in cutting out the semiconductor device 1 as a chip, the board is cut in directions intersecting with each other, and the cutting in one of the directions may be the single cutting, and the cutting in the other direction may be the step cutting. The cutting in the both directions may of course be the single cutting or the step cutting. Further, out of the two pairs of opposed side surfaces, only one pair of the side surfaces may have a curvature as described above.
Further, the silicon substrate 10 of the semiconductor device 1 may be replaced by a different substrate. For example, when the substrate is a substrate using gallium nitride (GaN), silicon carbide (SiC), or the like, the dicing method according to the above-described embodiment can also bring about the same effects as are obtained in the above-described semiconductor device 1.
Further, the semiconductor device 1 may be formed such that its side surface has a curvature from the middle of the metal layer 14 as illustrated in
The shape of the above-described semiconductor device 1 can be found through the observation of the cross section of the chip or the observation of its side surface using a microscope or the like, for instance.
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2018-033567 | Feb 2018 | JP | national |
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