Patent Application
20090166750
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2007-330333 filed on Dec. 21, 2007, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device, such as a CMOS-FET (Complementary Metal Oxide Semiconductor Field Effect Transistor) and the manufacturing method thereof.
In recent years, with needs of further miniaturization and higher functionality of electronic devices, for example, enhancement of carrier mobility has been studied to increase a driving force in a CMOS-FET for configuring a SRAM (Static Random Access Memory) cell.
It has been known that the carrier mobility depends upon a wafer plane orientation or an axial direction to be used or stress such as lattice strain, and the direction of the enhancement or degradation thereof is different between an n-type MOS-FET with an electron as a carrier and a p-type MOS-FET with a hole as a carrier. For example, if a <110> axial direction of a Si wafer (100) face is taken as a channel longitudinal direction, tensile stress is applied for an N-type MOS-FET and compressive stress is applied for a P-type MOS-FET, in the channel longitudinal direction (X-direction) and a direction (Z-direction) perpendicular to a wafer face, respectively. In a channel width direction (Y-direction), tensile stress is applied to each thereof. Application of such stress can enhance carrier mobility.
As an approach to each stress application, there have been proposed an approach to applying tensile stress by forming an SiN film having tensile stress at an isolation part of STI (Shallow Trench Isolation), an approach to applying compressive stress by epitaxially growing a SiGe layer having a higher lattice constant than Si and an approach to forming an insulation film having tensile stress or compressive stress on an electrode.
There has been also used an approach to applying stress suitable to respective elements by individually preparing the respective elements one by one, as disclosed in Japanese Patent Application Laid-Open No. 11-340337 and Japanese Patent Application Laid-Open No. 2006-165335. However, necessity of the individual preparation process causes inconveniences such as an increasing of the number of processes and affects on peripheral processes.
According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor wafer; a source region and a drain region formed within the semiconductor wafer; a gate electrode formed on the semiconductor wafer between the source region and the drain region; an interlayer film formed on the semiconductor wafer and the gate electrode; and a dummy floating pattern embedded into the interlayer film, the dummy floating pattern having a film containing metal or a metallic compound having tensile stress or compressive stress, and the dummy floating pattern formed to be spaced from the semiconductor wafer and the gate electrode.
According to an aspect of the present invention, there is provided a manufacturing method of a semiconductor comprising: forming a gate electrode on a semiconductor wafer; forming an active area within the semiconductor wafer; forming an interlayer film on the active area and the gate electrode; forming a first opening portion reaching the semiconductor wafer or the gate electrode and a second opening portion to be spaced from the semiconductor wafer and the gate electrode in the interlayer film; embedding a first film including metal or a metallic compound into the first opening portion and forming a via contact; and embedding a second film including metal or a metallic compound same as or different from the metal or the metallic compound of the first film into the second opening portion, and forming a dummy floating pattern having tensile stress or compressive stress.
Reference will now be made in detail to the present embodiment of the invention, an example of which is illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawing to refer to the same or like parts.
Respective regions which have been subjected to element separation are formed with an active area having a source region 12a, a drain region 13a and LDDs (Lightly Doped Drain) 12b, 13b, spaced from each other. On surfaces of the source region 12a and the drain region 13a, there are formed silicide layers 14, 15 containing Ni or the like, respectively. On a region between the source region 12a and the drain region 13a, there is formed a gate electrode 16 containing a poly-silicon layer 16b and a silicide layer 16c formed through the gate insulation film 16a. In the gate electrode 16, there are formed gate side walls containing insulation films 17a containing TEOS (tetraethoxysilane) or the like and LP-SIN films 17b.
On these upper layers, there is formed an interlayer film 18 containing, for example, an SiN film 18a, a P-SiN film 18b and a TEOS film 18c, tensile stress is provided by the SiN film 18a. To penetrate through the interlayer film 18, there are formed a via contact 19 reaching the gate electrode 16 and via contacts 20, 21 reaching the silicide layers 14, 15, respectively. Between the via contact 19 and the via contacts 20, 21, there is formed dummy floating patterns 22 spaced from the active area.
The via contacts 19, 20, 21 and the dummy floating patterns 22 are constructed from a barrier metal film containing titanium and a metal film containing tungsten or the like, respectively. Tensile stress is provided by the dummy floating patterns 22.
Further, on the via contacts 19, 20, 21, there is formed a wiring 24 containing a barrier metal film 24a containing Ti or the like and a Cu film 24b, which are separated by an interlayer film 23.
The semiconductor device described above is formed as stated below. As illustrated in
Using LPCVD method, an SiN film serving as the SiN film 11a is formed, for example, 20 nm, an insulation film such as a TEOS film serving as the isolation film 11b is deposited over the whole surface thereof to embed the STI trench. The embedded trench is etched back to a determined depth, so that a part of the SiN film 11a is exposed and the exposed portion is removed by etching.
An insulation film such as a TEOS film serving as the isolation film 11c is deposited over the whole surface. With the SiN film as a stopper film, a surface thereof is flattened using CMP (Chemical mechanical polishing) method.
The insulation film 11c is then etched by, for example, 100 nm so that the top face thereof matches a predetermined height from the surface of the wafer w. All the SiN film on the surface of the wafer w is removed by etching to be formed STI 11.
As illustrated in
On the wafer w, an insulation film serving as the gate insulation film 16a is formed, for example, 1 nm. Using a LPCVD method, poly-silicon serving as the poly-silicon layer 16b constituting the gate electrode 16 is formed, for example, 150 nm.
A resist film is applied onto poly-silicon and a resist pattern is formed using the lithographic technique. With the resist pattern as a mask, poly-silicon is etched using the RIE method. By removing the resist pattern, the poly-silicon layer 16b constituting the gate electrode 16 is formed. All the exposed insulation film is removed by wet-etching to be formed the gate electrode 16.
As illustrated in
Impurity is injected into the gate electrode 16 and well and channel and diffusion regions. When heat treatment is performed, for example, at a temperature of at least 1,000° C., the source region 12a, the drain region 13a and LDDs 12b, 13b are formed. Using the salicide method, the silicide layers 14, 15, 16c are selectively formed on surfaces of the source region 12a, the drain region 13a and the poly-silicon layer 16b, respectively.
As illustrated in
A resist film is applied onto the insulation film 18c and a resist pattern is formed using the lithographic technique. As shown in
The resist pattern is removed, there are formed contact holes 19′, 20′, 21′ and a dummy floating hole 22′, which are opening portions. The dummy floating holes 22′, the short side of which is formed in a dimension of the processing limit or less, is etch-stopped midway of the insulation film 18b without reaching the active area.
As illustrated in
By removing the metal film and the barrier metal film on the insulation film 18c using the CMP method, the via contacts 19, 20, 21 reaching the silicide layers 14, 15, 16c respectively and the dummy floating patterns 22 spaced from the active area are formed in the via contact holes 19′, 20′, 21′ and the dummy floating hole 22′. The barrier metal films 22a and the metal films 22b in the dummy floating patterns 22 have tensile stress.
On the insulation film 18c and the via contacts 19, 20, 21 and the dummy floating patterns 22, there is formed an insulation film serving as the interlayer film 23, for example, 200 nm, using a plasma CVD method. A resist film is applied onto the insulation film and a resist pattern is formed using the lithographic technique. With the resist pattern as mask, the insulation film is etched using RIE method. The resist pattern is removed and an interlayer film 23 and the trench are formed.
A barrier metal film containing titanium or the like serving as the barrier metal film 24a is formed. On the barrier metal film, a Cu film 24b is formed on the barrier metal film using a plating method to embed the trench. By removing the Cu film and the barrier metal film on the insulation film 18c using the CMP method, a wiring 24 including the barrier metal film 24a and the Cu film 24b is formed in the trench.
A semiconductor device as illustrated in
By forming a dummy floating pattern having tensile stress near the gate electrode in this way, tensile stress can be applied to the proximity of the gate electrode. By applying tensile stress, carrier mobility can be improved, which leads to improvement of a driving force of a semiconductor device such as a CMOS-FET.
In the present embodiment, the dummy floating pattern 22 is disposed between the via contact 19 and the via contacts 20, 21, respectively, but it is sufficient to dispose the dummy floating pattern so as to effectively apply stress to the proximity of the gate electrode and a shape of the dummy floating pattern is not particularly limited. For example, as illustrated in
The dummy floating pattern may be of a trench shape. For example, as illustrated in
The dummy floating pattern always does not need to be formed on a surface on which the active area is formed. For example, as illustrated in
In the present embodiment, as a film for internal dummy floating pattern which applies tensile stress, a titanium film and a tungsten film was used, but is not limited to the titanium film and tungsten film. For example, in addition to the titanium film and the tungsten film, titanium oxide film, titanium nitride film, tantalum film, tantalum oxide film, tantalum nitride film, aluminum film and Cu film may be used in a single layer or laminated layer.
In the present embodiment, tensile stress was applied by the dummy floating pattern, but compressive stress may be applied by the dummy floating pattern. By the dummy floating pattern, either stress of tension or compression is applied, depending upon material, film thickness, layer configuration and formation process. Accordingly, by using, for example, a Cu film as a film of the internal dummy floating pattern, or by changing, as needed, the film thickness, layer configuration or formation process of the above-described titanium film, tungsten film, titanium oxide film, titanium nitride film, tantalum film, tantalum oxide film, tantalum nitride film or aluminum film, compressive stress can be applied to the proximity of a gate electrode, or stress can be relieved.
For example, in C-MOSFET, by applying tensile stress to an n-type active device region and compressive stress to a p-type active device region in the above way, respectively, carrier mobility can be improved in each of the regions. As described above, because the stress to be applied depends upon a plane direction of the wafer, the dummy floating pattern can be formed so that either stress of tensile stress or compressive stress is applied in a direction suitable to the plane direction as needed.
In the present embodiment, a dummy floating hole is formed concurrently with the via contact with the film of the internal dummy floating hole having the same configuration as the via contact. This does not always need the same configuration or concurrent formation. However, concurrent formation allows providing stress to the proximity of the gate electrode without increasing the number of processes.
In the present embodiment, because the dummy floating hole and the via contact are concurrently formed, as illustrated in
For the dummy floating hole not to reach the active area, preferably, a ratio (a/b) of a short side of the dummy floating pattern to a film thickness of the interlayer film is 1/6 or less. In view of variations in process, more preferably, the ratio is 1/7.5 or less. On the other hand, too large ratio causes the dummy floating hole to be too shallow, making it difficult to effectively apply stress to the proximity of the gate electrode. Preferably, the rate is 1/10 or more.
An approach to concurrent formation of the dummy floating pattern and the via contact is not limited to defining the dimensional ratio of a short side of the dummy floating pattern. Use of a multi-tone mask such as graytone and halftone enables such a control as to obtain a depth different from that of the via contact hole. Other various types of approaches to changing an etching depth are available.
Preferably, the dummy floating pattern is formed up to as close proximity of the gate electrode as possible in order to apply stress to the proximity of the gate electrode. However, stress is released upon reaching the gate electrode or the active area, and therefore, the depth is required not so deep as to reach. In view of an alignment error in a process, a bottom portion of the dummy floating pattern can be located so as to obtain, for example, a position from 1.3 times to 2.2 times as large as a height of the gate electrode. Preferably, the position is from 1.5 times to 2.0 as large as the height of the gate electrode. The bottom portion may be formed up to a position lower than a height of the gate electrode.
In the present embodiment, the interlayer film is formed on the dummy floating pattern and is in a non-conductive state relative to an upper layer wiring (multi-layer wiring), but may be connected with the upper layer wiring (multi-layer wiring). This is because there is found no electrical failure without any adverse effect upon stress application to the proximity of the gate electrode whether the wiring is in a conductive state or not. Accordingly, arrangement of the upper layer wiring can be determined as necessary without being affected by arrangement of the dummy floating pattern.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-330333 | Dec 2007 | JP | national |
