Patent Application
20250105176
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-156365, filed on Sep. 21, 2023; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor device and a method of manufacturing a semiconductor device.
In manufacturing a semiconductor device, a metal layer being a thick film may be formed using electrolytic plating or the like at the final stage of a back-end-of-line process. The metal layer being a thick film is available as a re-distribution layer to change a wiring drawn position for a lower layer, or as an electrode pad to which a bonding wire or the like is connectable.
A semiconductor device according to an embodiment includes a transistor, and a plurality of metal layers that is respectively arranged in a plurality of layers stacked above the transistor, in which the plurality of metal layers includes a first metal layer that is arranged in a lowermost layer of the plurality of layers, a second metal layer that is arranged in an uppermost layer of the plurality of layers and that is thicker than the first metal layer, and a third metal layer that is arranged in the uppermost layer and that is thicker than the second metal layer.
The present invention will be described in detail below with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, component elements in the following embodiments include component elements that are readily conceivable by a person skilled in the art or that are substantially identical.
Hereinafter, a first embodiment will be described in detail with reference to the drawings.
The semiconductor substrate 10 is a silicon substrate or the like.
The plurality of transistors TR is provided, for example, on the semiconductor substrate 10. These transistors TR are a field-effect transistor (FET) or the like, and may be configured as, for example, a double-diffused metal-oxide-semiconductor FET (DMOS FET) or the like.
These transistors TR are covered with an insulating layer 20 such as a silicon oxide layer. In the insulating layer 20, contacts 21 and wiring layers 22 that are connected to these transistors TR are arranged. At least part of the insulating layer 20 and at least the wiring layers 22 of the contacts 21 and the wiring layers 22 belong to the layer M0 above the transistors TR. Each of the contacts 21 and the wiring layers 22 is a metal layer that includes, for example, a tungsten layer or the like.
The plurality of layers M0 to M4, R0, and R1 and the like including the layer M0 in the lowermost layer is provided above the transistors TR in this order, and includes the plurality of vias 31, 33, 41, 43, and VA, a plurality of wiring layers 22, 32, 34, 42, 44, WA, and WB, and the like. Design rules in these layers M0 to M4, R0, and R1 are gradually increased from the lower layer side closer to the transistors TR toward the upper layer side. In an example, the contact 21 directly connected to each of the transistors TR, the vias 31, 33, 41, 43, and VA and the like in the upper layers increase toward the upper layers in diameter, length in the extending direction, pitch, and the like, and the wiring layers 22, 32, 34, 42, 44, WA, and WB and the like increase toward the upper layers in width, thickness, pitch, and the like.
The layers M1 and M2 are provided in this order above the layer M0 in the lowermost layer. The layer M1 is provided with the via 31 and the wiring layer 32 that are connected to each wiring layer 22 or the like in the layer M0, and an insulating layer 30a that includes the via 31, the wiring layer 32, and the like. Similarly, the layer M2 is provided with the via 33 and the wiring layer 34 that are connected to the wiring layer 32 or the like in the layer M1, and an insulating layer 30b that includes the via 33 and the wiring layer 34.
The insulating layers 30a and 30b are each, for example, a silicon oxide layer or the like. Hereinafter, these insulating layers 30a and 30b are collectively referred to as insulating layers 30 or the like in some cases. The vias 31 and 33, the wiring layers 32 and 34, and the like are each a metal layer that includes, for example, a Cu layer or the like. Furthermore, the vias 31 and 33, the wiring layers 32 and 34, and the like electrically connect, for example, the plurality of transistors TR to each other, and are also referred to as local inter-connect or the like.
The layers M3 and M4 are provided in this order above the layer M2. The layer M3 is provided with the via 41 and the wiring layer 42 that are connected to the wiring layer 34 or the like in the layer M2, and an insulating layer 40a that includes the via 41 and the wiring layer 42, and the layer M4 is provided with the via 43 and the wiring layer 44 that are connected to the wiring layer 42 or the like in the layer M3, and an insulating layer 40b that includes the via 43 and the wiring layer 44.
The insulating layers 40a and 40b are each, for example, a silicon oxide layer or the like. The vias 41 and 43, the wiring layers 42 and 44, and the like are each a metal layer that includes, for example, a Cu layer or the like. Furthermore, the vias 41 and 43, the wiring layers 42 and 44, and the like electrically connect, for example, circuits including the plurality of transistors TR, and are also referred to as global inter-connect or the like.
The layers R0 and R1 are provided in this order above the layer M4. The layer R0 is provided with the vias VA each connected to the wiring layer 44 or the like in the layer M4, and an insulating layer 40c that includes the vias VA and the like. The layer R1 of the plurality of layers M0 to M4, R0, and R1 and the like is the uppermost layer, and the layer R1 is provided with a wiring layer WA and a wiring layer WB thicker than the wiring layer WA that are connected to the vias VA in the layer R0, and an insulating layer 50 that includes the wiring layers WA and WB and the like. The insulating layer 50 has an opening portion, and an upper surface of the wiring layer WB is exposed from the opening portion.
The insulating layer 40c is, for example, a silicon oxide layer or the like. Hereinafter, the insulating layers 40a to 40c are collectively referred to as insulating layers 40 or the like in some cases. The insulating layer 50 is, for example, a polyimide layer or the like.
The vias VA, the wiring layers WA and WB, and the like are each a metal layer that includes, for example, a Cu layer or the like. Furthermore, the via VA, the wiring layers WA and WB, and the like are also referred to as a re-distribution layer (RDL) formed using, for example, a re-distribution layer forming technology, as described later.
However, in the semiconductor device 1 of the first embodiment, the wiring layer WB of the wiring layers WA and WB functions as an electrode pad connectable to an external device or the like. Meanwhile, the wiring layer WA functions as a so-called re-distribution layer in a narrow sense to change a wiring drawn position for the wiring layer 44 or the like in the layer M4 therebelow.
Note that the configuration of the semiconductor device 1 illustrated in
Furthermore, in the example illustrated in
As illustrated in
On the insulating layer 40, the insulating layer 50 is arranged to be configured in the uppermost layer of the semiconductor device 1 and to have an opening portion 50p. Each of the plurality of the vias VA is connected to any of the wiring layers WA and WB included in the insulating layer 50.
More specifically, the wiring layers WA and WB are arranged on the insulating layer 40 belonging to the layers M4 and R0 below the layer R1 to which the wiring layers WA and WB belong. The wiring layer WA as the second metal layer is entirely buried in the insulating layer 50, and the wiring layer WB as the third metal layer has an upper surface, at least part of which is exposed from the opening portion 50p in the insulating layer 50. The insulating layer 50 may have an upper surface having bumps thereon along the unevenness of the wiring layers WA and WB.
Furthermore, the wiring layer WA may be configured to be thicker than at least the wiring layer 22 (see
For example, even when a process node is reduced to 130 nm, 90 nm, 65 nm, and 40 nm, the wiring layer WA can have a thickness of approximately 5 μm, and the wiring layer WB can have a thickness of 10 μm or more. Note that, for example, when the process node is 130 nm, it means that the transistor IR has a gate length of 130 nm.
As described above, even when the process node is gradually reduced, the thicknesses of the wiring layers WA and WB may be maintained at approximately 5 μm and 10 μm or more, respectively. This is because, since the wiring layers WA and WB are each formed using the re-distribution layer forming technology different from that for the wiring layers 22, 32, 34, 42, and 44 and the like in the layers M0 to M4 therebelow, as described later, approximately 5 μm that is the thickness of the wiring layer WA is closer to a minimum feature size. In addition, this is because, since the wiring layer WB is required to have a predetermined strength, as described later, it is preferable to maintain a thickness of 10 μm or more.
Meanwhile, as the process node is reduced to 130 nm, 90 nm, 65 nm, and 40 nm, the thickness of each wiring layer 22 in the layer M0 as the lowermost layer is gradually reduced, but the wiring layer WB has a thickness of 10 μm or more, that is, the wiring layer WB has a thickness that is, for example, 50 to 77 times the thickness of the wiring layer 22. In this way, the wiring layer WB may have a thickness, for example, 40 times or more, and more preferably, 40 times or more and 80 times or less the thickness of the wiring layer 22.
The wiring layers WA and WB and the vias VA connected to the wiring layers WA and WB each include a plating layer 52 as a first layer and a barrier metal layer 51 as a second layer.
The plating layer 52 is, for example, a Cu layer or the like that is formed by electrolytic plating or the like using a seed layer, which is not illustrated, as an electrode provided on the barrier metal layer 51, and corresponds to a core material of the via VA and a main body portion of the wiring layer WA. The plating layer 52 is continuously provided over the vias VA and the wiring layer WA.
The barrier metal layer 51 is a layer that includes a metal different from the metal of the plating layer 52, such as a Ti layer or a TiW layer, and is provided on lower surfaces of the wiring layers WA and WB, excluding portions to which the vias VA are connected, and a side surface and bottom surface of each via VA. The barrier metal layer 51 is continuously provided from the lower surfaces of the wiring layers WA and WB to the side surface and bottom surface of each via VA. This configuration makes it possible for the barrier metal layer 51 to suppress diffusion of the barrier metal layer 51 and the plating layer 52, which are the Cu layer and the like, in the insulating layer 40 and the like. Note that the barrier metal layer 51 is processed by, for example, wet etching or the like as described later, and therefore, the barrier metal layer 51 may have a side etched shape having a width smaller than that of the portion of the plating layer 52 on the wiring layers WA and WB.
Note that, as described above, the seed layer, which is not illustrated, is arranged between the barrier metal layer 51 and the plating layer 52. In other words, the seed layer is provided on the lower surfaces of the wiring layers WA and WB, excluding portions to which the vias VA are connected, the side surface and bottom surface of each via VA, and on the inner side of the barrier metal layer 51. The seed layer is, for example, a Cu layer or the like similarly to the plating layer 52, and serves as an electrode when the plating layer 52, which is the Cu layer or the like, is formed by the electrolytic plating.
In addition, the wiring layer WB further includes a coating layer 53 as a third layer, on a surface of the plating layer 52 exposed from the opening portion 50p of the insulating layer 50. The coating layer 53 includes a metal different from the metal of the plating layer 52, and is, for example, a NiPd layer, NiAu layer, NiPdAu layer, Au layer, or the like. The coating layer 53 has an outer edge portion that is covered and protected by the insulating layer 50.
The upper surface of the wiring layer WB including the coating layer 53 may not have a flat shape but may have a round shape with an outer edge portion rounded. The outer edge portion of the coating layer 53 may protrude from an outer edge portion of the plating layer 52. Even when the coating layer 53 has such a shape, the wiring layer WB having the round shape alleviates concentration of stress of the insulating layer 50 protecting the outer edge portion of the wiring layer WB, at an end portion of the wiring layer WB, suppressing removal of the insulating layer 50.
The wiring layer WB functions as, for example, the electrode pad of the semiconductor device 1 connected to the external device. Providing the coating layer 53 on the upper surface of the wiring layer WB, as described above, makes it possible, for example, to connect a bonding wire to the wiring layer WB, using the coating layer 53 as a bonding layer.
Meanwhile, as described above, the wiring layer WA functions as the re-distribution layer to change the wiring drawn position for the wiring layer 44 and the like therebelow. The wiring layer WA is configured to be thinner than the wiring layer WB, and therefore, the design rule finer than that of the wiring layer WB is applicable. In other words, in addition to the thickness of the wiring layer WA, the width, pitch, and the like of the wiring layer WA may be configured finer than those of the wiring layer WB.
When the plating layer 52 on the wiring layers WA and WB have the Cu layers, Cu is an example of a first metal. Furthermore, when the coating layer 53 of the wiring layer WB is a NiPd layer, NiAu layer, NiPdAu layer, Au layer, or the like, these metals used for the coating layer 53 are an example of a second metal.
Next, a method of manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to
Note that
In other words, referring to
The process having been described above is also referred to as, for example, a front-end-of-line (FEOL) process or the like. On the other hand, a subsequent process is also referred to as a back-end-of-line (BEOL) process or the like.
In the back-end-of-line process, when various configurations are formed in the layers M0 to M4, precision processing such as plasma etching or chemical vapor deposition (CVD) is exclusively used. In other words, contact holes and wiring trenches are formed in the insulating layer 20 in the layer M0, and the contacts 21 and the wiring layers 22 are formed in the contact holes and the wiring trenches. In addition, while forming the insulating layers 30a, 30b, 40a, and 40b and the like in the upper layers M1 to M4, via holes, wiring trenches, and the like are sequentially formed therein, and the vias 31, 33, 41, and 43, the wiring layers 32, 34, 42, and 44, and the like are formed in the via holes and the wiring trenches, respectively.
Note that, more specifically, as a method of forming the various configurations, there is a single damascene process to individually form the vias 31, 33, 41, and 43 and the like and corresponding wiring layers 32, 34, 42, and 44 and the like when the Cu layer is adopted as the metal layer, or a dual damascene process to collectively form these vias 31, 33, 41, and 43, the wiring layers 32, 34, 42, and 44, and the like.
For example, in an example of a combination of the via 31 and the wiring layer 32, in the single damascene process, a via hole is formed, the metal layer is filled in the via hole to form the via 31, before a wiring trench is formed on the formed via 31, and then, the metal layer is filled in the wiring trench to form the wiring layer 32.
On the other hand, in the dual damascene process, after the via hole and the wiring trench are formed, the via hole and the wiring trench are collectively filled with the metal layer to simultaneously form the via 31 and the wiring layer 32.
Furthermore, when the via hole and the wiring trench are formed by the dual damascene process, either a process (via first process) or a process (trench first process) is mainly adopted. In the process (via first process), after the via hole is formed, the wiring trench is formed by expanding an upper end portion of the via hole, and in the process (trench first process), after the wiring trench is formed, the via hole extending in a depth direction from a bottom surface of the wiring trench is formed.
In the semiconductor device 1 of the first embodiment, the vias 31, 33, 41, and 43, the wiring layers 32, 34, 42, and 44, and the like can be formed by, for example, any of the methods described above, different formation methods may be used in different layers, and in addition, an Al layer, an Al—Si—Cu layer, and the like may be used as a wiring material.
A process of forming the via VA, the wiring layers WA and WB, and the like in the layers R0 and R1 is performed as follows in the final stage of the back-end-of-line process, by using an inexpensive processing with reduced manufacturing load, such as lift-off using photolithography or the like or electrolytic plating.
As illustrated in
As illustrated in
As illustrated in
Note that when the barrier metal layer 51b and the seed layer are formed by sputtering or the like, it is preferable to continuously form the barrier metal layer 51b and the seed layer while holding the semiconductor substrate 10 to be treated under vacuum. Furthermore, for the barrier metal layer 51b, it is preferable to use a material having a barrier property against Cu or the like in the seed layer and plating layer 52 which are to be formed later and having high adhesion to the insulating layer 50. The Ti, TiW, or the like described above satisfies these conditions.
As illustrated in
As illustrated in
Note that the plating layer 52 and the like formed in each of the opening portions OA of the opening portions OA and OBa becomes the wiring layer WA that functions as the re-distribution layer. Therefore, the opening portions OA of the mask pattern 71 described above are formed at positions to which the wiring drawn position for the wiring layer 44 can be changed so that the wiring layer WA can rewire the lower wiring layer 44.
As illustrated in
Note that as described above, the process of forming a wiring pattern or the like by using the mask pattern 71 or the like as a template is also referred to as lift-off or the like.
As illustrated in
Thus, the plating layer 52 and the like having formed in the opening portion OA of the mask pattern 71 are covered with the mask pattern 72. In addition, the plating layer 52 is exposed from the opening portion OBb. At this time, from the viewpoint of alignment accuracy of the mask pattern 72 with the plating layer 52, the opening portion OBb of the mask pattern 72 is preferably formed larger than the opening portion OBa of the mask pattern 71.
As illustrated in
As illustrated in
As illustrated in
As illustrated in
Note that in wet etching of the barrier metal layer 51 and the like, side etching occurs in the seed layer and the barrier metal layer 51, and further, the plating layer 52 on the barrier metal layer 51 are partially etched. Therefore, the width of the plating layer 52 may be reduced, and the coating layer 53 on the plating layer 52 may have a shape protruding from an end of the plating layer 52 into an eaves shape.
As illustrated in
As described above, the semiconductor device 1 according to the first embodiment is manufactured.
Next, an example of forming wiring layers WAx and WBx according to a comparative example will be described with reference to
In other words, a barrier metal layer 51xb and the like are formed as illustrated in
Therefore, the wiring layer WAx functioning as the re-distribution layer and the wiring layer WBx functioning as the electrode pad are formed.
As described above, in the semiconductor device of the comparative example, the wiring layer WAx functioning as the re-distribution layer is formed identically to, for example, the thickness of the wiring layer WBx functioning as the electrode pad. Accordingly, a design rule increased for a thick film process is also applied to the wiring layer WAx, making it difficult to miniaturize the wiring layer WAx. This can be a factor that hinders the reduction in size of the semiconductor device.
Furthermore, the coating layer 53x serving as the bonding layer with the bonding wire is also formed in the wiring layer WAx that does not require the bonding layer, causing an increase in process cost. In addition, the wiring patterns of a thick film has a risk of removal of the insulating layer 50x serving as the protective layer for the wiring patterns, and therefore, it is necessary to perform appearance inspection to secure bonding reliability and improving a yield in bonding. Both the wiring layers WAx and WBx formed into the thick film increases the total number of inspections for the wiring layers WAx and WBx as well, and further, the process cost increases.
Therefore, it is considered to separately form the wiring layer WAx as the re-distribution layer, in a layer below the wiring layer WBx as the electrode pad. However, an increased number of layers of the semiconductor device eventually causes an increase in manufacturing load and process cost.
According to the first embodiment, the semiconductor device 1 includes the wiring layer 22, the wiring layer WA, and the wiring layer WB. The wiring layer 22 is arranged in the layer M0 as the lowermost layer of the plurality of layers M0 to M4, R0, and R1, the wiring layer WA is arranged in the layer R1 as the uppermost layer and thicker than the wiring layer 22, and the wiring layer WB is arranged in the layer R1 as the uppermost layer, thicker than the wiring layer WA, and has a thickness 40 times or more the thickness of the wiring layer 22.
In this way, the wiring layers WA and WB having different thicknesses are allowed to be formed at the final stage of the back-end-of-line process.
In addition, for example, the thickness of the wiring layer WB 40 times or more the thickness of the wiring layer 22 makes it possible to reduce on-resistance to improve output from each transistor TR when the wiring layer WB functions as the electrode pad connected to the bonding wire. In addition, the heat dissipation characteristic of the wiring layer WB can be improved to improve breakdown resistance, and the occurrence of damage in the lower layers M0 to M4 and the like due to a load upon bonding with the bonding wire can be suppressed.
Meanwhile, for example, forming the wiring layer WA functioning as the re-distribution layer or the like into the thin layer makes it possible to apply a finer design rule to the wiring layer WA, without increasing the number of layers of the semiconductor device 1. Therefore, it is possible to facilitate reduction in the process cost and reduction of the size of the semiconductor device 1.
As described above, it is possible to satisfy different requirements for improvement of device characteristic by forming the thick film and reduction of the design rules.
According to the semiconductor device 1 of the first embodiment, the wiring layer WB has the upper surface exposed from the opening portion 50p of the insulating layer 50. This configuration makes it possible to make the wiring layer WB function as the electrode pad.
According to the semiconductor device 1 of the first embodiment, the wiring layer WA includes the plating layer 52 that includes a metal such as Cu, and the barrier metal layer 51 that includes a metal different from the metal of the plating layer 52 and that is arranged below the plating layer 52, and on the plating layer 52 of the wiring layer WB, the coating layer 53 is selectively arranged that includes a metal such as Ti or TiW different from the metal of the plating layer 52 and that is arranged on the upper side of the plating layer 52.
As described above, the coating layer 53 is formed only in the wiring layer WB and the wiring layer WA eliminates the need for the coating layer 53, and therefore, the process cost can be further reduced.
Hereinafter, a second embodiment will be described in detail with reference to the drawings. A semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment described above in that some of wiring layers are formed without making contact with a layer therebelow.
In the following drawings, the same reference numerals are given to the same configurations as those of the first embodiment described above, and the descriptions thereof may be omitted.
As illustrated in
In addition, a plurality of vias VB connected to the wiring layer 46 are arranged in the insulating layer 40, and these vias VB are connected to a wiring layer WD arranged in the insulating layer 50 belonging to the layer as the uppermost layer. The wiring layer CB is also disposed in the insulating layer 50.
The wiring layer CB as the second metal layer has, for example, a meandering shape in which a thin line meanders several times as viewed from above, and is arranged above the insulating layer 40 without making contact with the insulating layer 40 therebelow. Therefore, the wiring layer CB is arranged, for example, inside the insulating layer 50 while being separated from the insulating layer 40. However, the wiring layer CB may have a comb shape or a membrane shape. In either configuration, the wiring layer CB is configured to exclusively include an intermediate layer 57.
The wiring layer WD as the third metal layer, has, for example, a pad shape as viewed from above, and has an upper surface partially exposed from the opening portion 50p of the insulating layer 50. The wiring layer WD also has a thickness 40 times, more preferably 40 times or more and 80 times or less the thickness of the wiring layer in the layer as the lowermost layer.
In addition, the wiring layer WD has a configuration in which a barrier metal layer 55 as the second layer, a plating layer 56 as the first layer, and a coating layer 58 are stacked in this order. The wiring layer WD includes the intermediate layer 57 as the third layer interposed in the plating layer 56, and a seed layer, which is not illustrated, interposed between the barrier metal layer 55 and the plating layer 56.
The barrier metal layer 55 is, for example, a Ti layer or TiW layer, similarly to the barrier metal layer 51 described above. The seed layer, which is not illustrated, and the plating layer 56 are each, for example, a Cu layer or the like, similarly to the seed layer and the plating layer 52 which are described above. In this configuration, Cu is an example of the first metal. The intermediate layer 57 is, for example, a Si layer, Pd layer, or the like. In this configuration, Si or Pd is an example of the second metal. Similarly to the coating layer 53 described above, the coating layer 58 is, for example, a NiPd layer, NiAu layer, NiPdAu layer, Au layer, or the like.
The intermediate layer 57 of the wiring layer WD is connected to the intermediate layer 57 of the wiring layer CB, and whereby the wiring layer WD functions as an anchor to support the wiring layer CB arranged above the insulating layer 40. The wiring layer WD may also have a function as the electrode pad.
The wiring layer WD is arranged on one or both sides of the wiring layer CB described above to support the wiring layer CB, and the wiring layer CB has a cantilever beam structure or a fixed beam structure.
Meanwhile, the wiring layer CB as a thin layer functions as, for example, an inductor. Alternatively, the wiring layer CB as a thin layer may function as a sensor or the like to sense pressure, a gas, a sound wave, or the like in the atmosphere around the semiconductor device of the second embodiment, or may function as a movable spring, a micromirror, or the like. In this configuration, instead of burying the wiring layer CB in the insulating layer 50, a gap serving as a movable range for the wiring layer CB may be provided therearound.
As described above, the portion of the layer as the uppermost layer of the semiconductor device of the second embodiment is allowed to be configured as, for example, the inductor or a micro electro mechanical system (MEMS).
Furthermore, in the portions of layers below the uppermost layer, the semiconductor device of the second embodiment can include a transistor, a contact connected to the transistor, a via, a wiring layer, and the like, similarly to the semiconductor device 1 of the embodiment described above. Such portions of the lower layers of the semiconductor device are configured as, for example, a control circuit or the like to control the inductor or MEMS in the portion of the uppermost layer.
Next, a method of manufacturing the semiconductor device according to the second embodiment will be described with reference to
Note that
As illustrated in
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Therefore, in portions covered with the coating layer 58, the barrier metal layer 55 and the seed layer that have a pattern of the wiring layer WD are formed with respect to the plating layer 56 thereabove to have a side etched shape, and the plating layer 56 itself is also partially etched to form the wiring layer WD recessed in the width direction.
On the other hand, in a portion covered with the intermediate layer 57, the intermediate layer 57 and the plating layer 56 have a thin line shape, and therefore, the barrier metal layer 55 and the seed layer disappear together with the plating layer 56 thereabove. At this time, the intermediate layer 57 including the metal having the wet etching resistance higher than that of the metal of the seed layer, the plating layer 56, and the like remains without being removed. Therefore, the wiring layer CB having the intermediate layer 57 separated upward from the insulating layer 40 and supported by the wiring layer WD is formed. This state is illustrated in the top view of
As illustrated in
As described above, the semiconductor device according to the second embodiment is manufactured.
According to the semiconductor device of the second embodiment, the wiring layer CB is arranged above a layer therebelow without making contact with the layer therebelow. The wiring layer CB configured in this way makes it possible to constitute the semiconductor device including the inductor, MEMS, or the like at low cost.
According to the semiconductor device of the second embodiment, the wiring layer CB includes a metal such as Si or Pd different from the metal of the plating layer 56, and the wiring layer WD includes the intermediate layer 57 including the metal different from the metal of the plating layer 56, at a height position equal to that of the wiring layer CB in the plating layer 56. Each layer of the wiring layers WD and CB constituted in this way makes it possible to constitute the wiring layer CB so as to be arranged above a layer therebelow without making contact with the layer therebelow.
According to the semiconductor device of the second embodiment, the wiring layer WD is connected to the wiring layer CB to serve as the anchor to support the wiring layer CB, and the wiring layer CB has the cantilever beam structure or fixed beam structure having a comb shape, a meandering shape, or a membrane shape. This configuration makes it possible to make the wiring layer CB function as the inductor, sensor, or the like.
The semiconductor device according to the second embodiment provides effects similar to those of the semiconductor device 1 according to the first embodiment described above.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-156365 | Sep 2023 | JP | national |
