SEMICONDUCTOR DEVICE COMPRISING A CONTACT STRUCTURE WITH INCREASED ETCH SELECTIVITY

Abstract

By providing additional etch stop layers and/or etch protection layers, a corresponding etch process for forming contact openings for directly connecting polysilicon lines and active areas may be controlled in a highly reliable manner. Consequently, conductive line erosion and/or penetration into extension regions may be significantly reduced, thereby improving the reliability and performance of corresponding semiconductor devices.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

FIGS. 1 a-1d schematically show cross-sectional views of a conventional semiconductor device during the formation of a contact region for directly connecting a polysilicon line and a drain/source region during various manufacturing stages in accordance with conventional techniques, resulting in an increased risk for leakage currents or short circuits and/or polysilicon line erosion;

FIGS. 2 a-2g schematically show cross-sectional views of a semiconductor device including a circuit element and a contact region for a direct connection of certain contact regions of the circuit element during various manufacturing stages in accordance with illustrative embodiments of the present invention, in which an additional etch stop layer is formed on the basis of an opening of a mask layer prior to the deposition of the interlayer dielectric material;

FIGS. 3 a-3b schematically show a top view and a cross-sectional view, respectively, of a semiconductor device having an increased thickness of an etch stop layer located between an active semiconductor region and a corresponding sidewall spacer element in accordance with still further illustrative embodiments;

FIG. 3 c schematically illustrates a sidewall spacer structure with increased etch selectivity for a contact etch process according to one illustrative embodiment;

FIGS. 4 a-4g schematically show cross-sectional views of a semiconductor device during the formation of an etch protection layer covering sidewall portions of a conductive line during the formation of a contact region in accordance with still other illustrative embodiments of the present invention; and

FIGS. 5 a-5c schematically illustrate cross-sectional views of a semiconductor device during the formation of a contact region during various manufacturing stages in which an additional etch stop layer is provided to reliably stop the etch process through a contact etch stop layer in accordance with further illustrative embodiments of the present invention.

Claims

1. A method, comprising: forming an etch stop layer above a circuit element having a conductive line and an active semiconductor region, said etch stop layer covering an area that substantially corresponds to a contact opening to be formed to connect said conductive line and said active semiconductor region;forming an interlayer dielectric material above said circuit element and said etch stop layer;forming said contact opening in said interlayer dielectric material by an etch process using said etch stop layer as an etch stop; andfilling said contact opening with a conductive material.

2. The method of claim 1, wherein forming said etch stop layer comprises depositing a dielectric material above said circuit element prior to depositing said interlayer dielectric material, said dielectric material of said etch stop layer having a high etch selectivity to at least a lower portion of said interlayer dielectric material.

3. The method of claim 2, wherein depositing said interlayer dielectric material comprises depositing a contact etch stop layer on said etch stop layer and depositing an interlayer dielectric layer on said contact etch stop layer.

4. The method of claim 3, wherein forming said contact opening comprises etching said interlayer dielectric layer using said contact etch stop layer as an upper etch stop, etching through said contact etch stop layer using said etch stop layer as said etch stop.

5. The method of claim 1, wherein forming said etch stop layer comprises forming a mask layer for defining an opening above said circuit element, said opening having dimensions substantially corresponding to said contact opening, forming said etch stop layer in said opening and on said mask layer, and removing said mask layer.

6. The method of claim 5, wherein said mask layer is comprised of photoresist.

7. The method of claim 5, wherein forming said etch stop layer comprises depositing a conductive etch stop material.

8. The method of claim 5, wherein forming said etch stop layer comprises depositing an insulating material and removing said insulating material prior to filling said contact opening with said conductive material.

9. The method of claim 8, further comprising forming at least one standard contact opening in said interlayer dielectric material together with said contact opening in a common process sequence.

10. The method of claim 1, wherein forming said etch stop layer comprises depositing an etch stop material above said circuit element, forming a mask layer for defining an opening above said circuit element, said opening having dimensions substantially corresponding to said contact opening, patterning said etch stop material on the basis of said mask layer and removing said mask layer.

11. The method of claim 10, wherein said etch stop material is deposited prior to forming said active semiconductor region by ion implantation.

12. The method of claim 10, further comprising forming at least one sidewall spacer adjacent to said conductive line and using said at least one sidewall spacer to form said active semiconductor region by ion implantation prior to depositing said etch stop material.

13. A method, comprising: forming a conductive line above a substrate;forming an etch protection layer on sidewalls of said conductive line;embedding said conductive line in an interlayer dielectric material;forming a contact opening in said interlayer dielectric material for contacting to said conductive line and said semiconductor region, said etch protection layer protecting the sidewalls of said conductive line; andfilling said contact opening with a conductive material to electrically connect said conductive line with said exposed semiconductor region.

14. The method of claim 13, further comprising forming an etch stop layer above said semiconductor region, said etch stop layer covering an area that corresponds to an area of said semiconductor region that is covered by said conductive material.

15. The method of claim 14, wherein said etch stop layer is formed after forming said etch protection layer.

16. The method of claim 15, wherein said etch stop layer is comprised of a conductive material.

17. The method of claim 15, wherein said etch stop layer is formed by using a mask layer.

18. The method of claim 17, wherein said mask layer is formed after depositing an etch stop material and wherein said etch stop material is patterned on the basis of said mask layer.

19. The method of claim 17, wherein said mask layer is formed prior to depositing an etch stop material, and wherein said etch stop material is patterned by removing said mask layer.

20. A semiconductor device comprising: a conductive line;an active semiconductor region adjacent to said conductive line;an interlayer dielectric layer formed on said conductive line and said active semiconductor region;a contact region formed in said interlayer dielectric layer and filled with a conductive material to electrically connect said conductive line and said active semiconductor region; andan etch stop layer formed within a portion of said contact region and located between said conductive material and said active semiconductor region, said etch stop layer being comprised of a material having a high etch selectivity with respect to a contact etch stop layer formed between said interlayer dielectric layer and said etch stop layer.

21. The semiconductor device of claim 20, wherein said conductive material comprises a conductive barrier layer formed on surface portions of said conductive line and said active semiconductor region, said barrier layer comprising a sidewall layer portion formed on sidewalls of said contact region and a bottom layer portion, said etch stop layer being a part of said bottom layer portion.