Patent Application
20250174507
This disclosure relates generally to semiconductor device packaging, and more specifically, to a semiconductor device having an embedded die and method of forming the same.
Today, there is an increasing trend to include sophisticated semiconductor devices in products and systems that are used every day. These sophisticated semiconductor devices may include features for specific applications which may impact the configuration of the semiconductor device packages, for example. With such features and applications, the configuration of the semiconductor device packages may limit performance of the semiconductor devices or impact the costs of the semiconductor devices. Accordingly, significant challenges exist in accommodating these features and applications while minimizing the impact on semiconductor devices' performance and costs.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
Generally, there is provided, a semiconductor device having an embedded die. The semiconductor device includes a package substrate with a cavity sized sufficiently to embed a semiconductor die within the cavity. The package substrate includes fiberglass reinforced epoxy resin core material such as FR4 with metal layers formed on both top and bottom side of the core. For example, a first metal layer (e.g., copper foil) is formed at a first major side (e.g., top) of the package substrate and a second metal layer (e.g., copper foil) is formed at a second major side (e.g., bottom) of the package substrate such the core is sandwiched between the first metal layer and the second metal layer. A plurality of redistribution traces is formed by patterning and etching the second metal layer, for example. The cavity is formed in central region of the package substrate. The cavity has an opening at the second major side and extends through the core and ends at an inner surface of a portion of the first metal layer at the first major side. The plurality of redistribution traces is arranged to substantially surround the cavity in a fanout configuration, for example. The semiconductor die is mounted in the cavity such that a backside of the semiconductor die is affixed to the exposed inner surface portion of the first metal layer. Bond pads at the active side of the semiconductor die are interconnected with respective redistribution traces by way of bond wires. An encapsulant encapsulates the semiconductor die and the second major side of the package substrate. Openings through the encapsulant are formed exposing base portions of the redistribution traces. Under-bump metallization structures are formed on respective exposed base portions of respective redistribution traces. Conductive package connectors (e.g., solder balls) are affixed to exposed surface portions of respective under-bump metallization structures. By forming the semiconductor device with an embedded semiconductor die in this manner, the semiconductor die is fully protected and capable of high-power applications requiring high current interconnects.
An outline of a cavity formed in the package substrate 102 at a subsequent stage of manufacture is shown as a dashed line 104 for reference. The redistribution traces 106 are arranged to substantially surround the cavity and a semiconductor die mounted in the cavity at a subsequent stage of manufacture, for example. In this embodiment, each of the redistribution traces 106 includes a wiring pad region 108 (e.g., proximal end) and a base region 110 (e.g., distal end). The wiring pad region 108 is configured for conductive connection to the semiconductor die by way of a bond wire at a subsequent stage of manufacture, for example. In addition, the base region 110 is configured as a base for formation of an under-bump metallization (UBM) structure at a subsequent stage of manufacture, for example.
The shape, location, and number of the redistribution traces 106 of the package substrate 102 depicted in
An outline of a cavity formed in the package substrate 102 at a subsequent stage of manufacture is shown as a dashed line 104 for reference. In this embodiment, each of the redistribution traces 106 includes the wiring pad region 108 at a proximal end and a base region 110 at a distal end of the redistribution trace. For example, the wiring pad region 108 is configured for connection to the semiconductor die by way of a bond wire and the base region 110 is configured as a base for formation of a UBM structure at subsequent stages of manufacture, for example.
The semiconductor die 402 has an active side (e.g., major side having circuitry, bond pads) and a backside (e.g., major side opposite of the active side). As depicted in the cross-sectional view of
In this embodiment, bond pads 404 of the semiconductor die 402 interconnected with respective redistribution traces 106 by way of bond wires 408. In this embodiment, a first end of a first bond wire 408 is attached to a first bond pad 404 by way of a first bond (e.g., ball bond) and a second end of the first bond wire 408 is attached to a wiring pad region 108 of a respective redistribution trace 108 by way of a second bond (e.g., stitch bond).
After encapsulating the semiconductor die 402 and the bottom side of the package substrate 102, a plurality of cavities 504 are formed over the base regions 110 of respective redistribution traces 106. The cavities 504 include openings at the bottom side of the encapsulant 502 located directly over the base regions 110. In this embodiment, the cavities 504 are formed by way of laser ablation. Each of the cavities 504 extends from the opening at the bottom side, through the encapsulant 502, and ends at the metal base region 110 of a respective redistribution trace 106. As a result, at least a portion of the base region 110 of respective redistribution traces 106 is exposed through the cavities 504.
Generally, there is provided, a method including patterning a first metal layer at a first major side of a package substrate to form a plurality of redistribution traces; forming a first cavity in the package substrate, the plurality of redistribution traces substantially surrounding the first cavity; mounting a semiconductor die in the first cavity; forming a wire bond between a bond pad of the semiconductor die and a wiring pad region of a redistribution trace of the plurality of redistribution traces; encapsulating with an encapsulant the semiconductor die and the first major side of the package substrate; exposing a base region of the redistribution trace; and selectively plating an under-bump metallization (UBM) structure on the exposed base region. The exposing the base region of the redistribution trace may include forming a second cavity in the encapsulant by way of laser ablation, the base region of the redistribution trace exposed at the bottom of the second cavity. The selectively plating the UBM structure may include filling the second cavity with a copper or copper alloy material. The method may further include affixing a conductive package connector on the UBM structure. The forming the first cavity may include exposing a portion of a second metal layer at a second major side of the package substrate. The forming the first cavity in the package substrate may include using laser ablation to form the first cavity and expose the portion of the second metal layer. The mounting the semiconductor die in the first cavity may include affixing a backside of the semiconductor die to the exposed second metal layer portion by way of a die attach film (DAF). The first metal layer at the first major side and the second metal layer at the second major side may be formed from a copper or copper alloy material. The package substrate may be characterized as a metal clad FR4 substrate.
In another embodiment, there is provided, a semiconductor device including a package substrate having a first major side and a second major side; a cavity formed in the package substrate, the cavity having an opening at the first major side; a plurality of metal redistribution traces formed at the first major side, the plurality of redistribution traces substantially surrounding the cavity; a semiconductor die mounted in the cavity; a wire bond having a first end affixed at a bond pad of the semiconductor die and a second end affixed at a wiring pad region of a redistribution trace of the plurality of redistribution traces; an encapsulant encapsulating the semiconductor die and the first major side of the package substrate; a base region of the redistribution trace exposed through the encapsulant; and an under-bump metallization (UBM) structure formed on the exposed base region. The UBM structure may be characterized as a structure formed by way of plating a copper or copper alloy material. The cavity in the package substrate may be formed by way of laser ablation. The package substrate may further include a metal layer formed at the second major side of the package substrate. The cavity formed in the package substrate may expose a portion of the metal layer formed at the second major side of the package substrate. The semiconductor die mounted in the cavity may include a backside of the semiconductor die affixed to the exposed portion of the metal layer by way of a die attach film (DAF).
In yet another embodiment, there is provided, a method including forming a plurality of redistribution traces at a first major side of a package substrate; forming a cavity in the package substrate, the plurality of redistribution traces substantially surrounding an opening of the cavity at the first major side; mounting a semiconductor die in the cavity; forming a wire bond between a bond pad of the semiconductor die and a wiring pad region of a redistribution trace of the plurality of redistribution traces; encapsulating with an encapsulant the semiconductor die and the first major side of the package substrate; and exposing a base region of the redistribution trace. The forming the cavity in the package substrate may include exposing a portion of a second metal layer formed at a second major side of the package substrate. The mounting the semiconductor die in the cavity may include affixing a backside of the semiconductor die on the exposed second metal layer portion by way of a die attach film (DAF). The method may further include selectively plating an under-bump metallization (UBM) structure on the exposed base region of the redistribution trace. The method may further include affixing a conductive package connector on the UBM structure.
By now, it should be appreciated that there has been provided a semiconductor device having an embedded die. The semiconductor device includes a package substrate with a cavity sized sufficiently to embed a semiconductor die within the cavity. The package substrate includes fiberglass reinforced epoxy resin core material such as FR4 with metal layers formed on both top and bottom side of the core. For example, a first metal layer (e.g., copper foil) is formed at a first major side (e.g., top) of the package substrate and a second metal layer (e.g., copper foil) is formed at a second major side (e.g., bottom) of the package substrate such the core is sandwiched between the first metal layer and the second metal layer. A plurality of redistribution traces is formed by patterning and etching the second metal layer, for example. The cavity is formed in central region of the package substrate. The cavity has an opening at the second major side and extends through the core and ends at an inner surface of a portion of the first metal layer at the first major side. The plurality of redistribution traces is arranged to substantially surround the cavity in a fanout configuration, for example. The semiconductor die is mounted in the cavity such that a backside of the semiconductor die is affixed to the exposed inner surface portion of the first metal layer. Bond pads at the active side of the semiconductor die are interconnected with respective redistribution traces by way of bond wires. An encapsulant encapsulates the semiconductor die and the second major side of the package substrate. Openings through the encapsulant are formed exposing base portions of the redistribution traces. Under-bump metallization structures are formed on respective exposed base portions of respective redistribution traces. Conductive package connectors (e.g., solder balls) are affixed to exposed surface portions of respective under-bump metallization structures. By forming the semiconductor device with an embedded semiconductor die in this manner, the semiconductor die is fully protected and capable of high-power applications requiring high current interconnects.
The terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
