BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:
FIG. 1 is a cross sectional view showing a semiconductor device according to a first embodiment mode;
FIG. 2 is a partially enlarged cross sectional view showing a super junction structure in the device shown in FIG. 1;
FIG. 3 is a graph showing a voltage waveform and a current waveform in the device shown in FIG. 1 in case of switching;
FIG. 4 is a cross sectional view showing a semiconductor device according to a second embodiment mode;
FIG. 5 is a partially enlarged cross sectional view showing a super junction structure in the device shown in FIG. 4;
FIG. 6 is a cross sectional view showing a semiconductor device according to a third embodiment mode;
FIG. 7 is a partially enlarged cross sectional view showing a super junction structure in the device shown in FIG. 6;
FIGS. 8-11 are cross sectional views explaining a method for manufacturing the semiconductor device shown in FIG. 6;
FIG. 12 is a cross sectional view explaining another method for manufacturing the semiconductor device shown in FIG. 6;
FIG. 13 is a partially enlarged cross sectional view showing a super junction structure in a semiconductor device according to a fourth embodiment mode;
FIG. 14 is a partially enlarged cross sectional view showing a depletion layer in the super junction structure in FIG. 13;
FIG. 15 is a partially enlarged cross sectional view showing a super junction structure in a semiconductor device according to a modification of the fourth embodiment mode;
FIG. 16 is a cross sectional view showing another semiconductor device according to a first modification of the third embodiment mode;
FIG. 17 is a perspective view showing further another semiconductor device according to a second modification of the third embodiment mode;
FIG. 18 is a graph showing a relationship between a deviation of impurity surface concentration and a breakdown voltage;
FIG. 19 is a cross sectional view showing a semiconductor device as a comparison of the first embodiment mode;
FIGS. 20-22 are partially enlarged cross sectional views showing a depletion layer in the device shown in FIG. 19;
FIG. 23 is a graph showing a voltage waveform and a current waveform of the device shown in FIG. 19 in case of switching;
FIG. 24 is a cross sectional view showing a semiconductor device according to a fifth embodiment mode;
FIG. 25 is a cross sectional view showing the device taken along line XXV-XXV in FIG. 24;
FIGS. 26A and 26B are cross sectional views showing a depletion layer in the device shown in FIG. 25;
FIGS. 27A and 27B are cross sectional views showing a depletion layer in a semiconductor device having no bridge portion as a comparison of the fifth embodiment mode;
FIGS. 28-29 and 31-32 are cross sectional views explaining a method for manufacturing the device shown in FIG. 25;
FIG. 30 is a perspective view explaining the method for manufacturing the device shown in FIG. 25;
FIG. 33 is a cross sectional view showing a semiconductor device according to a sixth embodiment mode; and
FIG. 34 is a perspective view showing the semiconductor device having no bridge portion as a comparison of the fifth embodiment mode.