Patent Application
20060151785
The present invention is generally directed to a semiconductor device and, more specifically, to a semiconductor device with a split pad design.
Conventional metal-oxide semiconductor field-effect transistor (MOSFET) and insulated-gate bipolar-transistor (IGBT) power devices have usually been designed with a cellular structure, which includes thousands of elementary cells integrated within a semiconductor die. Each cell has included a transistor, which is connected in parallel to the transistors of the other cells to contribute to an overall current associated with the power device. In general, each cell includes a gate region, which is covered by a thin electrically insulative layer, e.g., a gate oxide layer. The gates of the cells are interconnected with a conductor, e.g., a polysilicon or metal layer, that is formed on a surface of the device. The remaining surface of a MOSFET semiconductor device is typically covered by another conductor, which contacts and interconnects the source region of all of the cells. In general, the cellular structure allows for the achievement of relatively low voltage drop across the power device, i.e., low drain-to-source resistance, when it is in the on-state and, thus, relatively low power dissipation for the power device.
With reference to
In semiconductor devices that have implemented solder connections, at least one such device has located a gate pad in a corner of the device. With reference to
In general, designers have attempted to design gate signal ring and fingers to allow parallel cells within a semiconductor device to turn on and off with minimal propagation delay between the cells and to allow current to flow in a uniform manner across the power device. The gate signal runners have been made of a variety of materials, e.g., metals, polysilicon or a combination of metal and polysilicon, and have had various configurations depending on the physical dimensions and operating frequency of the device. For devices operating at lower frequencies, a relatively simple gate structure that traverses the periphery of the device has generally been suitable. However, devices operating at higher frequencies have generally required additional gate fingers (see
Gate pads have usually been centered along one of the edges of the semiconductor device or located at a center of the device. In a typical semiconductor device that implements wire bonding, the gate pad provides an interconnect point between the cells of the device and an external lead or device. Frequently, MOSFET (IGBT) devices are interconnected to external circuitry by soldering the drain (collector) and wire bonding the gate and source (gate and emitter) to other interconnects. Other solderable MOSFET devices, such as flip-chip devices, have been configured to allow for drain, source and gate interconnects to be achieved with a solder connection. Similarly, IGBT devices have been constructed such that collector, gate and emitter connections are made through a solder connection.
In many MOSFET semiconductor designs, it is desirable to integrate electronic components, such as resistors, zener diodes or conventional diodes from the gate to the source or from the gate to the drain. In IGBT semiconductor designs, electronic components are typically integrated from the gate to emitter or from the gate to the collector. In general, such components provide control or protection functions for an associated power device. In smart power devices, additional complex logic or driver circuitry may be integrated within the semiconductor device and be connected to various input/output pads to provide added functionality. Unfortunately, the addition of the integrated electronic components and circuitry to the gate of a semiconductor device can affect testing of the semiconductor device. For example, leakage current tests, gate stress tests, avalanche tests and energy tests of the semiconductor device may be adversely affected, when integrated electronic components are coupled to the gate of the device. While the previously mentioned tests may be omitted on semiconductor devices that include integrated components and other circuitry, omitting the tests may allow semiconductor devices with high gate leakage currents or latent defects to be placed in a production electronic product that may then experience premature failure in the field.
What is needed is a technique that allows semiconductor devices that include a device body including a plurality of parallel cells and at least one integrated electronic component to be tested without the test results associated with the plurality of parallel cells being adversely affected by the at least one integrated electronic component.
According to one embodiment of the present invention, a semiconductor device is provided that includes a device body, a gate pad and a gate signal distribution runner. The device body includes a plurality of parallel cells and at least one integrated electronic component. The gate pad is located on a surface of the device body and includes a first portion and a second portion that are electrically isolated. The gate signal distribution runner is electrically coupled to and extends from the first portion of the gate pad. The gate signal distribution runner provides a gate signal to a gate of each of the plurality of parallel cells. In order to provide additional electronic components without affecting the testing of the device, at least one integrated electronic component is electrically coupled to the second portion of the gate pad.
According to another aspect of the present invention, the plurality of parallel cells defines a metal-oxide semiconductor field-effect transistor (MOSFET). According to a different aspect of the present invention, the plurality of parallel cells defines an insulated-gate bipolar-junction transistor (IGBT). According to another embodiment of the present invention, the gate signal distribution runner is made of one of a metal and a polysilicon. According to another aspect, the metal is aluminum. According to a different aspect, the integrated electronic component includes at least one of a resistor, a diode and a zener diode. According to another embodiment, the first and second portions of the gate pad are electrically interconnected after testing of the parallel cells.
According to another aspect of the present invention, a semiconductor device includes a device body, a pad and a signal distribution runner. The device body includes a plurality of parallel cells and at least one integrated electronic component. The pad is located on a surface of the device body and includes a first portion and a second portion that are electrically isolated. The signal distribution runner is electrically coupled to and extends from the first portion of the pad. The signal distribution runner provides a signal to a same terminal of each of the plurality of parallel cells. In order to provide additional electronic components without affecting the testing of the device, at least one integrated electronic component is electrically coupled to the second portion of the pad.
These and other features, advantages and objects of the present invention will be further understood and appreciated by those skilled in the art by reference to the following specification, claims and appended drawings.
The present invention will now be described, by way of example, with reference to the accompanying drawings, in which:
As is noted above, in power metal-oxide semiconductor field-effect transistor (MOSFET) devices and/or insulated-gate bipolar-junction transistor (IGBT) devices, gate pad and gate signal distribution runners are utilized to provide gate signal distribution to a plurality of parallel cells of the devices. The distribution of the gate signal controls the turn-on and turn-off characteristics of the device. In a typical prior art device, the gate pad has been a single metalized pad, which has been connected to an external package pin by a wire bond or solder interconnect. However, as is noted above, in many semiconductor designs, it is desirable to integrate other electronic components, e.g., resistors, zener diodes or conventional diodes, from the gate to source or from the gate to drain for a MOSFET device, or from the gate to emitter or from the gate to the collector for an IGBT device.
These integrated electronic components may provide control or protection functions for the power device. As is also noted above, in smart power devices, additional complex logic or driver circuitry may be integrated within the device and be connected to various input/output pads to provide additional functionality. As noted above, the addition of the integrated electronic components and circuitry to the gate of the device affects the ability of a test engineer to accurately determine device characteristics, such as current leakage, gate stress and avalanche and also affects energy tests performed on the device.
According to the present invention, in order to provide accurate useful results for various tests, the gate pad of the semiconductor device is partitioned to allow the semiconductor device to be tested, without the additional electronic components. According to the present invention, the pads are rejoined after testing such that the integrated electronic components are connected to the plurality of parallel cells that form the semiconductor device. As is discussed further below, the electronic components may be added back into the circuit through soldering the partitioned gate pad together or wire bonding the partitioned gate pad together during the wire bonding process.
In general, the present invention is applicable to the semiconductor devices that have top-side solderable or wire-bonded gate connections. It should be appreciated that a semiconductor device configured in this manner can be tested at the wafer level or at a die level using standard probe cards. In this manner, the probe cards and the tester hardware allow the various resistors, conventional diodes and/or zener diodes to be switched into or out of the circuit, thus, allowing full functional and parametric tests to occur at a wafer level. Further, special tests, such as gate level stress tests, energy tests and avalanche tests can also be performed without the test results being affected by the additional electronic components. When the semiconductor device is assembled into its package or system, the two or more split gate areas are then connected together through a solder connection or a wire bond.
It should be appreciated that a large variety of split gate options are possible. In general, the edge patterns of the various portions of the gate pad may be optimized to ensure proper bridging during the solder reflow or wire bond process. The present invention is also generally applicable to any input or-output integrated circuit pad that has circuitry or protection devices attached to it that would adversely affect testing of the device. It should be appreciated that testing the integrated circuit (IC) with the option of switching circuitry in or out at the wafer level may also be generally desirable.
As is also shown in
Accordingly, a semiconductor device with a split pad design has been disclosed herein that advantageously allows for testing of a primary semiconductor device without the test results being affected by an integrated electronic component that is included in the semiconductor device.
The above description is considered that of the preferred embodiments only. Modifications of the invention will occur to those skilled in the art and to those who make or use the invention. Therefore, it is understood that the embodiments shown in the drawings and described above are merely for illustrative purposes and not intended to limit the scope of the invention, which is defined by the following claims as interpreted according to the principles of patent law, including the doctrine of equivalents.
