Patent Application
20240014152
This disclosure relates generally to semiconductor device packaging, and more specifically, to a semiconductor device with under-bump metallization and method of forming the same.
Today, there is an increasing trend to include sophisticated semiconductor devices in products and systems that are used every day. These sophisticated semiconductor devices may include features for specific applications which may impact the configuration of the semiconductor device packages, for example. For some features and applications, the configuration of the semiconductor device packages may be susceptible to lower reliability which could impact performance and system costs. Accordingly, significant challenges exist in accommodating these features and applications while minimizing the impact on semiconductor devices' reliability while minimizing impact on performance and costs.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
Generally, there is provided, a semiconductor device with an under-bump metallization (UBM) structure. The semiconductor device includes a semiconductor die partially encapsulated with an encapsulant. An active side of the semiconductor die is exposed and coplanar with a surface of the encapsulant. A non-conductive layer is formed over an active side of semiconductor die and surface of the encapsulant. An opening in the non-conductive layer is formed to expose a bond pad. A laser ablated trench is formed at the surface of the non-conductive layer near a perimeter of the opening. By using a low energy laser to form the trench, a bottom surface of the trench is roughened. The UBM structure is formed by plating over the trench and exposed pad region. The rough texture of the trench allows for superior adhesion of the UBM structure at the trench. By forming the UBM in this manner, potential stress induced delamination is minimized thus improving overall reliability of the semiconductor device.
The semiconductor die 102 has an active side (e.g., major side having circuitry) and a backside (e.g., major side opposite of the active side). In this embodiment, the active side of the semiconductor die 102 is exposed (e.g., not encapsulated) and substantially coplanar with a first surface 114 of the encapsulant 112. The semiconductor die 102 includes a substrate (e.g., bulk) portion 110, a conductive interconnect trace 106 (e.g., copper, aluminum, or other suitable metal), a bond pad 104 conductively connected to the trace, and a final passivation layer 108 formed over the active side of the die. The bond pad 104 is configured for conductive connection to printed circuit board (PCB) by way of a UBM structure formed at a subsequent stage, for example. The term “conductive,” as used herein, generally refers to electrical conductivity unless otherwise noted.
The semiconductor die 102 may be formed from any suitable semiconductor material, such as silicon, germanium, gallium arsenide, gallium nitride, silicon nitride, silicon carbide, and the like. The semiconductor die 102 may further include any digital circuits, analog circuits, RF circuits, memory, signal processor, MEMS, sensors, the like, and combinations thereof. The semiconductor die 102 may include any number of conductive interconnect layers and passivation layers. For illustration purposes, the interconnect layer forming trace 106 and the final passivation layer 108 are depicted.
In this embodiment, the laser ablated trench 402 is formed at a first (e.g., outermost) surface 204 of the non-conductive layer 202. The laser ablated trench 402 is configured to enhance adhesion between the non-conductive layer 202 and the UBM structure formed at a subsequent stage, for example. The laser ablated trench 402 may be formed by way of a low energy laser, for example, configured to remove material at the first surface 204 of the non-conductive layer 202. By forming the laser ablated trench 402 in this manner, a bottom surface of the trench may result with a substantially roughened texture configured for improved adhesion. The laser ablated trench 402 may be formed having desired cross-sectional depth 404 and width 408 dimensions sufficient for enhancing adhesion between the non-conductive layer 202 and the subsequent UBM. For example, it may be desirable to form the laser ablated trench 402 with a predetermined cross-sectional depth 404 in a range of 25% to 50% of the thickness dimension 406 of the non-conductive layer 202. In this embodiment, a portion of the first surface 204 of the non-conductive layer 202 remains between the inner side wall of the laser ablated trench 402 and the perimeter of the opening 302.
In this embodiment, the laser ablated trench 502 is formed at the first surface 204 of the non-conductive layer 202 in a somewhat similar manner as the laser ablated trench 402. However, the laser ablated trench 502 includes an outer sidewall without an inner sidewall thus having a cross-sectional depth continuous from the outer sidewall through to the opening 302 as depicted in
In one embodiment, there is provided, a method including forming a non-conductive layer over an active side of a semiconductor die, the semiconductor die partially encapsulated with an encapsulant; forming an opening in the non-conductive layer, the opening exposing a portion of a bond pad of the semiconductor die; forming a laser ablated trench at a first surface of the non-conductive layer proximate to a perimeter of the opening, a bottom surface of the laser ablated trench substantially roughened; and plating to form an under-bump metallization (UBM) structure over the bond pad and laser ablated trench. The laser ablated trench may be formed at least partially surrounding the perimeter of the opening. The substantially roughed bottom of the laser ablated trench may be continuous into the opening. The method may further include affixing a conductive connector to the UBM structure. The method may further include after forming the laser ablated trench, applying a seed layer on the non-conductive layer and the exposed portion of the bond pad. The method may further include patterning a mask layer on the seed layer before plating to form the UBM structure. The method may further include after plating to form the UBM structure, removing the mask layer and the seed layer portion underlying the mask layer. The laser ablated trench may have a depth in a range of 25% to 50% of a thickness of the non-conductive layer. The opening may be formed by way of laser ablation at a higher energy level than that of the formation of the laser ablated trench.
In another embodiment, there is provided, a semiconductor device including a semiconductor die partially encapsulated with an encapsulant, an active side of the semiconductor die exposed and substantially coplanar with a first surface of the encapsulant; a non-conductive layer formed over the active side of the semiconductor die and the first surface of the encapsulant; an opening formed in the non-conductive layer exposing a portion of a bond pad of the semiconductor die; a laser ablated trench formed at a first surface of the non-conductive layer proximate to a perimeter of the opening, a bottom surface of the laser ablated trench substantially roughened; and an under-bump metallization (UBM) structure formed over the bond pad and laser ablated trench. The laser ablated trench may be formed at least partially surrounding the perimeter of the opening. The substantially roughed bottom of the laser ablated trench may be continuous into the opening. The semiconductor device may further include a conductive connector affixed to the UBM structure, the conductive connector configured for connection to a printed circuit board. The non-conductive layer may be formed as an Ajinomoto build-up film (ABF). The laser ablated trench may have a depth in a range of 25% to 50% of a thickness of the non-conductive layer.
In yet another embodiment, there is provided, a method including forming a non-conductive layer over an active side of a semiconductor die and a first surface of an encapsulant, the encapsulant partially encapsulating the semiconductor die; forming a laser ablated opening in the non-conductive layer exposing a portion of a bond pad of the semiconductor die; forming a laser ablated trench at a first surface of the non-conductive layer proximate to a perimeter of the opening, a bottom surface of the laser ablated trench substantially roughened; and plating to form an under-bump metallization (UBM) structure over the bond pad and laser ablated trench. The laser ablated trench may be formed at least partially surrounding the perimeter of the laser ablated opening. The substantially roughed bottom of the laser ablated trench may be continuous into the laser ablated opening. The method may further include affixing a conductive connector to the UBM structure. The laser ablated trench may have a depth in a range of 25% to 50% of a thickness of the non-conductive layer.
By now, it should be appreciated that there has been provided a semiconductor device with an under-bump metallization (UBM) structure. The semiconductor device includes a semiconductor die partially encapsulated with an encapsulant. An active side of the semiconductor die is exposed and coplanar with a surface of the encapsulant. A non-conductive layer is formed over an active side of semiconductor die and surface of the encapsulant. An opening in the non-conductive layer is formed to expose a bond pad. A laser ablated trench is formed at the surface of the non-conductive layer near a perimeter of the opening. By using a low energy laser to form the trench, a bottom surface of the trench is roughened. The UBM structure is formed by plating over the trench and exposed pad region. The rough texture of the trench allows for superior adhesion of the UBM structure at the trench. By forming the UBM in this manner, potential stress induced delamination is minimized thus improving overall reliability of the semiconductor device.
The terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
