Patent Application
20240347492
The present disclosure relates to a semiconductor device.
A semiconductor device has been used in which a semiconductor chip is mounted by flip-chip mounting (for example, see Patent Literature 1). In a case where a semiconductor chip is mounted on a multi-layer substrate, a pillar is formed on an electrode of the semiconductor chip, the semiconductor chip is flipped over, and the semiconductor chip is mounted on the multi-layer substrate while the electrode of the multi-layer substrate is caused to contact with the pillar of the semiconductor chip by solder. A heat sink is die-bonded to a back surface of the semiconductor chip. After those are sealed by mold-sealing, the heat sink is exposed by a procedure such as wafer backgrinding.
There may be a case where a semiconductor chip is inclined in flip-chip mounting. Further, there may also be a case where the semiconductor chip is inclined due to a fluid pressure in mold-sealing, a transverse stress in wafer backgrinding, an irresistible accident occurring in operation as a product, and so forth. There have been a case where the semiconductor chip is inclined, contact is not normally achieved between an electrode of a multi-layer substrate and a pillar of the semiconductor chip, and an opening condition of those occurs. Further, there have been a case where the pillar comes off from an electrode of the semiconductor or a contact defect occurs due to insufficient solder or the like.
The present disclosure has been made for solving the above-described problems, and an object thereof is to obtain a semiconductor device that can detect a contact defect between a multi-layer substrate and a semiconductor chip in a non-destructive manner.
A semiconductor device according to the present disclosure includes: a multi-layer substrate; and a semiconductor chip mounted on the multi-layer substrate by flip-chip mounting and having an internal circuit, wherein plural pads are formed on a front surface of the semiconductor chip, plural pillars are respectively formed on the plural pads, plural upper-surface electrodes are formed on an upper surface of the multi-layer substrate, plural lower-surface electrodes are formed on a lower surface of the multi-layer substrate and are respectively connected with the plural upper-surface electrodes via through holes, the plural pillars are joined to the plural upper-surface electrodes by solder, the plural pads include an electrode pad connected with the internal circuit and plural inspection pads formed in at least three parts in four corners on the front surface of the semiconductor chip and not connected with the internal circuit, and a line connects the adjacent inspection pads with each other.
In the present disclosure, the inspection pads are formed in at least three parts in four corners on the front surface of the semiconductor chip and the adjacent inspection pads are connected with each other by the lines. A check is made to a contacting part of each of the inspection pads. In a case where short-circuits are occurring in all of the contacting parts, it can be determined that the semiconductor chip is evenly mounted. In this case, it can be determined that the electrode pads are also in contact. Thus, a contact defect between the multi-layer substrate and the semiconductor chip can be detected in a non-destructive manner.
A semiconductor device according to the embodiments of the present disclosure will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted.
A heat sink 10 is die-bonded to a back surface of the semiconductor chip 5 by using an adhesive 9 such as a conductive resin. The multi-layer substrate 1, the semiconductor chip 5, and the heat sink 10 are sealed by a mold resin 11. An upper surface of the heat sink 10 is exposed from the mold resin 11 by a procedure such as wafer backgrinding. Heat produced in the semiconductor chip 5 is dissipated from the upper surface side of the heat sink 10. The lower-surface electrodes 3 of the multi-layer substrate 1 are exposed from the mold resin 11 and are used for inputs and outputs of signals with respect to an external portion.
As for such a molded product, an external appearance of the semiconductor chip 5 mounted by flip-chip mounting cannot be seen. Thus, a time might be needed for investigation of causes and decision about measures when a characteristic defect occurs. For a quick investigation of causes, it is important to distinguish a defect mode due to a circuit from a defect mode due to assembly. An example of a representative mode of a defect due to assembly is a contact defect between the upper-surface electrode 2 of the multi-layer substrate 1 and the pillar 7 of the semiconductor chip 5.
There may be a case where when flip-flop mounting is performed, the semiconductor chip 5 is mounted while being inclined due to a fluid pressure in mold-sealing, a transverse stress in wafer backgrinding, an irresistible accident occurring in operation as a product, and so forth.
On the upper surface of the multi-layer substrate 1, as the upper-surface electrodes 2, upper-surface electrodes 21a, 21b, and 21c are formed. On the lower surface of the multi-layer substrate 1, as the lower-surface electrodes 3, lower-surface electrodes 31a, 31b, and 31c are formed and are respectively connected with the upper-surface electrodes 21a, 21b, and 21c via the through holes 4 passing through the multi-layer substrate 1 in the up-down direction. The pillars 7 formed on the inspection pads 61a to 61c are respectively and individually connected with the upper-surface electrodes 21a, 21b, and 21c by the solder 8.
Each of a resistance value between the lower-surface electrodes 31a and 31b, a resistance value between the lower-surface electrodes 31b and 31c, and a resistance value between the lower-surface electrodes 31c and 31a is measured, and a check is made about whether an opening (open) or a short-circuit (short) is occurring to a contacting part of each of the inspection pads (open-short check). In a case where the resistance value is sufficiently low, it is assessed that a short-circuit is occurring. In a case where short-circuits are occurring in all of the contacting parts, it can be determined that the semiconductor chip 5 is evenly mounted. In this case, it can be determined that the electrode pads 6a to 6f are also in contact. Thus, a contact defect between the multi-layer substrate 1 and the semiconductor chip 5 can be detected in a non-destructive manner.
In a case where a thickness of the semiconductor chip 5 is 50 μm or smaller, the chip might be warped in a protruded shape when the front surface of the chip is up. In such a case, when the front and back surfaces are inverted, contact checks about three parts in the four corners of the semiconductor chip 5 are not sufficient, but contact checks about four parts are necessary.
For example, the open-short check is performed for the condition between the lower-surface electrodes 31b and 31c. In a case of a short-circuit, it can be determined that the pillars 7 of the electrode pads 6a and 6b arranged between the inspection pads 61b and 61c are in contact with the upper-surface electrodes 2 of the multi-layer substrate 1. Similarly, the open-short check is performed for the condition between the lower-surface electrodes 31a and 31b. In a case of a short-circuit, it can be determined that the pillar 7 of the electrode pad 6e arranged between the inspection pads 61a and 61b is in contact with the upper-surface electrode 2 of the multi-layer substrate 1. The open-short check is performed for the condition between the lower-surface electrodes 31c and 31d. In a case of a short-circuit, it can be determined that the pillar 7 of the electrode pad 6f arranged between the inspection pads 61c and 61d is in contact with the upper-surface electrode 2 of the multi-layer substrate 1.
An inspection pad 61e is formed in a central portion of the front surface of the semiconductor chip 5 and is connected with the inspection pad 61a by the line 13. The inspection pad 61e is not connected with the internal circuit 12 of the semiconductor chip 5. An upper-surface electrode 21e is connected with a lower-surface electrode 31e on the lower surface of the multi-layer substrate 1 via the through hole 4. The pillar 7 formed on the inspection pad 61e is connected with the upper-surface electrode 21e by the solder 8. Other configurations are similar to those of the second embodiment.
In a case where the thickness of the semiconductor chip 5 is 50 μm or smaller, the chip might be warped in a recessed shape when the front surface of the chip is up. In such a case, when the front and back surfaces are inverted, contact checks about the four corners of the semiconductor chip 5 are not sufficient, but a contact check about the central portion of the chip is necessary as well. For example, the open-short check is performed for the condition between the lower-surface electrodes 31a and 31e. In a case of a short-circuit, it can be determined that the pillar 7 of an electrode pad 6g arranged around the inspection pad 61e is in contact with the upper-surface electrode 2 of the multi-layer substrate 1.
In a normal action, the transistor 15 is turned on while a voltage Vc applied to the lower-surface electrode 32c is set to 0 V. In the contact check, the transistor 15 is turned off while the voltage Vc applied to the lower-surface electrode 32c is set to −5 V.
For example, in a case where the pillar 7 of the electrode pad 62a is not connected with the upper-surface electrode 22a, the S-parameter comes to a position (a) of “open”. In a case of normal connection, the S-parameter comes to a position (b) of a short-circuit. In a case where connection is incomplete and the resistance is high, the S-parameter moves to a position (b′) on an inner side because the resistance is observed to be higher than that in the position of a short-circuit.
Note that two inspection pads 62b and 62c are provided. Thus, even when a contact defect occurs to one of the inspection pads 62b and 62c, a contact condition of the electrode pad 62a can be inspected. In a case where contact defects occur to both of the inspection pads 62b and 62c, it can also be assessed that a defect is occurring regardless of a connection condition of the electrode pad 62a.
Here, a state where connection is incomplete is a state where joining is not achieved but contact is achieved by an external force or the like. It is assumed that a contact resistance value in such a case is several ohms. For example, it is premised that the resistances of the electrode pad 62a and the inspection pads 62b and 62c are 0Ω in a case where the connection is normal and are 2Ω in a case where the connection is incomplete, and the resistance value between the lower-surface electrode 32a and the lower-surface electrode 32c is thereby measured. Relationships among contact conditions of the pads and resistance values between the electrodes are indicated in Table 1. The resistance value becomes 0 or 1Ω in cases where the contact of the electrode pad 62a is normal, and the resistance value becomes 2 or 3Ω in cases where the contact is incomplete.
In a case where the contact condition is assessed as “short” when the low-frequency signal is input in the measurement 1, it is assessed that the contact of the electrode pad 62a is normal. Otherwise, a measurement 2 is conducted. In a case where the contact condition is assessed as “open” in the measurement 2, a measurement 3 is conducted. This situation is summarized in Table 2.
In the measurement 2, the lower-surface electrode 32b is grounded, the transistor 15 is turned on while the voltage Vc of the lower-surface electrode 32c is set to 0 V, a high-frequency signal is input to the lower-surface electrode 32b, and the one-port S-parameter measurement is thereby conducted. When the contact of either one of the inspection pads 62b and 62c is normal, characteristics of the internal circuit 12 are measured in the measurement 2. Consequently, the S-parameter changes between the measurement 1 and the measurement 2, and “open” of the electrode pad 62a is thereby confirmed. In a case where the contact conditions of both of the inspection pads 62b and 62c are “open”, because the contact condition is measured to be “open” in the measurement 2, the measurement 3 is conducted.
In a case where the electrode pad 62a is connected, the characteristics of the internal circuit 12 are measured in the measurement 3. As for cases where the applied voltages Vc of the lower-surface electrode 32c are −5 V and 0 V, differences in the S-parameter between a case where the connection of the electrode pad 62a is normal and a case where the connection is incomplete are in advance recognized by experiments or simulations. Accordingly, whether the connection of the electrode pad 62a is normal or incomplete can be assessed based on measurement results of the measurement 3.
As described above, in the present embodiment, on the front surface of the semiconductor chip 5, as the pads 6, the electrode pad 62a, the inspection pads 62b and 62c, and the control pad 62d are formed. The electrode pad 62a is connected with the internal circuit 12 via the transistor 15. The inspection pads 62b and 62c are connected with the electrode pad 62a by the respective lines 13. The control pad 62d is connected with the control terminal of the transistor 15. Accordingly, a contact defect between the multi-layer substrate 1 and the semiconductor chip 5 can be detected in a non-destructive manner.
On the front surface of the semiconductor chip 5, as the pads 6, a pad 63a and pads 63b and 63c, which are connected with the pad 63a by the line 13, are formed. The pad 63a is a DC supplying pad or an RF electrode pad which is connected with the internal circuit 12.
On the upper surface of the multi-layer substrate 1, as the upper-surface electrodes 2, an upper-surface electrode 23a and an upper-surface electrode 23b are formed, the upper-surface electrode 23a being connected with the pillar 7 formed on the pad 63a by the solder 8, the upper-surface electrode 23b being individually connected with the pillars 7 formed on the pads 63b and 63c by the solder 8.
On the lower surface of the multi-layer substrate 1, as the lower-surface electrodes 3, lower-surface electrodes 33a and 33b and lower-surface electrodes 33c and 33d are formed, the lower-surface electrodes 33a and 33b being individually connected with the upper-surface electrode 23a by the through holes 4, the lower-surface electrodes 33c and 33d being individually connected with the upper-surface electrode 23b by the through holes 4. Other configurations are similar to those of the first embodiment.
For example, a four-terminal resistance measurement is conducted by using the lower-surface electrodes 33c and 33b on an outer side as force terminal through which a current flow and by using the lower-surface electrodes 33a and 33d on an inner side as sensing terminals for measuring a voltage. The contact condition becomes “open” in a case of a contact defect and becomes “short” in a case of normal contact. Thus, a contact defect between the multi-layer substrate 1 and the semiconductor chip 5 can be detected in a non-destructive manner.
Because a difference in the resistance value between a case where solder connection of the pads is normal and a case where the solder connection is incomplete is insignificant, a contact resistance between an inspection apparatus and the lower-surface electrode disturbs an inspection. However, because no current flows through the sensing terminals, the contact resistance can be ignored. Thus, whether the connection is normal or incomplete can be discriminated by figuring out the difference in the resistance value between both of those cases.
As for a point different from the seventh embodiment, the pads 63a, 63b, and 63c are inspection pads which are not connected with the internal circuit 12 and are formed in at least three parts in the four corners on the front surface of the semiconductor chip 5. Other configurations are similar to those of the first and seventh embodiments.
A check is made about whether an opening or a short-circuit is occurring in the contacting part of the inspection pad in each of the parts. In a case where short-circuits are occurring in all of the contacting parts, it can be determined that the semiconductor chip 5 is evenly mounted. In this case, it can be determined that electrode pads are also in contact. Thus, a contact defect between the multi-layer substrate 1 and the semiconductor chip 5 can be detected in a non-destructive manner. Note that the pads 63a, 63b, and 63c may be formed in four corners on the front surface of the semiconductor chip 5 or may be formed in central portions of the semiconductor chip 5.
Although the preferred embodiments and the like have been described in detail above, the present disclosure is not limited to the above-described embodiments and the like, but the above-described embodiments and the like can be subjected to various modifications and replacements without departing from the scope described in the claims. Aspects of the present disclosure will be collectively described as supplementary notes.
A semiconductor device comprising:
The semiconductor device according to Supplementary Note 1, wherein the plural inspection pads include first to fourth inspection pads formed in four corners on the front surface of the semiconductor chip.
The semiconductor device according to Supplementary Note 1 or 2, wherein the plural inspection pads include a fifth inspection pad formed in a central portion of the front surface of the semiconductor chip.
The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein a resistance is connected between the adjacent inspection pads.
The semiconductor device according to Supplementary Note 2, further comprising a printed substrate on which the multi-layer substrate is mounted,
A semiconductor device comprising:
A semiconductor device comprising:
The semiconductor device according to Supplementary Note 7, wherein the semiconductor chip has an internal circuit, and
The semiconductor device according to Supplementary Note 7, wherein the semiconductor chip has an internal circuit, and
The semiconductor device according to Supplementary Note 9, wherein the first and second pads are formed in the four corners on the front surface of the semiconductor chip.
The semiconductor device according to Supplementary Note 9 or 10, wherein the first and second pads are formed in a central portion of the front surface of the semiconductor chip.
The semiconductor device according to any one of Supplementary Notes 1 to 11, comprising a heat sink die-bonded to a back surface of the semiconductor chip, and a mold resin sealing the multi-layer substrate, the semiconductor chip, and the heat sink,
Obviously many modifications and variations of the present disclosure are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.
The entire disclosure of Japanese Patent Application No. 2023-064244, filed on Apr. 11, 2023 including specification, claims, drawings and summary, on which the convention priority of the present application is based, is incorporated herein by reference in its entirety.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-064244 | Apr 2023 | JP | national |
