Semiconductor device

Abstract

A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view, illustrating a configuration of a semiconductor device in an embodiment;

FIG. 2 is a cross-sectional view, illustrating a configuration of a semiconductor device in an embodiment;

FIG. 3 is a cross-sectional view, illustrating a configuration of a semiconductor device in an embodiment;

FIGS. 4A and 4B are diagrams, illustrating a configuration of a semiconductor device in an embodiment;

FIGS. 5A and 5B are diagrams, illustrating a configuration of a semiconductor device in an embodiment;

FIGS. 6A and 6B are diagrams, illustrating a configuration of a semiconductor device in an embodiment;

FIGS. 7A and 7B are diagrams, illustrating a configuration of a semiconductor device in an embodiment;

FIGS. 8A and 8B are diagrams, illustrating a configuration of a semiconductor device in an embodiment;

FIGS. 9A and 9B are diagrams, illustrating a configuration of a semiconductor device in an embodiment;

FIGS. 10A and 10B are diagrams, illustrating a configuration of a semiconductor device in an embodiment;

FIG. 11 is a cross-sectional view, illustrating a configuration of a conventional semiconductor device;

FIGS. 12A and 12B are diagrams, illustrating a configuration of a conventional semiconductor device;

FIG. 13 is a cross-sectional view, illustrating a configuration of a conventional semiconductor device;

FIG. 14 is a cross-sectional view, illustrating a configuration of a conventional semiconductor device;

FIG. 15 is a cross-sectional view, illustrating a configuration of a conventional semiconductor device; and

FIG. 16 is a cross-sectional view, illustrating a configuration of a semiconductor device in an embodiment.

Claims

1. A semiconductor device, comprising: a semiconductor substrate;an insulating interlayer provided on said semiconductor substrate;a multiple-layered interconnect embedded in said insulating interlayer;an electrode pad, provided so as to be opposite to an upper surface of an uppermost layer interconnect in said multiple-layered interconnect and having a bump electrode for an external coupling mounted thereon; anda capacitance insulating film provided between said uppermost layer interconnect and said electrode pad,wherein said semiconductor device includes a capacitor element, which is composed of said uppermost layer interconnect, said capacitance insulating film and said electrode pad.

2. The semiconductor device according to claim 1, further comprising a bump electrode joined to said electrode pad.

3. The semiconductor device according to claim 1, further comprising a first insulating film covering an upper portion of said insulating interlayer, wherein said first insulating film is provided with a concave portion in a region opposite to an upper surface of said uppermost layer interconnect, andwherein said electrode pad is provided so as to cover an interior wall of said concave portion and to extend to outside of said concave portion.

4. The semiconductor device according to claim 3, wherein a thickness of said first insulating film is reduced in the region where said concave portion is formed,and said first insulating film in a region having a reduced thickness constitutes said capacitance insulating film.

5. The semiconductor device according to claim 4, wherein said first insulating film is an organic resin film.

6. The semiconductor device according to claim 3, wherein said concave portion is a through hole extending through said first insulating film,said semiconductor device has a second insulating film covering an interior wall of said through hole, andwherein said electrode pad is provided on said second insulating film.

7. The semiconductor device according to claim 6, wherein said second insulating film is a high dielectric constant film.

8. The semiconductor device according to claim 1, wherein said uppermost layer interconnect that constitutes said capacitor element is a power supply interconnect or a grounding interconnect.

9. The semiconductor device according to claim 1, wherein said uppermost layer interconnect constituting said capacitor element is a signal interconnect.

10. The semiconductor device according to claim 1, further comprising a substrate, which is flip-bonded with said semiconductor substrate, wherein said electrode pad is coupled to a power supply interconnect or a grounding interconnect provided in said substrate.

11. The semiconductor device according to claim 1, wherein said uppermost layer interconnect and said electrode pad, which constitute said capacitor element, are coupled to different power supply potentials, respectively.

12. The semiconductor device according to claim 1, wherein said uppermost layer interconnect that is opposite to one of said electrode pads includes a first uppermost layer interconnect and a second uppermost layer interconnect, wherein said electrode pad and said first uppermost layer interconnect constitute a first capacitor element, andwherein said electrode pad and said second uppermost layer interconnect constitute a second capacitor element.

13. The semiconductor device according to claim 1, wherein said uppermost layer interconnect that is opposite to one of said electrode pads includes a first uppermost layer interconnect and a second uppermost layer interconnect,wherein said electrode pad and said first uppermost layer interconnect constitute said capacitor element, andwherein said electrode pad is electrically coupled to said second uppermost layer interconnect.