Claims
- 1. A semiconductor integrated circuit device comprising:a clock-generating circuit that includes a variable delay circuit for producing second clock signals by delaying, by a predetermined delay time, first clock signals that are formed based upon clock signals input through an external terminal, and a control circuit for comparing the phase of third clock signals formed based on the second clock signals with the phase of the first clock signals and for so controlling the delay time that the difference between the phases is decreased; and an internal circuit that operates in response to the second clock signals; which are formed on a common semiconductor substrate; wherein an element-forming region constituting the variable delay circuit is isolated from an element-forming region constituting the internal circuit; and wherein the control circuit includes a frequency-dividing circuit that divides the frequencies of the first clock signals and of the second clock signals.
- 2. A semiconductor integrated circuit device comprising:a clock-generating circuit that includes a variable delay circuit for producing second clock signals by delaying, by a predetermined delay time, first clock signals that are formed based upon clock signals input through an external terminal, and a control circuit for comparing the phase of third clock signals formed based on the second clock signals with the phase of the first clock signals and for so controlling the delay time that the difference between the phases is decreased; and an internal circuit that operates in response to the second clock signals; which are formed on a common semiconductor substrate; wherein an element-forming region constituting the variable delay circuit is isolated from an element-forming region constituting the internal circuit; and wherein: the delay time is controlled by an analog voltage; the control circuit includes a first frequency-dividing circuit for forming fifth clock signals by dividing the frequency of the first clock signals, a second frequency-dividing circuit for forming sixth clock signals by dividing the frequency of the third clock signals, and a phase comparator circuit for producing control signals by comparing the phase of the fifth clock signals with the phase of the sixth clock signals, and a charge pump circuit that generates the analog voltage based upon the control signals; and wherein the fifth and sixth signals assume predetermined initial values when the clock-generating circuit is in operation.
Priority Claims (1)
Number |
Date |
Country |
Kind |
11-243154 |
Aug 1999 |
JP |
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CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a division of U.S. Application No. 10/036,374 filed Jan. 7, 2002, which is a continuation of U.S. Application No. 09/629,173 filed Jul. 31, 2000 now U.S. Pat No. 6,377,511.
US Referenced Citations (27)
Foreign Referenced Citations (6)
Number |
Date |
Country |
2-90666 |
Mar 1990 |
JP |
10-171774 |
Jun 1998 |
JP |
11-55145 |
Feb 1999 |
JP |
2000-124796 |
Apr 2000 |
JP |
2000-183730 |
Jun 2000 |
JP |
2000-188540 |
Jul 2000 |
JP |
Non-Patent Literature Citations (1)
Entry |
Johnson et al., “A Variable Delay Line PLL for CPU-Coprocessor Synchronization”, IEEE Journal of Solid-State Circuits, vol. 23, No. 5, pp. 1218-1223, Oct. 1998. |
Continuations (1)
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Number |
Date |
Country |
Parent |
09/629173 |
Jul 2000 |
US |
Child |
10/036374 |
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US |