Embodiments described herein relate to a semiconductor memory device.
In a manufacturing step of a semiconductor memory device, for example, in a manufacturing step of a NAND type flash memory, there has been known a case where a thickness of an element separating insulating film or a film formed on a semiconductor substrate is etched away during the formation of a contact structure between adjacent gate electrodes. When a film of a different material than the underlying material is formed on the underlying exposed surface, such as an element forming region of a semiconductor substrate, the differences in the internal stresses of the materials, and their coefficients of thermal expansion, can cause delamination of the contact from the underlying element forming region. Additionally, if an insulating material is formed on a proportion of the element forming region, the resistance between the contact and the element forming region is increased, leading to erratic performance of a resulting semiconductor device or even non-operability thereof.
In general, according to an embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of NAND strings each of which includes a plurality of memory cells provided on the semiconductor substrate and disposed in a first direction, and a select gate provided adjacent to the memory cell at an end portion of the plurality of memory cells, such that two select gates face each other at the ends of their respective memory cells, and a first spacer layer formed on a side wall between the select gates of the NAND strings disposed adjacent to each other. The first spacer layer includes a recess therein at the portion thereof located adjacent to the semiconductor substrate.
Hereinafter, the explanation is made with respect to an embodiment where a NAND type flash memory device is used as a semiconductor memory device with reference to the drawings. In the explanation made hereinafter, elements having identical functions or identical configurations are given the reference numerals or letters. The drawings are schematic views and hence, the relationship between thicknesses and sizes in a plane, a ratio of the thicknesses of the respective layers and the like, are not always equal to those of an actual semiconductor memory device. Further, also with respect to the directions (“up”, “down”, “left” and “right”), these directions are the relative directions when a circuit forming surface side of a semiconductor substrate described later is set as an upper side, and these directions do not always agree with directions determined with reference to the direction of gravitational acceleration. In the explanation made hereinafter, for the sake of convenience of the explanation, an XYZ orthogonal coordinate system is used. In such an orthogonal coordinate system, two directions which are parallel to a surface of a semiconductor substrate and are orthogonal to each other are assumed as the X direction and the Y direction. The direction orthogonal to both the X direction and the Y direction is assumed to be the Z or “up” direction.
The configuration of a NAND type flash memory device is explained with reference to
As shown in
Each of the plurality of unit memory cells UC includes: a NAND string including a plurality of memory cells MC connected in series; and two selector gate transistors STD, STS which are connected to both ends of the NAND string respectively. One end of the unit memory cell UC is connected to bit lines BL1, BL2, . . . , BLm respectively. The bit lines BL1, BL2, . . . , BLm are connected to a sense amplifier (not shown in the drawing). The other ends of the unit memory cells UC are connected to a source line SL in common. Hereinafter, “BL1, BL2, . . . ” are used when individual bit lines BL are to be indicated, and “BL” is used when bit lines are to be indicated without specifying individual bit lines.
The unit memory cell UC includes the plurality of memory cells MC. A gate electrode of each memory cell MC is electrically connected to a word line WL. A control line SGD in each unit memory cell UC is electrically connected to a gate electrode of the select gate transistor STD on a drain side (on a side connected to the bit line) thereof. A control line SGS in each unit memory cell is electrically connected to a gate electrode of the select gate transistor STS on a source line side thereof (on a side connected to the source line).
As shown in
The memory cell MC is disposed at an intersection of the word line WL and the bit line BL. The select gate transistor STD is disposed at an intersection of the bit line BL and the control line SGD, and the select gate transistor STS is disposed at an intersection of the bit line BL and the control line SGS. A bit line contact BLC is disposed on the bit line BL between the control lines SGD of the blocks BK1, BK2 disposed adjacent to each other.
In
The memory gate MG of the memory cell transistor MT is formed by stacking an electric charge storage layer 14, an inter-electrode insulating film 15, and a control gate electrode 18 on agate insulating film 12 in this order. The gate insulating film 12 is a silicon oxide film, for example. The electric charge storage layer 14 is formed of a first polycrystalline silicon film 20 into which a dopant is implanted, for example. For example, boron is implanted into the first polycrystalline silicon film 20 as a dopant so that a conductive type of the first polycrystalline silicon film 20 is a p type.
The inter-electrode insulating film 15 is formed of an ONO (oxide-nitride-oxide) film, an NONON (nitride-oxide-nitride-oxide-nitride) film, an insulating film having high dielectric constant or the like, for example. The control gate electrode 18 is formed of a multilayer film including a second polycrystalline silicon film 22 doped with a dopant and a metal film 24 made of tungsten or the like. For example, boron is implanted into the second polycrystalline silicon film 22 as a dopant so that a conductive type of the second polycrystalline silicon film 22 is a p type. The electric charge storage layer 14 and the control gate electrode 18 are insulated from each other by the inter-electrode insulating film 15.
The memory cell transistor MT includes the memory gates MG formed on the semiconductor substrate 10. The select gate transistor STD is disposed adjacent to the memory cell transistor MT positioned at one end of the unit memory cell UC, i.e., at the end of a NAND string.
The select gate electrode SG of the select gate transistor STD has a film layer structure substantially the same as the film layer structure of the memory gate MG of the memory cell transistor MT. The select gate electrode SG has the structure where the first polycrystalline silicon film 20, the inter-electrode insulating film 15, the second polycrystalline silicon film 22 and the metal film 24 are layered on the gate insulating film 12. The first polycrystalline silicon film 20 is a film corresponding to the electric charge storage layer 14 in the memory gate MG (hereinafter referred to as “lower electrode film 46”), and the second polycrystalline silicon film 22 and the metal film 24 are films corresponding to the control gate electrode 18 in the memory gate MG (hereinafter referred to as “upper electrode film 48”).
For example, boron is implanted into the first polycrystalline silicon film 20 and the second polycrystalline silicon film 22 as a dopant as described above so that a conductive type of the first polycrystalline silicon film 20 and the second polycrystalline silicon film 22 is a p type. The upper electrode film 46 and the lower electrode film 48 are connected to each other through an opening portion 25 formed in the inter-electrode insulating film 15 so that the upper electrode film 46 and the lower electrode film 48 are brought into an electrically connected state. Due to such a configuration, the select gate transistor STD functions as a normal transistor. A first cap insulating film 26 and a second cap insulating film 28 are formed on the metal film 24. A silicon nitride film may be used as the first cap insulating film 26, for example. A silicon oxide film may be used as the second cap insulating film 28, for example.
A source/drain region (not shown in the drawing) is formed on a surface layer of the semiconductor substrate 10 at a position between the memory gates MG and a position between the memory gate MG and the selection gate electrode SG. For example, phosphorus is implanted into the source/drain region as a dopant.
A source/drain region (not shown in the drawing) having the LDD (lightly doped drain) structure is formed on the front layer of the semiconductor substrate 10 at a position between the select gate electrodes SG disposed adjacent to each other.
An air gap AG is formed between the memory gates MG and between the memory gate MG and the select gate electrode SG. A first insulating film 29 is formed over the memory gates MG, the select gate electrode SG and the air gaps AG such that the first insulating film 29 covers the air gaps AG from above. A second insulating film 30 is formed on the first insulating film 29. The first insulating film 29 and the second insulating film 30 are formed of a silicon oxide film, for example. A third insulating film 31 is formed so as to cover an upper surface of the second insulating film 30, side surfaces of the second insulating film 30, side surfaces of the first insulating film 29 and side surfaces of the select gate electrode SG. The third insulating film 31 is formed of a silicon oxide film, for example.
A side wall insulating film 32 is formed on the portion of the third insulating film 31 on the side surface of the select gate electrodes SG on a side where the select gate electrodes SG face each other, that is, on a side where the air gaps AG are not formed. The side wall insulating film 32 is formed of a silicon oxide film, for example. A first liner film 34 and a second liner film 36 are formed so as to cover the second insulating film 30, the third insulating film 31 and the side wall insulating film 32.
The side wall insulating film 32 is formed on only a portion of the side surface of the select gate electrode SG. The side wall insulating film 32 is not formed on a lower portion of the side surface of the select gate electrode SG, such that a space exists between the lowest surface of the side wall insulating film 32 and the adjacent surface of the third insulating film 31. The first liner film 34 is formed so as to cover a surface of the side wall insulating film 32 and the exposed surface of the selection gate electrode SG between the lowest surface of the side wall insulating film 32 and the adjacent surface of the third insulating film 31. The side wall insulating film 32 and the first liner film 34 are collectively referred to as a first spacer 38. A silicon oxide film having film quality with lower density may be used as the side wall insulating film 32, for example. A silicon oxide film having film quality with higher density may be used as the first liner film 34, for example.
A surface of the first spacer 38 is further covered with a second liner film 36. The second liner film 36 is referred to as a second spacer 39. The second liner film 36 is formed of a silicon nitride film, for example.
An interlayer insulating film 40 is formed on the second liner film 36 such that the interlayer insulating film 40 is filled in a recessed portion (trench portion) between the select gate electrodes SG, and it overlies the memory gates MG and an upper surface of the select gate electrode SG. Contact plugs 42 are formed such that each contact plug 42 extends through the interlayer insulating film 40 from an upper portion to a lower portion thereof, further extends through the second liner film 36, the first liner film 34 and the third insulating film 31, and reaches the semiconductor substrate 10 in a region adjacent to the select gate electrode SG. The contact plug 42 is formed of a layered film including a barrier film 42a and a metal film 42b, and a silicide layer is formed at an interface between the contact plug 42 and the semiconductor substrate 10.
In this embodiment, as described hereinafter, on the side surface of the select gate electrode SG, the first spacer 38 (the multilayer film including the side wall insulating film 32 and the first liner film 34) is further divided into two portions. That is, a portion of the first spacer 38 which corresponds to the side wall of the select gate electrode SG and on which the side wall insulating film 32 and the first liner film 34 are layered is referred to as a first portion P1. On the side surface of the select gate electrode SG, a portion of the first spacer 38 where the side wall insulating film 32 is not formed on the side wall of the selection gate electrode SG, that is, the portion of the first spacer 38 disposed below the side wall insulating film 32 where the first spacer 38 is formed of a single layer of the first liner film 34 is referred to as a second portion P2. Assume a height of the second portion P2 as “H”. The height H of the second portion P2 is a distance from an upper surface of the third insulating film 31 to a lower surface of the side wall insulating film 32 in the second portion P2. The lower surface of the side wall insulating film 32 is located at a position higher than an upper surface of the semiconductor substrate 10.
The first spacer 38 forms a recessed shape (it is indented) in the lateral direction (Y direction in the drawing). Such a recessed portion has a U-shape, for example. The first portion P1 of the first spacer 38 is formed of a layered film including the side wall insulating film 32 and the first liner film 34. The second portion P2 of the first spacer 38 is formed of a single-layered film of the first liner film 34. Accordingly, a film thickness (width) T1 of the first portion P1 of the first spacer 38 in the lateral direction (Y direction in the drawing) is larger than a film thickness (width) T2 of the second portion P2 of the first spacer 38 in the lateral direction (Y direction in the drawing).
Next, a method of manufacturing the NAND type flash memory device according to the embodiment is explained with reference to
Firstly, as shown in
The first insulating film 29 is formed on the memory gates MG and the select gate electrodes SG. The first insulating film 29 is formed of a silicon oxide film, for example. The first insulating film 29 may be formed by a CVD method under a low step coverage condition, for example. Accordingly, the first insulating film 29 may be formed so as to cover upper portions of the memory gates MG and the selection gate electrode SG without filling into spaces formed between the memory gates MG and spaces formed between the memory gate MG and the select gate electrode SG and hence, air gaps AG may be formed. The air gap AG is formed between the memory gates MG and between the memory gate MG and the select gate electrode SG. Next, the second insulating film 30 is formed. The second insulating film 30 is formed of a silicon oxide film, for example. The silicon oxide film may be formed by a CVD method, for example. Next, the films are processed by a lithography method and an RIE method such that the select gate electrodes SG located adjacent to each other are separated from each other. In such a step, the films ranging from the second insulating film 30 to the first polycrystalline silicon film 20 are removed in regions corresponding to spaces between the selection gate electrodes SG. Next, a third insulating film 31 is formed. The third insulating film 31 is formed of a silicon oxide film, for example. The silicon oxide film may be formed by a CVD method, for example. The structure shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
As has been explained above, according to this embodiment, during etching of the side wall insulating film 32 explained with reference to
Accordingly, in the etching, it is possible to prevent the formation of an etched recess (indentation) on surfaces of the element separation regions Sb (element separating insulating films 44) during etching of the sidewall insulation film 32. Accordingly, it is possible to prevent the occurrence of a state where the third liner film 36 or the like is formed in a recess in the element separation regions Sb so that a stress is generated whereby crystal defects occur in the semiconductor substrate 10.
Further, it is possible to prevent a phenomenon that the surface of the semiconductor substrate 10 in the element regions Sa are recessed due to etching of the semiconductor substrate 10 (element region Sa) during etching of the sidewall insulation film 32. If this were to occur, the first liner film 34 would contact and directly contact and cover the element region Sa, and when the contact holes are etched based on a time of etching, the contact hole may not penetrate the first liner film 34 and second liner film 36 and an open circuit defect will occur because the contact plug 42 will not contact the element region Sa, but have an insulator disposed between the base of the contact plug and the element region Sa. Accordingly, the occurrence of an open-circuit defect at the contact plug 42 may be prevented. It is also possible to prevent the surface of the semiconductor substrate 10 from being damaged due to etching. Accordingly, in forming a silicide layer at a lower portion of the contact plug 42, it is possible to prevent silicide from being formed abnormally and hence, it is possible to prevent the occurrence of a leakage or an open circuit at the contact.
In this case, as shown in
In the above-mentioned embodiment, an example where the present disclosure is applied to the NAND type flash memory device is described. However, the present disclosure is also applicable to a semiconductor memory device such as an NOR type flash memory device or an EPROM, a semiconductor memory device such as a DRAM or an SRAM, or a logic semiconductor device such as a microcomputer besides the NAND type flash memory device.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modification as would fall within the scope and spirit of the inventions.
This application is based upon and claims the benefit of priority from U.S. Provisional Patent Application No. 61/981,453, filed Apr. 18, 2014, the entire contents of which are incorporated herein by reference.
Number | Date | Country | |
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61981453 | Apr 2014 | US |