Patent Application
20250029913
This application claims priority to Korean Patent Application No. 10-2023-0092989, filed in the Korean Intellectual Property Office on Jul. 18, 2023, the disclosure of which is incorporated by reference herein in its entirety.
The present disclosure relates generally to a semiconductor package and a manufacturing method thereof.
When bonding a plurality of semiconductor chips, or bonding a semiconductor chip and a substrate, in a semiconductor package process, a process for directly connecting pads to each other without solder balls or solder bumps has been developed as a pitch between bonding pads narrows.
Hybrid bonding is to bond a plurality of semiconductor chips, or a semiconductor chip and a substrate, using the property of combining the same materials, and an input/output (I/O) with a fine pitch may be formed by the hybrid bonding.
In the hybrid bonding process, because pads have to contact with pads, and insulation layers have to contact with insulation layers, to form a bonding interface, it may be important to accurately align the bonding surfaces of the plurality of semiconductor chips (or substrates).
One or more example embodiments provide a semiconductor package including a structure that can improve reliability of a bonding process, and a manufacturing method thereof. In particular, according to one or more example embodiments, a connection pad of an upper semiconductor chip and a connection pad of a lower semiconductor chip may be different from each other in size, thereby assuring an align margin during hybrid bonding between both semiconductor chips, and accordingly, the reliability of the bonding process may be improved.
According to an aspect of an example embodiment, a semiconductor package includes: a first semiconductor chip comprising: a first semiconductor layer; a first connection pad provided on a surface of the first semiconductor layer, and a first insulation layer provided on the surface of the first semiconductor layer, the surface of the first semiconductor layer extending in a first direction; and a second semiconductor chip comprising: a second semiconductor layer; a second connection pad provided on a surface of the second semiconductor layer; and a second insulation layer provided on the surface of the second semiconductor layer, wherein the first connection pad directly contacts the second connection pad, wherein the first connection pad is provided on the second connection pad in a second direction that is perpendicular to the first direction, wherein the first insulation layer directly contacts the second insulation layer, wherein the first insulation layer is provided on the second insulation layer in the second direction, and wherein a width of the second connection pad in the first direction is smaller than a width of the first connection pad in the first direction.
According to an aspect of an example embodiment, a semiconductor package includes: an interposer; a logic die provided on the interposer; and a high bandwidth memory provided on the interposer, wherein the high bandwidth memory comprises: a buffer die; a first semiconductor chip that is provided on the buffer die, the first semiconductor chip comprising: a first semiconductor layer; a first connection pad provided on a surface of the first semiconductor layer; and a first insulation layer provided on the surface of the first semiconductor layer, the surface of the first semiconductor layer extending in a first direction; and a second semiconductor chip comprising: a second semiconductor layer; a second connection pad provided on a surface of the second semiconductor layer; and a second insulation layer provided on the surface of the second semiconductor layer, wherein the first connection pad directly contacts the second connection pad, wherein the first connection pad is provided on the second connection pad in a second direction that is perpendicular to the first direction, wherein the first insulation layer directly contacts the second insulation layer, wherein the first insulation layer is provided on the second insulation layer in the second direction, and wherein the semiconductor package comprises a molding member that is provided on the buffer die and that molds the first semiconductor chip and the second semiconductor chip.
According to an aspect of an example embodiment, a method of manufacturing a semiconductor package, the method comprising: forming a first semiconductor chip comprising: a first semiconductor layer; a first connection pad provided on a surface of the first semiconductor layer, and a first insulation layer provided on the surface of the first semiconductor layer, the surface of the first semiconductor layer extending in a first direction; forming a second semiconductor chip comprising: a second semiconductor layer; a second connection pad provided on a surface of the second semiconductor layer, a second insulation layer provided on the surface of the second semiconductor layer; and bonding the first semiconductor chip and the second semiconductor chip such that the first connection pad and the second connection pad directly contact and the first insulation layer and the second insulation layer directly contact, wherein a width of the second connection pad in the first direction is smaller than a width of the first connection pad in the first direction.
The above and other aspects and features will be more apparent from the following description of one or more example embodiments taken in conjunction with the accompanying drawings, in which:
Hereinafter, example embodiments will be described in detail with reference to accompanying drawings. The present disclosure may be implemented in a number of different forms and is not limited to the example embodiments described herein.
In the following description, parts irrelevant to the description have been omitted, and the same reference numerals are used for the same or similar constituent elements throughout the specification.
In addition, the size and thickness of each component shown in the drawings are arbitrarily represented for the convenience of description, and thus embodiments of the disclosure are not necessarily limited to the drawings. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. In addition, in the drawings, for convenience of explanation, the thickness of some layers and regions are exaggerated.
It will be apparent that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, the element can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, throughout the specification, the word “on” a target element may mean positioned above or below the target element, and may not necessarily be understood to mean positioned “at an upper side” based on an opposite to a gravity direction.
In addition, unless explicitly described to the contrary, the word “comprise”, and variations such as “comprises” or “comprising” may imply the inclusion of stated elements but not the exclusion of any other elements.
Further, throughout the specification, the phrase “on a plane” may mean viewing a target portion from the top, and the phrase “on a cross-section” may mean viewing a cross-section formed by vertically cutting a target portion from the side.
Hereinafter, a semiconductor package according to example embodiments will be described with reference to the drawings.
Referring to
The semiconductor chip stacking structure 101 may have a structure in which a plurality of semiconductor chips 100A, 100B, 100C, and 100D are stacked in one direction (e.g., a second direction DR2). The semiconductor chip stacking structure 101 may be disposed on the bottom die 180. In one or more example embodiments, the bottom die 180 may have a larger width than the semiconductor chip stacking structure 101 in a first direction DR1.
In one or more example embodiments, the semiconductor package 100 may include a high bandwidth memory (HBM). According to one or more example embodiments, each of the plurality of semiconductor chips 100A, 100B, 100C, and 100D stacked in the semiconductor chip stacking structure 101 may be a memory chip (e.g., DRAM), and the bottom die 180 may be a buffer die. In the following one or more example embodiments, it will be exemplarily described that the semiconductor package 100 includes the HBM, but one or more example embodiments are not limited to the HBM.
The semiconductor chip stacking structure 101 and the bottom die 180 may be bonded by hybrid bonding. Each of the semiconductor chips 100A, 100B, 100C, and 100D included in the semiconductor chip stacking structure 101 may be bonded to each other by hybrid bonding. Hybrid bonding may be performed by a bonding portion included in each of the semiconductor chips 100A, 100B, 100C, and 100D or the bottom die 180. The bonding portion may be a portion where each of the semiconductor chips contacts each other in the case that the plurality of semiconductor chips 100A, 100B, 100C, and 100D are stacked and connected to each other. Alternatively, the bonding portion may be a portion where the semiconductor chip and the bottom die 180 contact each other when any one of the plurality of semiconductor chips 100A, 100B, 100C, and 100D and the bottom die 180 are connected to each other.
Hybrid bonding is a method of fusing the same materials of two devices by using the bonding properties of the same materials to bond two devices. For example, in the bonding portion, hybrid bonding may mean that two devices are bonded to each other through metal-metal bonding and non-metal-non-metal bonding. According to hybrid bonding, an I/O with a fine pitch may be formed. Specifically, when two semiconductor chips are bonded to each other, a bonding portion of each semiconductor chip may include one or more metal pads and an insulation layer adjacent to the metal pad. According to one or more example embodiments, in the bonding portion, a metal pad may be bonded between metal pads, and an insulation layer may be bonded between insulation layers.
In one or more example embodiments, an upper semiconductor chip and a lower semiconductor chip may each include metal pads with different widths. In one or more example embodiments, the upper semiconductor chip and the lower semiconductor chip may each include insulation layers having different widths. In one or more example embodiments, the contact surface of the metal pad and the contact surface of the insulation layer may be positioned in different layers.
The molding member 191 may be disposed on the bottom die 180 and may mold the semiconductor chip stacking structure 101. The molding member 191 may serve to protect and insulate the semiconductor chip stacking structure 101. In one or more example embodiments, the molding member 191 may comprise a thermosetting resin such as epoxy resin. In one or more example embodiments, the molding member 191 may comprise an epoxy molding compound (EMC). In one or more example embodiments, the molding process with the molding member 191 may include a compression molding or transfer molding process.
The dummy silicon layer 192 may be configured to radiate heat generated within the high bandwidth memory to the outside. The dummy silicon layer 192 may include crystalline silicon. The thermal conductivity of silicon may have a value greater than that of molding member 190. Heat generated in the high bandwidth memory may be effectively dissipated by the dummy silicon layer 192 comprising silicon.
For example,
The first semiconductor chip 100A may be connected to the second semiconductor chip 100B using a flip chip method. For example, in
Referring to
The first semiconductor layer 110a may include a compound semiconductor such as, for example, a semiconductor device such as silicon (Si) or germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The first semiconductor layer 110a may have a silicon-on insulator (SOI) structure. The first semiconductor layer 110a may include an active region, for example, an impurity doped well, or an impurity doped structure. The first semiconductor layer 110a may include various device isolation structures such as a shallow trench isolation (STI) structure. According to one or more example embodiments, the first semiconductor layer 110a may include one or more separate semiconductor device (e.g., a transistor) at a position adjacent to the interconnection structure 120a.
The interconnection structure 120a may be disposed on the first semiconductor layer 110a. The interconnection structure 120a may include a wiring layer 121a and an wiring insulation layer 122a surrounding the wiring layer 121a. The wiring layer 121a may include a multi-layer structure including wiring patterns and vias. According to one or more example embodiments, the wiring layer 121a may further include a thick top metal (TTM). The wiring patterns and the vias included in the wiring layer 121a may include a metal material. For example, the wiring patterns and the vias may include copper (Cu), aluminum (AI), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or at least two or more alloys thereof. The wiring insulation layer 122a may include an insulating material. For example, the wiring insulation layer 122a may include an insulating material such as silicon oxide, silicon nitride, insulating polymer, or a combination thereof. The wiring layer 121a may connect individual semiconductor devices included in a first through electrode 140a and a first semiconductor layer 110a with a first connection pad 131a disposed on the upper surface of the first semiconductor chip 100A through the wiring patterns and vias.
A first connection pad 131a and a lower insulation layer 133a surrounding the side of the first connection pad 131a may be disposed on the interconnection structure 120a. The first connection pad 131a may directly contact the second connection pad 131b included in the second semiconductor chip 100B in the vertical direction (e.g., second direction DR2). The lower insulation layer 133a may prevent the plurality of first connection pads 131a disposed on the interconnection structure 120a from contacting each other and may insulate the plurality of first connection pads 131a from each other. The lower insulation layer 133a may include an insulating material. For example, the lower insulation layer 133a may include an insulating material such as silicon oxide, silicon nitride, insulating polymer, or a combination thereof.
The upper insulation layer 134a may be disposed on the lower insulation layer 133a. In one or more example embodiments, an upper surface (i.e., a surface contacting the second insulation layer 132b) of the upper insulation layer 134a may be formed at a layer of a different height from an upper surface of the first connection pad 131a (i.e., a surface in contact with the second connection pad 131b). That is, the upper insulation layer 134a may be protruded in the opposite direction of the second direction DR2 based on the upper surface of the lower insulation layer 133a and/or first connection pad 131a. That is, the upper surface of the first connection pad 131a may be disposed in a concave portion in the second direction DR2 from the upper surface of the upper insulation layer 134a. In one or more example embodiments, a width of the upper insulation layer 134a in the horizontal direction (e.g., first direction DR1) may gradually decrease as it moves toward the vertical direction (e.g., the opposite direction of the second direction DR2). In one or more example embodiments, an edge of a portion adjacent to the second connection pad 131b of the upper insulation layer 134a may have a round shape. In one or more example embodiments, the upper insulation layer 134a may be formed in a subsequent process after the first connection pad 131a and the lower insulation layer 133a are formed. The upper insulation layer 134a may include an insulating material such as silicon oxide, silicon nitride, insulating polymer, or a combination thereof. The upper insulation layer 134a may directly contact the second insulation layer 132b included in the second semiconductor chip 100B in the vertical direction.
The first through electrode 140a may penetrate the first semiconductor layer 110a in the vertical direction (e.g., second direction DR2). The through electrodes 140a and 140b may be formed by drilling thousands of fine holes vertically penetrating each of the semiconductor chip 100A and 100B, filling the holes with conductive material, and connecting them to electrodes. Holes of the through electrodes 140a and 140b may be formed by deep etching. In one or more example embodiments, the holes of the through electrodes 140a and 140b may be formed by laser. The through electrodes 140a and 140b may include a conductive plug and a barrier layer surrounding the conductive plug. In one or more example embodiments, the holes of the through electrodes 140a and 140b may be filled by electrolytic plating. In one or more example embodiments, the conductive plugs of the through electrodes 140a and 140b may include at least one of tungsten (W), aluminum (AI), copper (Cu), and alloys thereof. The barrier layer may contain at least one of the following metal compounds: titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). Referring to
Referring to
The second semiconductor layer 110b may include, for example, a semiconductor device such as silicon (Si) or germanium (Ge), or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The second semiconductor layer 110b may have a SOI structure. The second semiconductor layer 110b may include an active region, for example, an impurity doped well, or an impurity doped structure. The second semiconductor layer 110b may include various device isolation structures such as an STI structure. In
The second insulation layer 132b may be disposed on the second semiconductor layer 110b. The second insulation layer 132b may include an insulating material. For example, the second insulation layer 132b may include an insulating material such as silicon oxide, silicon nitride, insulating polymer, or a combination thereof. The second insulation layer 132b may surround a portion of the sidewall of the second through electrode 140b that penetrates the second semiconductor layer 110b in the vertical direction. The second insulation layer 132b may directly contact the upper insulation layer 134a of the first semiconductor chip 100A in the vertical direction (e.g., second direction DR2).
The second connection pad 131b may be disposed on the second semiconductor layer 110b. The second connection pad 131b may directly contact the first connection pad 131a included in the first semiconductor chip 100A in the vertical direction (e.g., second direction DR2). In one or more example embodiments, a width of the second connection pad 131b in the horizontal direction (e.g., first direction DR1) may be smaller than a width of the first connection pad 131a in the horizontal direction. A lower surface of the second connection pad 131b (a surface in contact with the first connection pad 131a) may be formed at a layer of a different height than a lower surface of the second insulation layer 132b (a surface in contact with the upper insulation layer 134a). That is, the second connection pad 131b may be protruded in the second direction DR2 based on an upper surface of the second insulation layer 132b. Accordingly, as shown in
The second through electrode 140b may penetrate the second semiconductor layer 110b in the vertical direction (e.g., second direction DR2). Referring to
In one or more example embodiments, the first connection pad 131a and the second connection pad 131b may include the same metal material. For example, the first connection pad 131a and the second connection pad 131b may include copper (Cu). Referring to
In one or more example embodiments, the first insulation layer 132a and the second insulation layer 132b may include the same insulating material. For example, the first insulation layer 132a and the second insulation layer 132b may include silicon oxide, silicon nitride, and TEOS forming oxide. The first insulation layer 132a and the second insulation layer 132b may be directly bonded by non-metal-non-metal bonding. That is, at the interface between the first insulation layer 132a and the second insulation layer 132b, covalent bonds may be formed between the same insulating materials, and accordingly, the interface between the first insulation layer 132a and the second insulation layer 132b may not be discernable. That is, the first insulation layer 132a and the second insulation layer 132b may be integrated.
Specifically,
Referring to
When the first semiconductor chip 100A and the second semiconductor chip 100B are bonded by hybrid bonding in the second direction DR2, a metal had to be bonded with a metal and an insulating material has to be bonded with an insulating material, and therefore it may be important to accurately align the first semiconductor chip 100A and the second semiconductor chip 100B vertically. According to one or more example embodiments, an edge of the first connection pad 131a and an edge of the second connection pad 131b may be separated by a first distance w1. According to one or more example embodiments, the width of the first connection pad 131a in the first direction DR1 is about twice the first distance w1 than the width of the second connection pad 131b in the first direction, and therefore, in the process of bonding the first semiconductor chip 100A and the second semiconductor chip 100B, an alignment margin of approximately twice the first distance w1 can be secured.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
After the first semiconductor chip 100A and the second semiconductor chip 100B are bonded, the bonding portion can be heated to a predetermined temperature. According to one or more example embodiments, the bonding portion may be heated at 160° C. to 220° C. As the bonding portion is heated during the bonding process, the volume of the connection pads may increase, and as a result, mutual stress may occur between the connection pad and the insulation layer, which may cause defects inside the connection pad or the insulation layer. In one or more example embodiments, the phenomenon of defects occurring as described above inside the connection pad or insulation layer in the junction process may be improved by including an empty space between the pad and the insulation layer.
For example,
Referring to
A bonding portion of the third semiconductor chip 100C may include a third semiconductor layer 110c, a third connection pad 131c, a third insulation layer 132c, and a third through electrode 140c. The third insulation layer 132c may include a lower insulation layer 135c, a first upper insulation layer 134c, and a second upper insulation layer 133c.
Referring to
In one or more example embodiments, a width of the second connection pad 171b in the first direction and a width of the third connection pad 131c in the first direction may be different from each other. For example, the width of the second connection pad 171b in the first direction may be smaller than the width of the third connection pad 131c in the first direction. In one or more example embodiments, the width of the second connection pad 171b in the first direction may be substantially the same as the width of first connection pad 131a described with reference to
In one or more example embodiments, the width of the third through electrode 140c may be greater than a width of the second through electrode 140b. In one or more example embodiments, the width of the third through electrode 140c may be substantially the same as the width of the first through electrode 140a described with reference to
The detailed composition of the bonding portion disclosed with reference to
For example,
Referring to
The detailed composition of the bonding portion disclosed with reference to
The second semiconductor chip 100B shown in
Referring to
The semiconductor chip stacking structure 1020 may have a structure in which a plurality of semiconductor chips 1020A, 1020B, 1020C, and 1020D are stacked in one direction (e.g., second direction DR2). The top die 1010 may be disposed on the semiconductor chip stacking structure 1020. In one or more example embodiments, the top die 1010 may have a larger width in the first direction DR1 compared to the semiconductor chip stacking structure 1020.
Each of the plurality of semiconductor chips 1020A, 1020B, 1020C, and 1020D stacked on the semiconductor chip stacking structure 1020 may be a memory chip. The top die 1010 may be a buffer die or a logic die. For example, the top die 1010 may be a central processing unit (CPU) chip, a graphic processing unit (GPU) chip, or an application processor (AP) chip.
The semiconductor chip stacking structure 1020 and the top die 1010 may be bonded by hybrid bonding. Each of the semiconductor chips 1020A, 1020B, 1020C, and 1020D included in the semiconductor chip stacking structure 1020 may be bonded to each other by hybrid bonding. Hybrid bonding may be performed by a bonding portion included in each semiconductor chip 1020A, 1020B, 1020C, and 1020D or the top die 1010. The bonding portion may be a portion where the respective semiconductor chips contact each other in the case that the plurality of semiconductor chips 1020A, 1020B, 1020C, and 1020D are stacked and connected. Alternatively, when one of the plurality of semiconductor chips 1020A, 1020B, 1020C, and 1020D and the top die 1010 contact each other, the bonding portion may be a portion where the one of the plurality of semiconductor chips 1020A, 1020B, 1020C, and 1020D and the top die 1010 contact each other.
A semiconductor package 1100 of
A substrate may be disposed below the interposer 1130. Connection members may be disposed on a bottom surface of the interposer 1130. In one or more example embodiments, the interposer 1130 may include a silicon interposer.
The first semiconductor chips 1110 and the second semiconductor chip 1120 may be disposed on the interposer 1130. The first semiconductor chips 1110 and the second semiconductor chip 1120 may be bonded with the interposer 1130 by hybrid bonding. The second semiconductor chip 1120 may include connection pads and an insulation layer for hybrid bonding. For hybrid bonding, the contents of hybrid bonding described with reference to
The second semiconductor chip 1120 may be disposed side-by-side with the first semiconductor chips 1110 between the first semiconductor chips 1110. In one or more example embodiments, the second semiconductor chip 1120 may include a system on chip (SoC). In one or more example embodiments, the second semiconductor chip 1120 may include a central processing unit (CPU) or a graphic processing unit (GPU).
The molding member 1150 may be disposed on the interposer 1130, and may mold the first semiconductor chips 1110 and the second semiconductor chip 1120. The molding member 240 may serve to protect and insulate the first semiconductor chips 1110 and the second semiconductor chip 1120. In one or more example embodiments, the molding member 240 may be formed of a thermosetting resin such as epoxy resin. In one or more example embodiments, the molding member 240 may comprise an epoxy molding compound (EMC). In one or more example embodiments, the molding process with the molding member 240 may include a compression molding or transfer molding process.
A semiconductor package 1200 of
A substrate may be disposed below the interposer 1230. Connection members may be disposed on a lower surface of the interposer 1230. In one or more example embodiments, the interposer 1230 may include a silicon interposer. The second semiconductor chip 1220 may be disposed on the interposer 1230. The second semiconductor chip 1220 may be bonded with the interposer 1230 by hybrid bonding. For hybrid bonding, the contents of hybrid bonding described with reference to
In one or more example embodiments, the second semiconductor chip 1220 may include a system on chip (SoC). In one or more example embodiments, the second semiconductor chip 1220 may include a central processing unit (CPU) or a graphic processing unit (GPU).
The first semiconductor chip 1210 may be disposed on the second semiconductor chip 1220. The first semiconductor chip 1210 may be bonded with the second semiconductor chip 1220 by hybrid bonding. For hybrid bonding, the contents of hybrid bonding described with reference to
The molding member 1240 may be disposed on the interposer 1230, and may mold the first semiconductor chips 1210 and the second semiconductor chip 1220. The molding member 1240 may serve to protect and insulate the first semiconductor chips 1210 and the second semiconductor chip 1220. In one or more example embodiments, the molding member 1240 may be formed of a thermosetting resin, such as epoxy resin. In one or more example embodiments, the molding member 240 may comprise an epoxy molding compound (EMC). In one or more example embodiments, the molding process with the molding member 240 may include a compression molding or transfer molding process.
Although one or more example embodiments have been described above, one or more example embodiments are not limited thereto and it will be apparent to those skilled in the art that one or more example embodiments can be modified and implemented in various ways without departing from the spirit and scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0092989 | Jul 2023 | KR | national |
