Patent Application
20250029941
This U.S. nonprovisional application claims priority under 35 U.S.C ยง 119 to Korean Patent Application No. 10-2023-0094117 filed on Jul. 19, 2023, and Korean Patent Application No. 10-2023-0108352 filed on Aug. 18, 2023, in the Korean Intellectual Property Office, the disclosures of which are both hereby incorporated by reference in their entirety.
The present inventive concepts relate to a semiconductor package, and more particularly, to a semiconductor package including a wiring pad and a method of fabricating the same.
A semiconductor package may implement an integrated circuit chip for use in electronic products. A semiconductor package can be configured such that a semiconductor chip is mounted on a printed circuit board, and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. A substrate and a semiconductor chip may include pads for electrical connection. With the development of electronic industry, various studies of pads have been conducted to improve reliability and of semiconductor packages.
The embodiments of the present inventive concepts provide a semiconductor package having improved reliability and electrical properties and a method of fabricating the same.
The embodiments of the present inventive concepts can provide a semiconductor package having a reduced manufacturing cost due to process simplification in a method of fabricating the same.
According to various embodiments of the present inventive concepts, a semiconductor package may include a substrate; a seed layer on the substrate; and a wiring pad on the seed layer. The wiring pad may include: a pad portion; and a capping layer on the seed layer and the pad portion. A bottom surface of the pad portion may be in contact with a top surface of the seed layer. A width of a top surface of the pad portion may be greater than a width of the bottom surface of the pad portion.
According to various embodiments of the present inventive concepts, a semiconductor package may comprise: a redistribution substrate; a semiconductor chip on the redistribution substrate; and a chip pad on a bottom surface of the semiconductor chip. The chip pad may include a first pad portion and a first capping layer that covers the first pad portion. A bottom surface of the chip pad may be in contact with the bottom surface of the semiconductor chip. A width of the bottom surface of the chip pad may be less than a width of a top surface of the chip pad.
According to various embodiments of the present inventive concepts, a method of fabricating a semiconductor package may comprise: forming a seed layer on a substrate; forming on the seed layer a resist layer having an opening that exposes a top surface of the seed layer; forming a resist pattern by etching a lateral surface of the resist layer exposed by the opening, wherein a width at an upper portion of the resist pattern is less than a width at a lower portion of the resist pattern; forming a plurality of spacer patterns on a lateral surface of the resist pattern exposed by the opening, wherein the spacer patterns expose a central portion of the top surface of the seed layer; forming a pad portion on the exposed central portion of the seed layer between an adjacent pair of the plurality of spacer patterns, the pad portion filling a portion of the opening; removing the spacer patterns to form a through hole that exposes a lateral surface of the pad portion and a peripheral portion of the top surface of the seed layer; and forming a capping layer that fills the through hole and covers a top surface and the lateral surface of the pad portion.
Principles and embodiments of the present inventive concepts will now be described in detail with reference to the accompanying drawings to aid in clearly explaining the present inventive concepts. In this description, like reference numerals indicate like components.
Referring to
In various embodiments, the pad portion 120 may have a top surface 120a and a bottom surface 120b that are opposite to each other in a first direction D1, where the first direction D1 is perpendicular to a top surface 100a of the substrate 100. The bottom surface 120b of the pad portion 120 may be in contact with the top surface 110a of the seed layer 110. The pad portion 120 may have a width in a second direction D2 parallel to the top surface 100a of the substrate 100, where the first direction D1 may be called a vertical direction, and the second direction D2 may be called a horizontal direction. A width 120TW in the horizontal direction D2 of the top surface 120a of the pad portion 120 may be greater than a width 120BW in the horizontal direction D2 of the bottom surface 120b of the pad portion 120. The pad portion 120 may include, for example, copper (Cu).
In various embodiments, the capping layer 130 may cover the top surface 120a and a lateral surface 120s of the pad portion 120. The capping layer 130 may serve to prevent oxidation of the pad portion 120. The capping layer 130 may be disposed on the seed layer 110, where a portion of the capping layer 130 on the lateral surface 120s can adjoin the top surface 110a of the seed layer 110, and form a portion of the bottom surface 101b of the pad portion 120. The lateral surface 120s of the pad portion 120 may extend from the top surface 120a of the pad portion 120 to the top surface 110a of the seed layer 110. The lateral surface 120s of the pad portion 120 may have a first lateral surface s1 and a second lateral surface s2 that are opposite to each other with the pad portion 120 interposed between the first lateral surface s1 and the second lateral surface s2. The capping layer 130 may have a first width W1 in the horizontal direction D2 on the first lateral surface s1 of the pad portion 120, and the capping layer 130 may have a second width W2 in the horizontal direction D2 on the second lateral surface s2 of the pad portion 120. The first width W1 and the second width W2 may be the same at the same height H from the top surface 110a of the seed layer 110. The capping layer 130 may have a symmetric structure, for example, a vertical symmetric structure along a normal line to the top surface 100a of the substrate 100, where a vertical plane can divide the capping layer 130 and pad portion 120 through the center. The capping layer 130 may include, for example, nickel (Ni).
In various embodiments, the lateral surface 120s of the pad portion 120 may be inclined at a first angle A1 with respect to the top surface 110a of the seed layer 110, where the first angle A1 may be an acute angle. For example, the first angle A1 may range from about 45 degrees to about 90 degrees. The capping layer 130 may have an inner lateral surface in contact with the lateral surface 120s of the pad portion 120 and an outer lateral surface 130s opposite to the inner lateral surface with a thickness of the capping layer therebetween. The outer lateral surface 130s of the capping layer 130 may be inclined at a second angle A2 with respect to the top surface 110a of the seed layer 110, where the second angle A2 may be an acute angle. For example, the second angle A2 may range from about 45 degrees to about 90 degrees, where the first angle A1 and the second angle A2 may be different angles.
According to various embodiments of the present inventive concepts, as shown in
In various embodiments, the wiring pad 101 including the pad portion 120 and the capping layer 130 may have a width in the horizontal direction D2. A width 101TW of the top surface 101a of the wiring pad 101 may be greater than a width 101BW of the bottom surface 101b of the wiring pad 101.
Referring to
Referring to
In various embodiments, the etching of the lateral surface of the resist layer 200 may be achieved through a plasma etching process that uses O2/CF4/Ar plasma. In the etching process, O2 may be used as a primary etching gas (e.g., a main etchant). A concentration of O2 in the etching process may be adjusted to control how much the lateral surface of the resist layer 200 is etched. For example, when the etching gas has a high concentration of O2, the second angle A2 may become small, and when the etching gas has a low concentration of O2, the second angle A2 may become large. In addition, a concentration of CF4 in the etching gas may be adjusted to control how much the lateral surface of the resist layer 200 is etched. For example, when CF4 has a high concentration, carbon (C) may be deposited on an upper portion of the resist layer 200, and thus the second angle A2 may become large. The adjustment of concentrations of O2 and CF4 in the etching gas may control how much the lateral surface of the resist layer 200 is etched, and therefore it may be possible to adjust how much the lateral surface 201s of the resist pattern 201 is inclined with respect to a bottom surface 201b of the resist pattern 201.
Referring to
Referring to
In various embodiments, the spacer patterns 211 may have widths 211W in the horizontal direction D2. The widths 211W of the spacer patterns 211 may be substantially the same along the vertical direction D1 at the same height H from the top surface 110a of the seed layer 110.
In various embodiments, the spacer patterns 211 may have lateral surfaces 211s exposed by the opening 202. The lateral surfaces 211s of the spacer patterns 211 may be inclined at a first angle A1 with respect to bottom surfaces 211b of the spacer patterns 211. The first angle A1 may be substantially the same as the first angle A1 at which the lateral surface 120s of the pad portion 120 is inclined with respect to the top surface 110a of the seed layer 110 which is discussed with reference to
Referring to
Referring to
Referring to
Referring back to
The pad portion 120 and the capping layer 130 may each be formed by an independent photolithography process. The two photolithography processes, however, may lead to difficulty in obtaining an overlay margin and uniformly controlling a thickness of the capping layer 130, such that the capping layer 130 may be formed with a relatively large thickness and an asymmetric structure, where the first width W1 and the second width W2 may be different. If the formation process of the capping layer 130 results in a relatively large thickness and an asymmetric structure, a wiring pad 101 may decrease in reliability and electrical properties.
According to principles and embodiments of the present inventive concepts, a photolithography process may be performed a single time to form the wiring pad 101, and the capping layer 130 may be formed to have a relatively small thickness and a symmetric structure. Therefore, a semiconductor package may include a wiring pad 101 having improved reliability and electrical properties. In addition, a simplification of fabrication of the wiring pad 101 may result in a reduction in manufacturing cost and an improvement in fabrication speed of a semiconductor package.
Referring to
In various embodiments, the semiconductor chip 300 may have a top surface 300a and a bottom surface 300b that are opposite to each other in a first direction D1 perpendicular to a top surface 500a of the redistribution substrate 500. A chip pad 301 may be disposed on the bottom surface 300b of the semiconductor chip 300. A bottom surface 301b of the chip pad 301 may be in contact with a bottom surface 300b of the semiconductor chip 300. The chip pad 301 may be electrically connected to integrated circuits of the semiconductor chip 300. The chip pad 301 may include a first pad portion 320 and a first capping layer 330. The first capping layer 330 may cover a top surface and a lateral surface 320s of the first pad portion 320. The first pad portion 320 may include, for example, copper (Cu). The first capping layer 330 may include, for example, nickel (Ni). The chip pad 301 may have a width in a second direction D2 parallel to the top surface 500a of the redistribution substrate 500. The first direction D1 may be referred to as a vertical direction, and the second direction D2 may be referred to as a horizontal direction. A width 301BW in the horizontal direction D2 of the bottom surface 301b of the chip pad 301 may be less than a width 301TW in the horizontal direction D2 of a top surface 301a of the chip pad 301.
In various embodiments, the lateral surface 320s of the first pad portion 320 may include a first lateral surface 320s1 and a second lateral surface 320s2 that are opposite to each other. The first capping layer 330 may have a first width 330W1 in the horizontal direction D2 on the first lateral surface 320s1 of the first pad portion 320. The first capping layer 330 may have a second width 330W2 in the horizontal direction D2 on the second lateral surface 320s2 of the first pad portion 320. The first width 330W1 and the second width 330W2 may be the same as each other at a distance D, along a direction opposite to the vertical direction D1, from the bottom surface 300b of the semiconductor chip 300. The first capping layer 330 may have a symmetric structure (e.g., a vertical symmetric structure along a normal line to the bottom surface 300b of the semiconductor chip 300).
In various embodiments, the lateral surface 320s of the first pad portion 320 may be inclined at a first angle A1 with respect to the bottom surface 300b of the semiconductor chip 300. The first angle A1 may be an acute angle, where for example, the first angle A1 may range from about 45 degrees to about 90 degrees. The first capping layer 330 may have an inner lateral surface in contact with the lateral surface 320s of the first pad portion 320 and an outer lateral surface 330s opposite to the inner lateral surface. The outer lateral surface 330s of the first capping layer 330 may be inclined at a second angle A2 with respect to the bottom surface 300b of the semiconductor chip 300. The second angle A2 may be an acute angle, where for example, the second angle A2 may range from about 45 degrees to about 90 degrees. According to various embodiments of the present inventive concepts, the chip pad 301 may be substantially the same as the wiring pad 101 discussed with reference to
In various embodiments, the formation of the chip pad 301 may be substantially the same as the formation of the wiring pad 101 discussed with reference to
In various embodiments, the redistribution substrate 500 may include a dielectric layer 510, redistribution patterns 511, including redistribution vias 550, and redistribution pads 560 disposed in the dielectric layer 510, and a protection layer 540 disposed on the dielectric layer 510. The dielectric layer 510 may include one or more stacked dielectric layers. The number of the redistribution patterns 511 may be different from the number that are shown. The redistribution patterns 511 may include metal, such as copper, aluminum, titanium, or tungsten. The dielectric layer 510 may include, for example, a photosensitive dielectric material.
In various embodiments, the protection layer 540 may be formed on a top surface 500a of the dielectric layer 510. The protection layer 540 may include, for example, a dielectric polymer. A conductive pad 501 may be disposed in the protection layer 540. The conductive pad 501 may be formed on and electrically connected to the redistribution patterns 511. A bottom surface 501b of the conductive pad 501 may be in contact with the top surface 510a of the dielectric layer 510. A top surface 501a of the conductive pad 501 may be coplanar with a top surface of the protection layer 540, and/or the top surface 500a of the redistribution substrate 500. The conductive pad 501 may include a second pad portion 520 and a second capping layer 530. The conductive pad 501 may have a width in the horizontal direction D2. A width 501TW of the top surface 501a of the conductive pad 501 may be greater than a width 501BW of the bottom surface 501b of the conductive pad 501.
In various embodiments, the conductive pad 501 may be substantially the same as the wiring pad 101 discussed with reference to
In various embodiments, a connection terminal 310 may be disposed between the chip pad 301 and the conductive pad 501. The connection terminal 310 may electrically connect the conductive pad 501 and the chip pad 301 to each other. The semiconductor chip 300 may be electrically connected through the connection terminal 310 to the redistribution substrate 500. The connection terminal 310 may include a conductive material, and may have a shape selected from solder-ball shapes, bump shapes, and pillar shapes. The connection terminal 310 may include metal (e.g., copper).
In various embodiments, a molding layer 400 may be disposed on the redistribution substrate 500. The molding layer 400 may cover the semiconductor chip 300. The molding layer 400 may extend between the semiconductor chip 300 and the protection layer 540 of the redistribution substrate 500 to encapsulate the chip pad 301 and the connection terminal 310. The molding layer 400 may include a dielectric polymer, such as an epoxy-based molding compound.
The chip pad 301 can have a profile in which the width 301TW of the top surface 301a is greater than the width 301BW of the bottom surface 301b, and the chip pad 301 may have an increased adhesion force. For example, the second angle A2 may have an acute angle, and thus a space between neighboring chip pads 301 may increase with decreasing distance from the bottom surface 300b of the semiconductor chip 300. Therefore, the molding layer 400 may easily fill the space between neighboring chip pads 301, and as a result, there may be an increase in bonding force between the chip pad 301 and the molding layer 400.
In various embodiments, a terminal pad 601 may be disposed on the bottom surface 500b of the redistribution substrate 500. The terminal pad 601 may include a third pad portion 620 and a third capping layer 630. When viewed in a plan view, the terminal pad 601 may not overlap any of the chip pad 301 and the conductive pad 501. The terminal pad 601 may be substantially the same as the wiring pad 101 discussed with reference to
In various embodiments, an external coupling terminal 610 may be disposed on a bottom surface of the terminal pad 601. The external coupling terminal 610 may be electrically connected to the chip pad 301 through the terminal pad 601, the redistribution patterns 511, and the connection terminal 310. The external coupling terminal 610 may include a conductive material, and may have a shape selected from solder-ball shapes, bump shapes, and pillar shapes. The external coupling terminal 610 may include metal (e.g., copper).
A semiconductor package according to the present inventive concepts may include a wiring pad that is formed by a photolithography process performed a single time. The wiring pad may have a symmetric structure, and thus a semiconductor package including the wiring pad may demonstrate an improvement in reliability and electrical properties. In addition, the fabrication process for forming the wiring pad may be simplified to reduce manufacturing cost for fabricating the semiconductor package. Moreover, a profile of the wiring pad may be adjusted to increase an adhesion force between the wiring pad and a molding layer that surrounds the wiring pad.
The aforementioned description provides various embodiments for explaining the present inventive concepts. Therefore, the present inventive concepts are not limited to the embodiments described above, and it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the present inventive concepts.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0094117 | Jul 2023 | KR | national |
| 10-2023-0108352 | Aug 2023 | KR | national |
