Patent Application
20120074506
This invention relates to a semiconductor package for high power transistors. More particularly the invention relates to a semiconductor package to combine multiple die such as metal oxide field effect transistors (MOSFETs) in high power high frequency applications.
The need for high power semiconductor devices has led to combining multiple die, such as field effect transistors (FETs) into a single package so that the multiple die act as if they are a single device. In high frequency applications parallel combinations of smaller FETs rather than one large FET maximize device performance and better control power dissipation. One example of a multiple-die semiconductor package is described in commonly-assigned U.S. Pat. No. 6,617,679 B2, entitled Semiconductor Package for Multiple High Power Transistors invented by Gideon Van Zyl and issued Sep. 9, 2003. An on-going goal with such multiple-die semiconductor packaging is the reduction of internal inductance in the conductive paths in the package. Problems with the internal inductance include power loss and oscillations within the package.
Inductance in the source conductive path of the semiconductor package is referred to as common because it is common to both a source-gate circuit path and a source-drain circuit path in the package. When high frequency source-drain current flows through the common inductance of the source conductive path, the source-drain current creates additional source voltage at the source of the FET. The additional source voltage at the source of the FET adds to the voltage of the gate drive and looks like the change in the FET threshold voltage. The additional source voltage changes during RF cycle. It may have one sign when current flows into the gate, and the opposite sign when current flows from the gate. As a result, power can flow between gate-source and drain-source circuits. Since the phase of the additional source voltage depends on the load, for some loads power can flow from gate driver into drain-source circuit, which may result in overloading the gate driver and insufficient amount of gate drive voltage. For some other loads, power can flow from the drain-source circuit into the gate-source circuit, which can make the whole FET unstable. Ideal FET should have absolute insulation (no power exchange) between gate and drain circuits.
Exemplary embodiments of the present invention that are shown in the drawings are summarized below. These and other embodiments are more fully described in the Detailed Description section. It is to be understood, however, that there is no intention to limit the invention to the forms described in this Summary of the Invention or in the Detailed Description. One skilled in the art can recognize that there are numerous modifications, equivalents and alternative constructions that fall within the spirit and scope of the invention as expressed in the claims.
In accordance with this invention a semiconductor package for one or more high-frequency, high-power semiconductor die, such as MOSFETs or FETs, is constructed to cancel voltages due to the effect of a common inductance in the source conductor of the package. The common inductance is shared by a source-drain circuit path and a source-gate circuit path. The gate conductor and the source conductor separated by a dielectric layer are overlaid throughout a portion of the source conductor shared by both the source-drain circuit path and source-gate circuit path. Due to the inductance in the gate conductor and the common inductance in the source conductor, the source conductor, dielectric layer and the gate conductor form a transformer. The voltage at the source of the FET from the common inductance of the source conductor is matched at the gate of the FET by the voltage across the inductance in the gate conductor. In effect the gate voltage from the inductance in the gate conductor cancels out the source voltage from the common inductance in the source conductor thereby decoupling the source-gate circuit loop and the source-drain circuit loop.
The semiconductor package utilizes shortened, flat, wide conductive paths to reduce the inductance in the source conductor and the gate conductor. The source conductor has a split configuration with a central portion and a tail portion split into two arm portions. The central portion is a common path for both the source-gate circuit path and the source-drain circuit path in the package. One arm portion in the split tail contains inductance only in the source-gate circuit path. The other arm portion contains inductance only in the source-drain circuit path.
Further the gate conductor and the central portion of the source conductor are stacked with a dielectric layer between them to electrically separate them as they overlay each other. In such a structure, the inherent inductances in the overlaid conductors form a transformer. The voltage from the “common” inductance in the central portion of the source conductor appears at the source of the FET. Because of the transformer, substantially the same voltage from the gate inductance in the gate conductor appears at the gate of the FET. The voltages cancel each other out and the source-gate circuit loop is effectively decoupled from the source-drain circuit loop.
Various objects and advantages and a more complete understanding of the present invention are apparent and more readily appreciated by reference to the following Detailed Description and to the appended claims when taken in conjunction with the accompanying Drawings wherein:
Referring now to the drawings, where like or similar elements are designated with identical reference numerals throughout the several figures, Now referring to
Source-drain circuit path 60 in the semiconductor package is made up of inductor L34, drain to source of FET 26, inductor L24, resistor 20 and inductor L36. Inductor L34 is the inductance in drain conductor 34, inductor L24 is the inductance of source wires 24, and inductor L36 is the “common” inductance of central portion 36 of source conductor 14 and acts as first coil L36 of transformer 59 in
Source-gate circuit path 62 in the semiconductor package is made up of inductor L15, inductor L25, gate-to-source capacitance in FET 26, inductor L24, resistor 20, inductor L36 and inductor L38. Inductor L15 is inductance of the gate conductor and is second coil L15 of transformer 59. Inductor L25 is the inductance of gate wires 25, and inductor L24 is the inductance in source wires 24. The source-gate current flow also passes through the common inductance L36 of central portion 36 of source conductor 14 which acts also as first coil L36 of transformer 59. Inductor L38 is the inductance in arm 38 of the split tail portion of source conductor 14.
Both circuit paths include inductor L36 which is therefore referred to as the common inductance in the source conductor. The source-gate circuit path also contains inductor L15 which is the second coil of transformer 59. Accordingly the voltage appearing across inductor L36, the common inductance, will be mirrored and appear across inductor L15. When there is a change in load 56, which load is typically a plasma chamber prone to large impedance changes, an accompanying large change in current will flow through common inductance of inductor L36. This produces a corresponding voltage change across inductor L36, which acts as first coil L36 of transformer 59. Whatever voltage change occurs at inductor L36 will appear at source SFET of FET 26. Substantially the same voltage appears across inductor L15, the second coil of transformer 59 and thus at the gate GFET of FET 26. This effectively decouples the source gate circuit loop 62 from the effects of load changes in source-drain circuit loop 60.
The semiconductor package of
Gate conductor 15 is connected to gate connections on the FETs by gate wires 25 soldered to the gate conductor 15 and to the gate connections on the FETs. For example, gate wires 25 connect the gate conductor 15 to gate connections on FET 26. Alternative connection locations on gate conductor 15 are provided for each FET by lateral extensions 30 of the gate conductor 15. For example, gate wires 25 for FET 26 could be soldered to lateral extensions 30A and 30B of the gate conductor 15.
Gate conductor 15 overlays source conductor 14 and is electrically separated from the source conductor by a dielectric layer 31. The dielectric layer is any depositable electrically insulative layer and is typically a glass layer. The dielectric layer 31 insulates the gate conductor and source conductor from each other. This stacked source conductor and gate conductor structure is particularly advantageous in the source-gate circuit loop. The inductances of the two conductors form a transformer with the two transformer inductances electrically positioned in the source-gate circuit loop to operate in voltage opposition to each other on opposite sides of the FET in the circuit loop. Therefore the voltage contribution of the “common” inductance (common to both the source-gate circuit loop and the source-drain circuit loop) in the source conductor cancels out the voltage contribution from the inductance inherent in the gate conductor.
The configuration of the conductive paths in the semiconductor package making up the drain conductor, the source conductor and the gate conductor is most clearly seen in
The drain conductor 12 is as wide as, or slightly wider than the FET to be soldered to the drain conductor. Drain conductor 12 has two leg portions 32 and 34 to shorten the path to the FETs. Each leg 32 or 34 is made flat and wide to minimize the inductance of the drain conductor connected to each FET. The drain leg portions 32 and 34 are shown connected by a lateral portion of drain conductor 12 at the top of FIG. 2. Alternatively, a conductor external to the semiconductive package could replace lateral portion 33. Terminal connector D32 for leg 32 of drain conductor 12 is soldered or deposited at the top of leg 32 of drain conductor 12. Likewise terminal connector D34 for leg 34 of the drain conductor is soldered or deposited at the top of leg 34 of drain conductor 12.
Source conductor 14, drain conductor 12 and gate conductor 15 (
The top layer deposited on the semiconductor package is the gate conductor 15 shown in
The source and gate conductors separated by the dielectric layer are stacked on top of each other. To the extent the source and gate conductors are stacked on top of each other, the configuration forms a transformer structure represented as transformer 59 in the equivalent circuit of
It will be appreciated by one skilled in the art that a number of embodiment changes could be made without departing from the spirit and scope of the invention. For example the gate conductor might be deposited first and the dielectric layer and source conductor could be deposited on top of the gate conductor to create the transformer. In another variation contemplated for the invention the source conductor might not have a split tail so that the common inductance is the only inherent inductance in the source conductor.
In conclusion, the present invention provides, among other things, a semiconductor package for high-frequency multiple-transistors and a method for configuring such a semiconductor package to decouple of common inductance shared by a source-gate circuit loop and a source-drain circuit loop in the package. Those skilled in the art can readily recognize that numerous variations and substitutions may be made in the invention, its use and its configuration to achieve substantially the same results as achieved by the embodiments described herein. Accordingly, there is no intention to limit the invention to the disclosed exemplary forms. Many variations, modifications and alternative constructions fall within the scope and spirit of the disclosed invention as expressed in the claims.
