Patent Application
20250070048
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0110136, filed on Aug. 22, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including stacked semiconductor chips.
Electronic apparatuses are becoming more compact and lightweight according to the rapid development of the electronics industry and users' increased demand. As electronic apparatuses become smaller and lighter, semiconductor packages are also becoming smaller and lighter. In addition, high reliability, high performance, and large capacity are required for the semiconductor packages. As these semiconductor packages have high performance and large capacity, power consumption of the semiconductor packages needs to increase. Accordingly, structures of the semiconductor packages become more important, in order to cope with the size/performance of the semiconductor packages and provide stable power supply to the semiconductor packages.
Provided is a semiconductor package including stacked semiconductor chips and having improved structural reliability.
According to an aspect of the disclosure, a semiconductor package includes: a first semiconductor chip including: a first semiconductor substrate having an first active surface and a first inactive surface opposite to the first active surface, and a plurality of first electrodes penetrating through the first semiconductor substrate; a plurality of second semiconductor chips, each of the plurality of second semiconductor chips including: a second semiconductor substrate having a second active surface and a second inactive surface opposite to the second active surface, and a plurality of second electrodes penetrating through the second semiconductor substrate and stacked on the first semiconductor chip, wherein the second active surfaces of the plurality of second semiconductor substrates face the first inactive surface of the first semiconductor substrate, and the plurality of second semiconductor chips have vertical heights that are equal to each other; a plurality of coupling pads between the first semiconductor chip and the plurality of second semiconductor chips, the plurality of coupling pads electrically connecting the plurality of first electrodes to the plurality of second electrodes; chip coupling insulating layers, each of the chip coupling insulating layers surrounding the plurality of coupling pads and provided between the first semiconductor chip and the plurality of second semiconductor chips; and a support dummy substrate stacked on the plurality of second semiconductor chips, the support dummy substrate including a first support insulating layer on a lower surface of the support dummy substrate, wherein an uppermost second semiconductor chip among the plurality of second semiconductor chips includes a plurality of chip pads on the second inactive surface of the second semiconductor substrate of the uppermost second semiconductor chip, the support dummy substrate includes a plurality of solder balls on the lower surface of the support dummy substrate, and the plurality of solder balls are bonded to the plurality of chip pads.
According to an aspect of the disclosure, a semiconductor package includes: a high bandwidth memory (HBM) controller die including: a first semiconductor substrate having a first active surface and a first inactive surface opposite to the first active surface, and a plurality of first electrodes at least partially penetrating through the first semiconductor substrate; a plurality of dynamic random access memory (DRAM) dies, each of the plurality of DRAM dies including: a second semiconductor substrate having a second active surface and a second inactive surface opposite to the second active surface, and a plurality of second electrodes penetrating through the second semiconductor substrate and stacked on the HBM controller die, wherein the second active surfaces of the plurality of second semiconductor substrates face the first inactive surface of the first semiconductor substrate, and the plurality of DRAM dies have vertical heights that are equal to each other; a plurality of coupling pads between the HBM controller die and the plurality of DRAM dies, the plurality of coupling pads electrically connecting the plurality of first electrodes to the plurality of second electrodes; chip coupling insulating layers, each of the chip coupling insulating layers surrounding the plurality of coupling pads and provided between the HBM controller die and the plurality of DRAM dies; at least one first support dummy substrate stacked on the plurality of DRAM dies; and a second support dummy substrate between the at least one first support dummy substrate and an uppermost DRAM die among the plurality of DRAM dies, wherein the second support dummy substrate includes a plurality of chip pads on an upper surface of the second support dummy substrate that faces the at least one first support dummy substrate, and the at least one first support dummy substrate includes a plurality of solder balls on a lower surface of the at least one first support dummy substrate that faces the second support dummy substrate, and the plurality of solder balls are bonded to the plurality of chip pads.
According to an aspect of the disclosure, a semiconductor package includes: a base redistribution layer including: a plurality of package redistribution line patterns, a plurality of package redistribution vias contacting and connected to at least one of the plurality of package redistribution line patterns, and a package redistribution insulating layer surrounding the plurality of package redistribution line patterns and the plurality of package redistribution vias; a high bandwidth memory (HBM) controller die including: a first semiconductor substrate having a first active surface and a first inactive surface opposite to the first active surface, and a plurality of first electrodes at least partially penetrating through the first semiconductor substrate, wherein the HBM controller die has a first horizontal width and a first vertical height; a plurality of dynamic random access memory (DRAM) dies, each of the plurality of DRAM dies including a second semiconductor substrate having a second active surface and a second inactive surface opposite to the second active surface, wherein the plurality of DRAM dies are stacked on the HBM controller die, the second active surfaces of the plurality of second semiconductor substrates face the first inactive surface of the first semiconductor substrate, and each of the plurality of DRAM dies has a second horizontal width that is less than the first horizontal width of the HBM controller die and a second vertical height; a plurality of coupling pads between the HBM controller die and the plurality of DRAM dies; chip coupling insulating layers, each of the chip coupling insulating layers surrounding the plurality of coupling pads and provided between the HBM controller die and the plurality of DRAM dies; a support dummy substrate on the plurality of DRAM dies, the support dummy substrate having a third horizontal width that is equal to the second horizontal width of at least one DRAM die of the plurality of DRAM dies and a third vertical height that is greater than the first vertical height of the HBM controller die and the second vertical height of the at least one DRAM die of the plurality of DRAM dies; a support coupling insulating layer on an inactive surface of an uppermost DRAM die among the plurality of DRAM dies; a plurality of chip pads on a surface of the support coupling insulating layer that faces the support dummy substrate; and a molding layer provided on the HBM controller die, the molding layer covering an upper surface of the HBM controller die, side surfaces and an upper surface of the plurality of DRAM dies, and side surfaces and a lower surface of the support dummy substrate, wherein the molding layer exposes an upper surface of the support dummy substrate without covering the upper surface of the support dummy substrate, wherein the support dummy substrate includes a plurality of solder balls on the lower surface of the support dummy substrate that faces the upper surface of the support coupling insulating layer, and the plurality of solder balls are bonded to the plurality of chip pads.
The above and/or other aspects will be more clearly understood from the following detailed description of embodiments taken in conjunction with the accompanying drawings, in which:
Hereinafter, embodiments are described in detail with reference to the accompanying drawings. The embodiments of the disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. The following embodiments are provided to sufficiently convey the scope of the disclosure to those skilled in the art rather than to make the present disclosure thorough and complete.
Referring to
The first semiconductor chip 110 and the plurality of second semiconductor chips 120 in the semiconductor package 10 may be electrically connected to each other through a plurality of coupling pads 132 to exchange signals and provide power and ground. For example, the plurality of coupling pads 132 may be arranged between the first semiconductor chip 110 and the lowermost second semiconductor chip 120L and between two neighboring second semiconductor chips 120.
For example, the plurality of coupling pads 132 may include a material containing Cu. A coupling pad 132, located between the first semiconductor chip 110 and the lowermost second semiconductor chip 120L, among the plurality of coupling pads 132 may be referred to as a first coupling pad and a coupling pad 132, located between two neighboring second semiconductor chips 120, among the plurality of coupling pads 132 may be referred to as a second coupling pad.
The first semiconductor chip 110 may include a first semiconductor substrate 112 having an active surface and an inactive surfaces opposite to each other, a first semiconductor element 1122 formed on the active surface of the first semiconductor substrate 112, a first wiring structure 114 formed on the active surface of the first semiconductor substrate 112, and a plurality of first electrodes 116 connected to the first wiring structure 114 and passing or penetrating through at least a portion of the first semiconductor chip 110. The first semiconductor chip 110 may further include a plurality of lower chip pads 117 which are arranged on the lower surface of the first semiconductor chip 110 and electrically connected to a first wiring pattern 1142 and/or a first wiring via 1144. The plurality of lower chip pads 117 may be electrically connected to the first semiconductor element 1122 or the first wiring structure 114 through the first wiring pattern 1142 and/or the first wiring via 1144.
In the semiconductor package 10, the first semiconductor chip 110 may be arranged such that the active surface of the first semiconductor substrate 112 faces down and the inactive surface of the first semiconductor substrate 112 faces up. Therefore, in the semiconductor package 10, unless otherwise stated herein, the upper surface of the first semiconductor chip 110 refers to the side toward which the inactive surface of the first semiconductor substrate 112 is directed and the lower surface of the first semiconductor chip 110 refers to the side toward which the active surface of the first semiconductor substrate 112 is directed. However, when describing the above surfaces on the basis of the first semiconductor chip 110, the lower surface of the first semiconductor chip 110 toward which the active surface of the first semiconductor substrate 112 is directed may be referred to as a front surface of the first semiconductor chip 110 and the upper surface of the first semiconductor chip 110 toward which the inactive surface of the first semiconductor substrate 112 is directed may be referred to as a back surface of the first semiconductor chip 110.
Each of the second semiconductor chips 120 may include a second semiconductor substrate 122 having an active surface and an inactive surfaces opposite to each other, a second semiconductor element 1222 formed on the active surface of the second semiconductor substrate 122, and a second wiring structure 124 formed on the active surface of the second semiconductor substrate 122.
Each of the plurality of second semiconductor chips 120 may include a plurality of second electrodes 126, which are connected to the second wiring structure 124 and pass or penetrate through at least a portion of the second semiconductor chip 120. The uppermost second semiconductor chip 120H, which is the second semiconductor chip 120 located farthest from the first semiconductor chip 110 and located uppermost in the semiconductor package 10, among the plurality of second semiconductor chips 120 may not include the plurality of second electrodes 126.
In some embodiments, the vertical height, that is, the thickness, of the uppermost second semiconductor chip 120H among the plurality of second semiconductor chips 120 may be substantially the same as the vertical height, that is, the thickness, of the other second semiconductor chips 120 among the plurality of second semiconductor chips 120.
In the semiconductor package 10, the plurality of second semiconductor chips 120 may be sequentially stacked on the first semiconductor chip 110 in the vertical direction with each of the active surfaces of the second semiconductor chips 120 directed downward, that is, toward the first semiconductor chip 110. Therefore, in the semiconductor package 10, unless otherwise stated herein, the upper surface of the second semiconductor chip 120 refers to the side toward which the inactive surface of the second semiconductor substrate 122 is directed and the lower surface of the second semiconductor chip 120 refers to the side toward which the active surface of the second semiconductor substrate 122 is directed. However, when describing the above surfaces on the basis of the second semiconductor chip 120, the lower surface of the second semiconductor chip 120 toward which the active surface of the second semiconductor substrate 122 is directed may be referred to as a front surface of the second semiconductor chip 120 and the upper surface of the second semiconductor chip 120 toward which the inactive surface of the second semiconductor substrate 122 is directed may be referred to as a back surface of the second semiconductor chip 120.
The first semiconductor substrate 112 and the second semiconductor substrate 122 may include, for example, a semiconductor material, such as silicon (Si). Also, the first semiconductor substrate 112 and the second semiconductor substrate 122 may include a semiconductor material, such as germanium (Ge). Each of the first semiconductor substrate 112 and the second semiconductor substrate 122 may have an active surface and an inactive surface opposite to the active surface. The first semiconductor substrate 112 and the second semiconductor substrate 122 may include a conductive region, for example, a well doped with impurities. The first semiconductor substrate 112 and the second semiconductor substrate 122 may have various device isolation structures, such as a shallow trench isolation (STI) structure.
Each of the first semiconductor element 1122 and the second semiconductor element 1222 may include a plurality of various types of individual devices. The plurality of individual devices may include various microelectronic devices, for example, metal-oxide-semiconductor field effect transistors (MOSFET), such as complementary metal-oxide-semiconductor (CMOS) transistors, system large scale integration (LSI), image sensors, such as CMOS imaging sensors (CIS), micro-electro-mechanical systems (MEMS), active elements, passive elements, etc. The plurality of individual devices may be electrically connected to the conductive region of the first semiconductor substrate 112 or the second semiconductor substrate 122. Each of the first semiconductor element 1122 and the second semiconductor element 1222 may further include a conductive wire or a conductive plug that electrically connects at least two of the plurality of individual devices or electrically connects the plurality of individual devices to the conductive region of each of the first semiconductor substrate 112 and the second semiconductor substrate 122. Also, the plurality of individual devices may be electrically separated from other neighboring individual devices by an insulating film.
At least one of the first semiconductor chip 110 and the second semiconductor chip 120 may include a memory semiconductor chip. In some embodiments, the first semiconductor chip 110 may be provided with a serial-parallel conversion circuit and include a buffer chip for controlling the plurality of second semiconductor chips 120. The plurality of second semiconductor chips 120 may include memory chips including memory cells. For example, the semiconductor package 10 including the first semiconductor chip 110 and the plurality of second semiconductor chips 120 may include high bandwidth memory (HBM). The first semiconductor chip 110 may be referred to as an HBM controller die and each of the plurality of second semiconductor chips 120 may be referred to as a dynamic random access memory (DRAM) die.
The first wiring structure 114 may include a plurality of first wiring patterns 1142, a plurality of first wiring vias 1144 connected to the plurality of first wiring patterns 1142, and a first inter-wiring insulating layer 1146 surrounding the plurality of first wiring patterns 1142 and the plurality of first wiring vias 1144. In some embodiments, each of the plurality of first wiring patterns 1142 may have a thickness of about 0.5 micrometer or less. In some embodiments, the first wiring structure 114 may have a multi-layer wiring structure including the first wiring patterns 1142 and the first wiring vias 1144 that are at different vertical levels.
The second wiring structure 124 may include a plurality of second wiring patterns 1242, a plurality of second wiring vias 1244 connected to the plurality of second wiring patterns 1242, and a second inter-wiring insulating layer 1246 surrounding the plurality of second wiring patterns 1242 and the plurality of second wiring vias 1244. In some embodiments, each of the plurality of second wiring patterns 1242 may have a thickness of about 0.5 micrometer or less. In some embodiments, the second wiring structure 124 may have a multi-layer wiring structure including the second wiring patterns 1242 and the second wiring vias 1244 that are at different vertical levels.
The plurality of first wiring patterns 1142, the plurality of first wiring vias 1144, the plurality of second wiring patterns 1242, and the plurality of second wiring vias 1244 may include, for example, metal materials, such as aluminum, copper, and tungsten. In some embodiments, the plurality of first wiring patterns 1142, the plurality of first wiring vias 1144, the plurality of second wiring patterns 1242, and the plurality of second wiring vias 1244 include a wiring barrier film and a wiring metal layer. The wiring barrier film may include metal, metal nitride, or alloy. The wiring metal layer may include one metal selected from among W, Al, Ti, Ta, Ru, Mn, and Cu.
When the first wiring structure 114 and the second wiring structure 124 have a multi-layer wiring structure, the first inter-wiring insulating layer 1146 and the second inter-wiring insulating layer 1246 may have a multi-layer structure in which a plurality of insulating layers are stacked, corresponding to the multi-layer wiring structure of the first wiring structure 114 and the second wiring structure 124. For example, the first inter-wiring insulating layer 1146 and the second inter-wiring insulating layer 1246 may include silicon oxide, silicon nitride, silicon oxynitride, an insulating material with lower permittivity than the silicon oxide, or a combination thereof. In some embodiments, the first inter-wiring insulating layer 1146 and the second inter-wiring insulating layer 1246 may include a tetraethyl orthosilicate (TEOS) film or an ultralow K (ULK) film having an ultralow dielectric constant K of about 2.2 to about 2.4. The ULK film may include an SiOC film or an SiCOH film.
Each of the first electrodes 116 and the second electrodes 126 may be provided in the form of a through silicon via (TSV). The first electrodes 116 and the second electrodes 126 may include conductive plugs respectively passing or penetrating through the first semiconductor substrate 112 and the second semiconductor substrate 122 and conductive barrier films surrounding the conductive plugs. Each of the conductive plugs may have a cylindrical shape and each of the conductive barrier films may have a cylinder shape surrounding a sidewall of the conductive plug. A via insulating film may be located between the first electrode 116 and the first semiconductor substrate 112 and between the second electrode 126 and the second semiconductor substrate 122 and may surround sidewalls of the first electrode 116 and the second electrode 126. The first electrode 116 and the second electrode 126 may have any one of a via-first structure, a via-middle structure, and a via-last structure.
The first semiconductor chip 110 may have a first horizontal width W1 and a first vertical height H1 and each of the plurality of second semiconductor chips 120 may have a second horizontal width W2 and a second vertical height H2. In some embodiments, the first horizontal width W1 may be greater than the second horizontal width W2. In some embodiments, the first vertical height H1 may be substantially equal to the second vertical height H2. For example, the first vertical height H1 and the second vertical height H2 may be about 50 micrometers to about 70 micrometers.
The plurality of coupling pads 132 may electrically connect the second wiring patterns 1242 and/or the second wiring vias 1244 of the second wiring structure 124 to the plurality of first electrodes 116 or the plurality of second electrodes 126, which are located below the second wiring structure 124.
For example, the second wiring patterns 1242 and/or the second wiring vias 1244 of the second wiring structure 124 of the lowermost second semiconductor chip 120L may be electrically connected to the plurality of first electrodes 116 of the first semiconductor chip 110 located below the lowermost second semiconductor chip 120L, through the plurality of coupling pads 132, that is, a plurality of first coupling pads. Also, the second wiring patterns 1242 and/or the second wiring vias 1244 of the second wiring structure 124 of another second semiconductor chip 120 other than the lowermost second semiconductor chip 120L may be electrically connected to the plurality of second electrodes 126 of the second semiconductor chip 120 located below another second semiconductor chip 120 stated above, through the plurality of coupling pads 132, that is, a plurality of second coupling pads.
The plurality of coupling pads 132 may be surrounded by a chip coupling insulating layer 130 between the first semiconductor chip 110 and the plurality of second semiconductor chips 120, that is, between the first semiconductor chip 110 and the lowermost second semiconductor chip 120L and between the plurality of second semiconductor chips 120 adjacent to each other. The plurality of coupling pads 132 may pass or penetrate through the chip coupling insulating layer 130. A plurality of chip coupling insulating layers 130 may be respectively provided in spaces or areas between the first semiconductor chip 110 and the plurality of second semiconductor chips 120.
Each of the plurality of coupling pads 132 may be formed by diffusion bonding of: respectively forming conductive material layers, for example, a plurality of upper chip connection pads 1321 and a plurality of lower chip connection pads 1322 shown in
The chip coupling insulating layer 130 may be formed, during the formation of the plurality of coupling pads 132, by diffusion bonding of: respectively forming insulating material layers, for example, an upper chip coupling insulating material layer 131 and a lower chip coupling insulating material layer 134 shown in
A lowermost chip coupling insulating layer 130L, located between the first semiconductor chip 110 and the lowermost second semiconductor chip 120L, among the plurality of chip coupling insulating layers 130 may be formed by performing the diffusion bonding on an insulating material layer covering the upper surface of the first semiconductor chip 110 and an insulating material layer covering the lower surface of the lowermost second semiconductor chip 120L, for example, by performing the diffusion bonding on a lowermost upper chip coupling insulating material layer 131 and a lowermost lower chip coupling insulating material layer 134 which are shown in
The lowermost chip coupling insulating layer 130L may have a recess 130R formed in an upper portion thereof so that the thickness of a portion of the lowermost chip coupling insulating layer 130L, overlapping the lowermost second semiconductor chip 120L in the vertical direction, is greater than the thickness of a portion of the lowermost chip coupling insulating layer 130L, not overlapping the lowermost second semiconductor chip 120L in the vertical direction. The recess 130R may be located in a portion of the lowermost chip coupling insulating layer 130L that does not overlap the lowermost second semiconductor chip 120L in the vertical direction. The lowermost chip coupling insulating layer 130L may have a flat lower surface. Also, a middle portion of the lowermost chip coupling insulating layer 130L, that is, the portion overlapping the lowermost second semiconductor chip 120L in the vertical direction, may protrude upward from an edge portion of the lowermost chip coupling insulating layer 130L, that is, the portion not overlapping the lowermost second semiconductor chip 120L in the vertical direction.
The lowermost chip coupling insulating layer 130L may entirely cover the upper surface of the first semiconductor chip 110 that does not overlap the lowermost second semiconductor chip 120L in the vertical direction. A portion of the upper surface of the first semiconductor chip 110 that overlaps the lowermost second semiconductor chip 120L in the vertical direction and a portion of the lower surface of the lowermost second semiconductor chip 120L may be covered by the plurality of coupling pads 132. The other portions may be covered by the lowermost chip coupling insulating layer 130L.
Each of the chip coupling insulating layers 130 other than the lowermost chip coupling insulating layer 130L may cover, together with the plurality of coupling pads 132, both the upper and lower surfaces of the facing second semiconductor chips 120. The chip coupling insulating layers 130 other than the lowermost chip coupling insulating layer 130L may have flat upper and lower surfaces and substantially the same thickness.
The lowermost chip coupling insulating layer 130L may have the first horizontal width W1 and each of the chip coupling insulating layers 130 other than the lowermost chip coupling insulating layer 130L may have the second horizontal width W2. The chip coupling insulating layers 130 other than the lowermost chip coupling insulating layer 130L may overlap the plurality of second semiconductor chips 120 in the vertical direction. The side surfaces of the chip coupling insulating layers 130 other than the lowermost chip coupling insulating layer 130L and the side surfaces of the second semiconductor chips 120 may be aligned with each other to form a coplanar plane.
The chip coupling insulating layer 130 may include any one of SiO, SiN, SiCN, SiCO, and a polymer material. The polymer material may include benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), silicone, acrylate, or epoxy. For example, the chip coupling insulating layer 130 may include silicon oxide. The chip coupling insulating layer 130 may have a thickness of, for example, about 100 nanometers to about 1 micrometer.
According to an embodiment, the semiconductor package 10 may further include a first support insulating layer 142 disposed on the inactive surface of the uppermost second semiconductor chip 120H. The first support insulating layer 142 may have a constant thickness and cover the inactive surface of the uppermost second semiconductor chip 120H. The shape of the upper surface of the first support insulating layer 142 may match the shape of the inactive surface of the uppermost second semiconductor chip 120H, and the first support insulating layer 142 may completely overlap the inactive surface of the uppermost second semiconductor chip 120H. That is, the side surfaces of the first support insulating layer 142 and the uppermost second semiconductor chip 120H may be aligned with each other in the vertical direction (Z direction) to form a coplanar plane. The thickness of the first support insulating layer 142 may be less than the thickness of the second semiconductor substrate 122 of the second semiconductor chip 120. The upper surface of the first support insulating layer 142 may have the same area as the upper surface of the uppermost second semiconductor chip 120H. That is, the first support insulating layer 142 may have the second horizontal width W2. According to an embodiment, the first support insulating layer 142 may include silicon nitride.
According to an embodiment, the semiconductor package 10 may further include a plurality of chip pads 144, which are disposed on the upper surface of the first support insulating layer 142 facing a support dummy substrate 150. The plurality of chip pads 144 may be arranged in a direction parallel to the upper surface of the first support insulating layer 142. As shown in detail in
The support dummy substrate 150 may be stacked above or on the uppermost second semiconductor chip 120H. The support dummy substrate 150 may include a body 152, a second support insulating layer 154, a connection pad 156, and a solder ball 158. The body 152 of the support dummy substrate 150 may include, for example, a semiconductor material, such as silicon (Si). In some embodiments, the body 152 may include only the semiconductor material. For example, the body 152 may include a portion of a bare wafer.
The body 152 of the support dummy substrate 150 may have a third horizontal width W3a and a third vertical height H3. In some embodiments, the third horizontal width W3a may be less than the first horizontal width W1 and the second horizontal width W2. In some embodiments, the third vertical height H3 may be greater than the first vertical height H1 and the second vertical height H2. For example, the third vertical height H3 may be about 100 micrometers to about 500 micrometers. Strictly speaking, the third vertical height H3 refers to the vertical height of the body 152 of the support dummy substrate 150. However, since the vertical height of the second support insulating layer 154 is very small compared to the vertical height of the body 152, the third vertical height H3 is substantially equal to the vertical height of the support dummy substrate 150. The side surfaces of the support dummy substrate 150 and the side surfaces of the second semiconductor chips 120 may be aligned with each other in the vertical direction (Z direction) to form a coplanar plane.
The second support insulating layer 154 of the support dummy substrate 150 may have a constant thickness and cover the lower surface of the body 152 facing the second semiconductor chips 120. The shape of the lower surface of the second support insulating layer 154 may match the shape of the lower surface of the body 152, and the second support insulating layer 154 may completely overlap the lower surface of the body 152. That is, the side surfaces of the second support insulating layer 154 and the side surfaces of the body 152 may be aligned with each other in the vertical direction (Z direction) to form a coplanar plane. According to an embodiment, the second support insulating layer 154 may include silicon nitride.
According to an embodiment, connection pads 156 may be disposed on the lower surface of the second support insulating layer 154 facing the second semiconductor chip 120. The plurality of connection pads 156 may be arranged in a direction parallel to the lower surface of the second support insulating layer 154. As shown in detail in
According to an embodiment, a plurality of solder balls 158 may be respectively attached to the plurality of connection pads 156. The solder ball 158 may include metal, such as a solder material. For example, the solder material may include tin (Sn), silver (Ag), zinc (Zn), and/or an alloy thereof. The solder balls 158 may be arranged between the body 152 of the support dummy substrate 150 and the uppermost second semiconductor chip 120H and electrically connect the connection pads 156 and the chip pads 144 to each other. However, since no semiconductor device is provided inside the support dummy substrate 150, the uppermost second semiconductor chip 120H and the body 152 of the support dummy substrate 150 may not be electrically connected to each other. According to an embodiment, the solder balls 158 may be entirely surrounded inside edges of the lower surface of the first support dummy substrate 150 in a plan view.
The uppermost second semiconductor chip 120H and the support dummy substrate 150 may be spaced apart in the vertical direction (Z direction) by a certain distance. Strictly speaking, the upper surface of the first support insulating layer 142 and the lower surface of the second support insulating layer 154 of the support dummy substrate 150 may be spaced apart from each other by a certain distance. The first semiconductor chip 110 and the plurality of second semiconductor chips 120 have a relatively small thickness in the vertical direction (Z direction) compared to the widths thereof in the horizontal direction, and thus, the upper surfaces of the first semiconductor chip 110 and the plurality of second semiconductor chips 120 may have a sinuous wave shape. Here, when the first semiconductor chip 110 and the plurality of second semiconductor chips 120 are stacked by hybrid bonding, wave shapes of the upper surfaces of the first semiconductor chip 110 and the plurality of second semiconductor chips 120 are accumulated, and thus, the upper surface of the uppermost second semiconductor chip 120H may have a large curve. The uppermost second semiconductor chip 120H and the support dummy substrate 150 are bonded using the solder balls 158 with a distance rather than hybrid bonding, and thus, it is possible to avoid the occurrence of voids due to surface-to-face adhesion. As described in detail below, a molding layer 160 may be buried between the uppermost second semiconductor chip 120H and the support dummy substrate 150 to fill an empty space (an empty area).
The semiconductor package 10 may further include the molding layer 160, which is provided on the first semiconductor chip 110, covers the upper surface of the first semiconductor chip 110, and surrounds the side surfaces of the plurality of second semiconductor chips 120 and the support dummy substrate 150. The molding layer 160 may be buried in the space (the area) between the uppermost second semiconductor chip 120H and the support dummy substrate 150. Strictly speaking, the molding layer 160 may be buried in the space (the area) between the upper surface of the first support insulating layer 142 and the lower surface of the second support insulating layer 154 in the support dummy substrate 150. The molding layer 160 may be buried between the uppermost second semiconductor chip 120H and the support dummy substrate 150 and surround the plurality of solder balls 158. That is, the molding layer 160 may fill the space (the area) between the support dummy substrate 150 and the uppermost second semiconductor chip 120H and surround the solder balls 158. Even if the plurality of second semiconductor chips 120 are stacked by hybrid bonding and the upper surface of the uppermost second semiconductor chip 120H or the upper surface of the first support insulating layer 142 is curved, the molding layer 160 may fill the space (the area) between curves and prevent voids from occurring.
The molding layer 160 may include, for example, an epoxy molding compound (EMC). In some embodiments, the molding layer 160 may cover the upper surface of the support dummy substrate 150. In some other embodiments, the molding layer 160 may not cover the upper surface of the support dummy substrate 150. For example, a heat dissipation member may be attached to the support dummy substrate 150 with a thermal interface material (TIM) layer therebetween.
In some embodiments, the semiconductor package 10 may further include a base redistribution layer 170 disposed on the lower surface of the first semiconductor chip 110. The base redistribution layer 170 may include a plurality of package redistribution line patterns 172, a plurality of package redistribution vias 174, and a package redistribution insulating layer 176. In some embodiments, a plurality of package redistribution insulating layers 176 may be stacked. The package redistribution insulating layer 176 may be formed from, for example, photo imageable dielectric (PID) or photosensitive polyimide (PSPI). Each of the package redistribution line patterns 172 and the package redistribution vias 174 may include, for example, metals, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or an alloy thereof. However, embodiments of the disclosure are not limited thereto. In some embodiments, the package redistribution line pattern 172 and the package redistribution via 174 may be formed by stacking a metal or a metal alloy on a seed layer including titanium, titanium nitride, or titanium tungsten.
The plurality of package redistribution line patterns 172 may be disposed on at least one of the upper surface and the lower surface of the package redistribution insulating layer 176. The plurality of package redistribution vias 174 may pass or penetrate through the package redistribution insulating layer 176 and be brought into contact with and connected to some of the plurality of package redistribution line patterns 172. In some embodiments, at least some of the plurality of package redistribution line patterns 172 may be formed together with some of the plurality of package redistribution vias 174 to form an integrated body. For example, the package redistribution line pattern 172 and the package redistribution via 174 in contact with the upper surface of the package redistribution line pattern 172 may be integrated with each other. The package redistribution insulating layer 176 may surround the plurality of package redistribution line patterns 172 and the plurality of package redistribution vias 174.
The plurality of package redistribution line patterns 172 and the plurality of package redistribution vias 174 may be electrically connected to the plurality of lower chip pads 117. In some embodiments, at least some of the plurality of package redistribution vias 174 may be in contact with the plurality of lower chip pads 117. For example, when the semiconductor package 10 includes a plurality of package redistribution insulating layers 176 in which the package redistribution line patterns 172 and the package redistribution vias 174 are stacked, the package redistribution vias 174 passing or penetrating through an uppermost package redistribution insulating layer 176 may be in contact with and electrically connected to the lower chip pads 117.
In some embodiments, the plurality of package redistribution vias 174 may each have a tapered shape extending from the bottom to the top with a decreasing horizontal width. That is, the horizontal width of each of the plurality of package redistribution vias 174 may increase in a direction away from the first semiconductor chip 110.
A package redistribution line pattern 172, which is disposed on the lower surface of the base redistribution layer 170, among the plurality of package redistribution line patterns 172 may be referred to as a package pad 178. A plurality of package connection terminals 180 may be respectively attached to a plurality of package pads 178. For example, each of the package connection terminals 180 may include a solder ball or a bump.
In embodiments, the semiconductor package 10 may not include the base redistribution layer 170. For example, the plurality of package connection terminals 180 may be attached to the plurality of lower chip pads 117.
The horizontal width and horizontal area of the base redistribution layer 170 may be same as the horizontal width and horizontal area of the first semiconductor chip 110. The base redistribution layer 170 and the first semiconductor chip 110 may overlap each other in the vertical direction (Z direction).
For example, the horizontal widths and horizontal areas of the base redistribution layer 170, the first semiconductor chip 110, and the molding layer 160 may be substantially the same. The side surfaces of the base redistribution layer 170, the first semiconductor chip 110, and the molding layer 160 may be aligned with each other in the vertical direction (Z direction) to form a coplanar plane.
The semiconductor package 10 according to the disclosure may be formed by stacking the first semiconductor chip 110 and the plurality of second semiconductor chips 120, through the hybrid bonding that forms the plurality of coupling pads 132 and the chip coupling insulating layer 130 by diffusion bonding.
Since the semiconductor package 10 according to the disclosure has a support dummy substrate 150 having a relatively large thickness (vertical height), the structural reliability of the semiconductor package 10 may be improved, and heat may be smoothly discharged to the outside of the semiconductor package 10 through the support dummy substrate 150. The support dummy substrate 150 and the uppermost second semiconductor chip 120H are bonded to each other by the solder balls 158.
Referring to
The semiconductor package 30 illustrated in
Referring to
According to an embodiment, a substrate coupling insulating layer 330 may be disposed on the upper surface of the uppermost second semiconductor chip 120H. A coupling pad 132 is not buried in the substrate coupling insulating layer 330, unlike in a plurality of chip coupling insulating layers 130. The substrate coupling insulating layer 330 may have a constant thickness and cover the inactive surface of the uppermost second semiconductor chip 120H. The shape of the upper surface of the substrate coupling insulating layer 330 may match the shape of the inactive surface of the uppermost second semiconductor chip 120H, and the substrate coupling insulating layer 330 may completely overlap the inactive surface of the uppermost second semiconductor chip 120H. That is, the side surfaces of the substrate coupling insulating layer 330 and the uppermost second semiconductor chip 120H may be aligned with each other in the vertical direction (Z direction) to form a coplanar plane. The substrate coupling insulating layer 330 may have substantially the same configuration as the chip coupling insulating layer 130. That is, the substrate coupling insulating layer 330 may be formed by diffusion bonding of: expanding facing insulating material layers using heat to bring the insulating material layers into contact with each other; and diffusing atoms contained in the insulating material layers so that the insulating material layers are integrated with each other.
According to an embodiment, the second support dummy substrate 320 may be disposed on the substrate coupling insulating layer 330. The second support dummy substrate 320 may have a fourth horizontal width W4 and a fourth vertical height H4. Here, the fourth horizontal width W4 may be substantially equal to a second horizontal width W2 of a second semiconductor chip 120 and the fourth vertical height H4 may be substantially equal to a second vertical height H2 of the second semiconductor chip 120. The second support dummy substrate 320 may include, for example, a semiconductor material, such as silicon. In some embodiments, the second support dummy substrate 320 may include only the semiconductor material. For example, the second support dummy substrate 320 may include a portion of a bare wafer. Unlike a plurality of second semiconductor chips 120, the second support dummy substrate 320 may not include a semiconductor device therein. A first support insulating layer 142 may be disposed on the second support dummy substrate 320, and a plurality of chip pads 144 may be arranged on the upper surface of the first support insulating layer 142 in the first horizontal direction (X direction) or the second horizontal direction (Y direction). In the semiconductor package 10 shown in
The semiconductor package 30 may further include a molding layer 160, which is provided on a first semiconductor chip 110, covers the upper surface of the first semiconductor chip 110, and surrounds the side surfaces of the plurality of second semiconductor chips 120, the side surfaces of the second support dummy substrate 320, and the side surfaces of the first support dummy substrate 150. In addition, the molding layer 160 may cover the upper surface and side surfaces of the first support insulating layer 142. The molding layer 160 may be buried in the space (the area) between the first support insulating layer 142 on the second support dummy substrate 320 and the first support dummy substrate 150. That is, the molding layer 160 may fill the space (the area) between the first support dummy substrate 150 and the second support dummy substrate 320 and surround solder balls 158.
According to an embodiment, all of the solder balls 158 may be provided within edges of the upper surface of the second support dummy substrate 320, in a plan view.
The semiconductor packages 40 and 50 respectively illustrated in
Referring to
The first semiconductor chip 110 may have a first horizontal width W1 and a first vertical height H1 and each of the plurality of second semiconductor chips 120 may have a second horizontal width W2 and a second vertical height H2.
The support dummy substrate 450 may be stacked above or on the uppermost second semiconductor chip 120H. The support dummy substrate 450 may include, for example, a semiconductor material, such as silicon. In some embodiments, the support dummy substrate 450 may include only the semiconductor material. For example, the support dummy substrate 450 may include a portion of a bare wafer.
The support dummy substrate 450 may have a third horizontal width W3b and a third vertical height H3. The third vertical height H3 of the support dummy substrate 450 shown in
The support dummy substrate 450 may include a first support insulating layer 142 disposed on the lower surface of the support dummy substrate 450, a plurality of connection pads 456 arranged on the lower surface of the first support insulating layer 142, and solder balls 458 respectively bonded to the plurality of connection pads 456. Here, the plurality of connection pads 456 and the plurality of solder balls 458 may be substantially the same as the plurality of connection pads 156 and the plurality of solder balls 158, respectively, shown in
Referring to
The support dummy substrate 550 may include a second support insulating layer 554 disposed on the lower surface of a body 552, a plurality of connection pads 556 arranged on the lower surface of the second support insulating layer 554, and solder balls 558 respectively bonded to the plurality of connection pads 556. Here, the plurality of connection pads 556 and the plurality of solder balls 558 may be substantially the same as the plurality of connection pads 156 and the plurality of solder balls 158, respectively, shown in
Referring to
The first semiconductor chip 110 may have a first horizontal width W1 and a first vertical height H1 and each of the plurality of second semiconductor chips 120 may have a second horizontal width W2 and a second vertical height H2.
A plurality of support dummy substrates 650 may be stacked above or on an uppermost second semiconductor chip 120H. The plurality of support dummy substrates 650 may include, for example, a semiconductor material, such as silicon. In some embodiments, the plurality of support dummy substrates 650 may include only the semiconductor material. For example, each of the plurality of support dummy substrates 650 may include a portion of a bare wafer. The total vertical height of the plurality of stacked support dummy substrates 650 may be greater than the second vertical height H2 of the second semiconductor chip 120. For example, the total vertical height of the plurality of stacked support dummy substrates 650 may be about 100 micrometers to about 500 micrometers.
Each of the plurality of support dummy substrates 650 may have a fifth horizontal width W5 and a fifth vertical height H5. In some embodiments, the fifth horizontal width W5 may be less than the first horizontal width W1 and equal to the second horizontal width W2. In some embodiments, the fifth vertical height H5 may be substantially equal to the first vertical height H1 and the second vertical height H2. For example, the fifth vertical height H5 may be about 50 micrometers to about 90 micrometers. In some embodiments, the fifth vertical height H5 may be less than the first vertical height H1 and the second vertical height H2. For example, the fifth vertical height H5 may be substantially equal to the vertical heights of the first semiconductor substrate 112 and the second semiconductor substrate 122 and may be less than the first vertical height H1 and the second vertical height H2 by several micrometers.
Substrate coupling insulating layers 632 may be respectively located between the plurality of support dummy substrates 650. The substrate coupling insulating layers 632 respectively located between the plurality of support dummy substrates 650 may not include the coupling pads 132 therein, unlike chip coupling insulating layers 130 located between the plurality of second semiconductor chips 120.
According to an embodiment, the semiconductor package 60 may include a second support insulating layer 654 disposed on the lower surface of a lowermost support dummy substrate 650L among the plurality of support dummy substrates 650, a plurality of connection pads 656 arranged on the lower surface of the second support insulating layer 654, and solder balls 658 respectively bonded to the plurality of connection pads 656. The second support insulating layer 654, the plurality of connection pads 656, and the plurality of solder balls 658 shown in
Referring to
According to an embodiment, the semiconductor package 70 may include the second support dummy substrate 220 stacked on a plurality of second semiconductor chips 120 stacked in a vertical direction (Z direction) and a plurality of first support dummy substrates 650 spaced apart from the second support dummy substrate 220 and stacked in the vertical direction (Z direction). Here, the second support insulating layer 654 extending along the lower surface of a first support dummy substrate 650 may be disposed on the lower surface of a lowermost first support dummy substrate 650L among the plurality of first support dummy substrates 650. Also, a plurality of connection pads 656 may be arranged on the second support insulating layer 654 in a first horizontal direction (X direction) or a second horizontal direction (Y direction) and solder balls 658 may be respectively attached to the plurality of connection pads 656. The plurality of solder balls 658 may be respectively bonded to a plurality of chip pads 144 formed on the second support dummy substrate 220 and may thus be arranged between the plurality of connection pads 656 and the plurality of chip pads 144.
Referring to
The first semiconductor chip 110 having the plurality of first chip connection pads 1321 and the first chip coupling insulating material layer 131 formed on the upper surface thereof is attached on a first support substrate 1001. After a first release film 1002 is attached to the upper surface of the first support substrate 1001, the first semiconductor chip 110 may be attached on the first release film 1002. The first semiconductor chip 110 may be attached to the first release film 1002 such that a first wiring structure 114 faces the first support substrate 1001.
The plurality of first chip connection pads 1321 and the first chip coupling insulating material layer 131 are also formed on the upper surface of a second semiconductor chip 120. The plurality of first chip connection pads 1321 may be arranged on the upper surface, that is, the inactive surface, of the second semiconductor chip 120. The plurality of first chip connection pads 1321 may be disposed on the upper surface of the second semiconductor chip 120 so that the first chip connection pads 1321 are respectively connected to a plurality of second electrodes 126. The first chip coupling insulating material layer 131 may be formed on the upper surface, that is, the inactive surface, of the second semiconductor chip 120 and surround side surfaces of the plurality of first chip connection pads 1321. The first chip coupling insulating material layer 131 may cover the upper surface of the second semiconductor chip 120 and the side surfaces of the plurality of first chip connection pads 1321 but may expose the plurality of first chip connection pads 1321 without covering the upper surfaces of the first chip connection pads 1321.
A plurality of second chip connection pads 1322 and a second chip coupling insulating material layer 134 are formed on the lower surface of the second semiconductor chip 120. The plurality of second chip connection pads 1322 may be disposed on the lower surface of the second semiconductor chip 120, that is, the lower surface of a second wiring structure 124. The plurality of second chip connection pads 1322 may be disposed on the lower surface of the second semiconductor chip 120 so that the second chip connection pads 1322 are respectively connected to second wiring patterns 1242 and/or second wiring vias 1244. The second chip coupling insulating material layer 134 may be formed on the lower surface of the second semiconductor chip 120 and surround side surfaces of the plurality of second chip connection pads 1322. The second chip coupling insulating material layer 134 may cover the lower surface of the second semiconductor chip 120 and the side surfaces of the plurality of second chip connection pads 1322 but may expose the plurality of second chip connection pads 1322 without covering the lower surfaces of the second chip connection pads 1322.
The second semiconductor chip 120 is placed on the first semiconductor chip 110. The second semiconductor chip 120 may include the lowermost second semiconductor chip 120L shown in
Referring to
Subsequently, heat at a second temperature higher than the first temperature is applied to the first semiconductor chip 110 and the second semiconductor chip 120. Accordingly, the plurality of coupling pads 132 may be formed by coupling the plurality of first chip connection pads 1321 and the plurality of corresponding second chip connection pads 1322 to each other and the chip coupling insulating layer 130 may be formed by coupling the first chip coupling insulating material layer 131 and the second chip coupling insulating material layer 134 to each other. The plurality of first chip connection pads 1321 and the plurality of corresponding second chip connection pads 1322 may be expanded by the heat and brought into contact with each other and then integrated with each other by diffusion of metal atoms contained therein. Accordingly, the plurality of coupling pads 132 may be formed through the diffusion bonding.
Referring to
Subsequently, a plurality of coupling pads 132, in which the plurality of first chip connection pads 1321 and the plurality of second chip connection pads 1322 are coupled to each other, and a chip coupling insulating layer 130, in which the first chip coupling insulating material layer 131 and the second chip coupling insulating material layer 134 are coupled to each other, may be formed between the plurality of second semiconductor chips 120 in a method similar to that described in
Referring to
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While certain embodiments of the disclosure have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0110136 | Aug 2023 | KR | national |
