Patent Application
20240421034
This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0076423, filed on Jun. 14, 2023, in the Korean Intellectual Property office, the disclosure of which is incorporated by reference herein in its entirety.
The present inventive concept relates to a semiconductor package.
Electronic devices have become more compact with versatile performance, and large capacity according to the rapid development of the electronic industry and demands of users. Accordingly, semiconductor packages including a plurality of semiconductor devices are currently under development. Recently, a method of mounting various types of semiconductor chips side-by-side on an interposer has been under development. In the case of the semiconductor package to which the interposer is applied, research is being conducted to reduce damage caused by warpage while a relatively large area of the interposer is secured for mounting a plurality of semiconductor devices.
According to an embodiment of the present inventive concept, a semiconductor package includes: a first redistribution structure including a first insulating layer and first conductive patterns; a connection substrate disposed on the first redistribution structure, and including a base layer and a through electrode penetrating the base layer, wherein the base layer includes a first material; a molding layer at least partially surrounding the connection substrate and disposed on the first redistribution structure, wherein the molding layer includes a second material; a second redistribution structure disposed on the molding layer and the connection substrate, and including a second insulating layer and second conductive patterns, and a plurality of semiconductor devices spaced apart from each other on the second redistribution structure, wherein a first thermal expansion coefficient of the first material of the base layer is less than a second thermal expansion coefficient of the second material of the molding layer, and wherein an upper surface of the base layer is substantially coplanar with an upper surface of the molding layer.
According to an embodiment of the present inventive concept, a semiconductor package includes: a first redistribution structure including a first insulating layer and first conductive patterns; a connection substrate disposed on the first redistribution structure, and including a base layer and a through electrode configured to penetrate the base layer, wherein the base layer includes glass; a molding layer at least partially surrounding the connection substrate on the first redistribution structure and including an epoxy mold compound; a second redistribution structure disposed on the molding layer and the connection substrate, and including a second insulating layer and second conductive patterns; and a plurality of semiconductor devices spaced apart from each other on the second redistribution structure, wherein an upper surface of the base layer is substantially coplanar with an upper surface of the molding layer, and wherein the second insulating layer extends along the upper surface of the base layer and the upper surface of the molding layer.
According to an embodiment of the present inventive concept, a semiconductor package includes: a first redistribution structure including a first insulating layer and first conductive patterns; a connection substrate mounted on the first redistribution structure, and including a base layer and a through electrode configured to penetrate the base layer, wherein the base layer includes a first material; first connection bumps disposed between the connection substrate and the first redistribution structure; a bridge chip mounted on the first redistribution structure and spaced apart from the connection substrate in a lateral direction, wherein the bridge chip includes a bridge circuit pattern; second connection bumps disposed between the bridge chip and the first redistribution structure; a plurality of conductive pillars disposed on the bridge chip, and electrically connected to the bridge circuit pattern; a molding layer at least partially surrounding the connection substrate and the bridge chip on the first redistribution structure and including a second material; a second redistribution structure disposed on the molding layer and the connection substrate, and including a second insulating layer and second conductive patterns; and a plurality of semiconductor devices spaced apart from each other and disposed on the second redistribution structure, wherein a first thermal expansion coefficient of the first material of the base layer is less than a second thermal expansion coefficient of the second material of the molding layer, wherein an upper surface of the base layer is substantially coplanar with an upper surface of the molding layer, wherein the second insulating layer extends along the upper surface of the base layer and the upper surface of the molding layer, and wherein the second conductive patterns include a conductive via pattern extending in the second insulating layer and contacting an upper surface of the through electrode.
The above and other aspects of the present inventive concept will become more apparent by describing in detail embodiments thereof, with reference to the accompanying drawings, in which:
Hereinafter, embodiments of the present inventive concept will be described in detail with reference to the accompanying drawings. Identical reference numerals are used for the same constituent elements in the drawings, and duplicate descriptions thereof are omitted or briefly discussed.
It will be understood that a vertical direction may be a Z direction, and a horizontal direction may be a direction substantially perpendicular to the Z direction. A first horizontal direction and a second horizontal direction may be directions crossing each other. For example, the first horizontal direction may be referred to as an X direction, and the second horizontal direction may be referred to as a Y direction. A horizontal width of a component, element, or layer may be referred to as a length in the horizontal direction.
Referring to
The first redistribution structure 110 may include a structure to which external connection terminals 145 are attached. In some embodiments of the present inventive concept, the first redistribution structure 110 may include a redistribution substrate manufactured by performing a redistribution process. In some embodiments of the present inventive concept, the first redistribution structure 110 may include a printed circuit board. For example, the first redistribution structure 110 may also be referred to as a substrate or a package substrate.
The first redistribution structure 110 may include a first redistribution insulating layer 111 and first conductive redistribution patterns 113.
The first redistribution insulating layer 111 may include a plurality of first sub-insulating layers stacked in the vertical direction (e.g., the Z direction). For example, each of the plurality of first sub-insulating layers of the first redistribution insulating layer 111 may include an insulating polymer, an epoxy, or a combination thereof. For example, the plurality of first sub-insulating layers may be formed from, for example, a photo imageable dielectric (PID) material or a photosensitive polyimide (PSPI) material.
The first conductive redistribution patterns 113 may include first conductive layers 1131 and first conductive via patterns 1133. Each of the first conductive layers 1131 may extend in the horizontal direction (for example, in X direction and/or Y direction), and may be disposed at different vertical levels to form a multi-layer distribution structure. The first conductive layers 1131 may be disposed on any one surface of an upper surface or a lower surface of each of the plurality of first sub-insulating layers of the first redistribution insulating layer 111. For example, the first conductive layers 1131 may include a line pattern extending in a line shape along any one surface of the upper and lower surfaces of one first sub-insulating layer of the plurality of first sub-insulating layers of the first redistribution insulating layer 111. The first conductive via patterns 1133 may electrically connect the first conductive layers 1131 to each other that are disposed at different vertical levels from one another. In some embodiments of the present inventive concept, each of the plurality of first conductive via patterns 1133 may have a tapered shape, in which a horizontal width thereof decreases in a direction from an upper side thereof to a lower side thereof. In other words, each of the first conductive via patterns 1133 may have a horizontal width that decreases as a lower surface of the first redistribution structure 110 is approached.
The first conductive redistribution patterns 113 may include first upper pads 117 and second upper pads 119 that are provided on the upper surface of the first redistribution insulating layer 111. The first upper pads 117 may be attached to first connection bumps 141. The second upper pads 119 may be attached to second connection bumps 143. The first conductive redistribution patterns 113 may include external connection pads 115 disposed under the lower surface of the first redistribution insulating layer 111. The external connection pads 115 may be respectively connected to the external connection terminals 145. In some embodiments of the present inventive concept, in a cross-sectional view, each external connection pad 115 may have a polygonal shape such as a rectangular shape. The external connection terminals 145 may be configured to electrically and physically connect the first redistribution structure 110 to an external device. The external connection terminals 145 may be formed of, for example, a solder ball or a solder bump.
For example, the first conductive redistribution patterns 113 may include a metal, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), and ruthenium (Ru), or an alloy thereof.
The first conductive redistribution patterns 113 may include first seed metal patterns 1135 extending along surfaces of the first conductive layers 1131 and surfaces of the first conductive via patterns 1133. The first seed metal patterns 1135 may extend along a bottom surface of the corresponding first conductive layer 1131 and/or sidewalls and a bottom surface of the corresponding first conductive via pattern 1133. For example, the first seed metal patterns 1135 may include at least one of Cu, Ti, TiW, Ti nitride (TIN), Ta, Ta nitride (TaN), chromium (Cr), and/or Al.
At least some of a plurality of first conductive layers 1131 may be integrated together with the corresponding first conductive via pattern 1133. For example, some of the plurality of first conductive layers 1131 may be integrated together with the corresponding first conductive via pattern 1133 that are in contact with the lower side thereof. For example, the first conductive layers 1131 and the first conductive via patterns 1133 may be formed by using an electroplating process by using the first seed metal patterns 1135.
The intermediate connection structure ML may be disposed on the first redistribution structure 110. A footprint of the intermediate connection structure ML may be the same as a footprint of the first redistribution structure 110. An outer wall of the intermediate connection structure ML may be substantially vertically aligned with an outer wall of the first redistribution structure 110. The intermediate connection structure ML may include at least one of a connection substrate 120, a bridge chip 150, a plurality of conductive pillars 161, and a first molding layer 130.
The connection substrate 120 may provide an electrical signal path for transmitting an electrical signal between the first redistribution structure 110 and the second redistribution structure 170. The connection substrate 120 may be mounted above the first redistribution structure 110 via the first connection bumps 141.
The connection substrate 120 may include an insulating base layer 121, a plurality of through electrodes 123, and connection pads 125.
The insulating base layer 121 may have a plate shape in which an upper surface thereof and a lower surface thereof are generally in parallel with each other. For example, the insulating base layer 121 may have a cuboid shape. An upper surface 1211 of the insulating base layer 121 may include a plane perpendicular to the vertical direction (e.g., the Z direction). In some embodiments of the present inventive concept, the insulating base layer 121 may include an inorganic-based insulating material. In some embodiments of the present inventive concept, the insulating base layer 121 may be formed of glass, ceramic, and/or ceramic glass.
The plurality of through electrodes 123 may vertically penetrate the insulating base layer 121. In other words, each through electrode 123 may extend in the vertical direction (e.g., the Z direction) from the upper surface 1211 of the insulating base layer 121 to the lower surface of the insulating base layer 121. The plurality of through electrodes 123 may be spaced apart from each other in the horizontal direction (e.g., the X direction). The plurality of through electrodes 123 may be formed of, for example, a metal such as Cu. In some embodiments of the present inventive concept, the insulating base layer 121 may correspond to a glass substrate formed of glass, and each through electrode 123 may be referred to as a through glass via.
In some embodiments of the present inventive concept, the plurality of through electrodes 123 may be arranged to have a pitch between about 10 μm and about 30 μm. Because the through electrodes 123 may be arranged at a fine pitch in the connection substrate 120, redistribution patterns connected to the through electrodes 123 (for example, the first conductive redistribution patterns 113 and second conductive redistribution patterns 173) may also be formed at a fine pitch.
The connection pads 125 may be disposed under a lower surface of the insulating base layer 121. An upper surface of each connection pad 125 may directly contact a lower surface of the corresponding through electrode 123, and a lower surface of each connection pad 125 may directly contact the corresponding first connection bump 141. Each connection pad 125 may be electrically and physically connected to the corresponding first upper pad 117 of the first redistribution structure 110 via the corresponding first connection bump 141. In some embodiments of the present inventive concept, the first connection bumps 141 may be omitted, and the connection substrate 120 may be physically and electrically connected to the first redistribution structure 110 via a conductive film (for example, an anisotropic conductive film (ACF)).
The bridge chip 150 may be mounted above the first redistribution structure 110 via the second connection bumps 143. The bridge chip 150 may be spaced apart from the connection substrate 120 in a lateral direction, and may be disposed between the first redistribution structure 110 and the second redistribution structure 170 in the vertical direction (e.g., the Z direction). In some embodiments of the present inventive concept, the bridge chip 150 may vertically overlap each of the plurality of semiconductor devices (for example, the first semiconductor device 210 and the second semiconductor device 220). For example, the bridge chip 150 may include a portion vertically overlapping the first semiconductor device 210 and a portion vertically overlapping the second semiconductor device 220.
The bridge chip 150 may provide an electrical signal path for transmitting an electrical signal between each of the plurality of semiconductor devices. The bridge chip 150 may include a semiconductor substrate, which includes a semiconductor material such as silicon, and a distribution structure that is provided on the semiconductor substrate. The distribution structure may include a bridge circuit pattern 151 configured to electrically connect each of the plurality of semiconductor devices to each other.
The plurality of conductive pillars 161 may be disposed on the bridge chip 150, and may be spaced apart from each other along an upper surface of the bridge chip 150. The plurality of conductive pillars 161 may be electrically connected to the bridge circuit pattern 151. Each of the plurality of conductive pillars 161 may have a pillar shape or cylindrical shape extending in the vertical direction (e.g., the Z direction). The plurality of conductive pillars 161 may provide an electrical signal path for transmitting an electrical signal between the bridge circuit pattern 151 and the second redistribution structure 170. The plurality of conductive pillars 161 may be configured to electrically connect between each of the plurality of semiconductor devices, together with the bridge circuit pattern 151. For example, each conductive pillar 161 may include Cu.
The first molding layer 130 may be disposed on the first redistribution structure 110, and may cover at least a portion of the connection substrate 120, at least a portion of the bridge chip 150, and at least a portion of each conductive pillar 161. An upper surface 131 of the first molding layer 130 may include a flat or substantially flat surface that is perpendicular to the vertical direction (e.g., the Z direction), and outer walls of the first molding layer 130 may be vertically aligned with outer walls of the first redistribution structure 110. In some embodiments of the present inventive concept, the first molding layer 130 may be formed of an epoxy mold compound (EMC). The EMC may include an epoxy-based resin, and an inorganic filler and/or an organic filler included in the epoxy-based resin.
In some embodiments of the present inventive concept, the first molding layer 130 may extend continuously along the sidewalls and lower surfaces of the connection substrate 120, but might not cover an upper surface of the connection substrate 120. The first molding layer 130 may fill gaps that are between the connection substrate 120 and the first redistribution structure 110, and at least partially surround the first connection bumps 141 that are provided between the connection substrate 120 and the first redistribution structure 110.
In some embodiments of the present inventive concept, the first molding layer 130 may continuously extend along sidewalls, a lower surface, and the upper surface of the bridge chip 150. The first molding layer 130 may fill a gap that is between the bridge chip 150 and the first redistribution structure 110, and surround the first connection bumps 141 that are provided between the bridge chip 150 and the first redistribution structure 110. In addition, the first molding layer 130 may extend along sidewalls of each conductive pillar 161, but might not cover an upper surface of each conductive pillar 161.
In some embodiments of the present inventive concept, the upper surface 131 of the first molding layer 130 may be substantially coplanar with the upper surface of the connection substrate 120 and/or the upper surface of each conductive pillar 161. As illustrated in
In some embodiments of the present inventive concept, a first coefficient of thermal expansion (CTE) of the first material constituting the insulating base layer (121) may be less than a second CTE of the second material constituting the first molding layer 130. In some embodiments of the present inventive concept, the second CTE of the first molding layer 130 may be about 10 ppm/° C. to about 20 ppm/° C., and the first CTE of the insulating base layer 121 may be about 0.1 ppm/°° C. to about 10 ppm/° C.
The second redistribution structure 170 may be disposed on the intermediate connection structure ML. A foot print of the second redistribution structure 170 may be the same as the foot print of the first redistribution structure 110 and the foot print of the intermediate connection structure ML. The outer walls of the second redistribution structure 170 may be vertically aligned with the outer walls of the intermediate connection structure ML. In the present inventive concept, a structure, in which the second redistribution structure 170 and the intermediate connection structure ML are combined, may be referred to as an interposer substrate.
The second redistribution structure 170 may include a second redistribution insulating layer 171 and the second conductive redistribution patterns 173.
The second redistribution insulating layer 171 may include a plurality of second sub-insulating layers stacked on each other in the vertical direction (e.g., the Z direction). For example, each of the plurality of second sub-insulating layers may have different thicknesses from each other. The material of the second redistribution insulating layer 171 may be substantially the same as the material of the first redistribution insulating layer 111. For example, each of the plurality of second sub-insulating layers may be formed of a PID material or a PSPI material.
The second conductive redistribution patterns 173 may include second conductive layers 1731 and second conductive via patterns 1733. Each of the second conductive layers 1731 may extend in the horizontal direction (for example, X direction and/or Y direction), and may be disposed at different vertical levels from one another to form a multi-layer distribution structure. The second conductive layers 1731 may be disposed on any one surface of an upper surface or a lower surface of each of the plurality of second sub-insulating layers of the second redistribution insulating layer 171. For example, the second conductive layers 1731 may include a line pattern extending along any one surface of the upper or lower surfaces of one second sub-insulating layer of the plurality of second sub-insulating layers of the second redistribution insulating layer 171. The second conductive via patterns 1733 may electrically connect the second conductive layers 1731 to each other, which are disposed at different vertical levels from one another. In some embodiments of the present inventive concept, each of the plurality of second conductive via patterns 1733 may have a tapered shape extending with a horizontal width decreasing in a direction from an upper side toward a lower side thereof. For example, the second conductive via patterns 1733 may penetrate a first second sub-insulating layer of the plurality of second sub-insulating layers, and the first second sub-insulating layer of the plurality of second sub-insulating layers may be disposed on the first molding layer 130 and the connection substrates 120. For example, the second conductive layers 1731 may be disposed on the first second sub-insulating layer, and a second second sub-insulating layer of the plurality of second sub-insulating layers may be disposed on the first second sub-insulating layer.
The second conductive redistribution patterns 173 may include upper pads 177 provided on the upper surface of the second redistribution insulating layer 171. For example, the upper pads 177 may penetrate the second redistribution insulating layer 171 to be connected to the second conductive layer 1731. For example, the upper pads 177 may be disposed on the second second sub-insulating layer of the plurality of second sub-insulating layers of the second redistribution insulating layer 171, and may penetrate the second second sub-insulating layer. The upper pads 177 may be attached to third connection bumps 231 or fourth connection bumps 233. The material of the second conductive redistribution patterns 173 may be substantially the same as the material of the first conductive redistribution patterns 113.
The second conductive redistribution patterns 173 may include second seed metal patterns 1735 extending along surfaces of the second conductive layers 1731 and surfaces of the second conductive via patterns 1733. Each of the second seed metal patterns 1735 may extend along a bottom surface of the corresponding second conductive layer 1731 and/or sidewalls and a bottom surface of the corresponding second conductive via pattern 1733. The material of the second seed metal patterns 1735 may be substantially the same as a material of the first seed metal patterns 1135.
At least a portion of the plurality of second conductive layers 1731 may be integrated together with the corresponding second conductive via pattern 1733. For example, a portion of a second conductive layer 1731 of the plurality of second conductive layers 1731 may be integrated together with the corresponding second conductive via pattern 1733 that is in contact with a lower side surface of the second conductive layer 1731. For example, the second conductive layers 1731 and the second conductive via patterns 1733 may be formed by using an electroplating process by using the second seed metal patterns 1735.
In some embodiments of the present inventive concept, a lower surface of the second redistribution insulating layer 171 may be in direct contact with the upper surface 131 of the first molding layer 130 and the upper surface 1211 of the insulating base layer 121. For example, a lower surface of the first second sub-insulating layer of the plurality of second sub-insulating layers of the second redistribution insulating layer 171 may be in direct contact with the upper surface 131 of the first molding layer 130 and the upper surface 1211 of the insulating base layer 121. At an interface between the second redistribution structure 170 and the first molding layer 130, the second redistribution insulating layer 171 may extend continuously along the upper surface 131 of the first molding layer 130. At an interface between the second redistribution structure 170 and the connection substrate 120, the second redistribution insulating layer 171 may extend continuously along the upper surface 1211 of the insulating base layer 121.
In some embodiments of the present inventive concept, an upper surface 1231 of each through electrode 123 of the connection substrate 120 may contact the corresponding second conductive via pattern 1733 among the second conductive via patterns 1733. For example, as illustrated in
In some embodiments of the present inventive concept, an upper surface (refer to 1611 in
Each of the plurality of semiconductor devices may be mounted on the second redistribution structure 170. The plurality of semiconductor devices may be mounted on the second redistribution structure 170 to be spaced apart from each other in the lateral direction. The plurality of semiconductor devices may be electrically connected to each other via the second conductive redistribution patterns 173, the plurality of conductive pillars 161, and/or the bridge circuit pattern 151 of the bridge chip 150.
In some embodiments of the present inventive concept, the plurality of semiconductor devices may include the first semiconductor device 210 and the second semiconductor device 220. The first semiconductor device 210 and the second semiconductor device 220 may include heterogeneous semiconductor devices. In some embodiments of the present inventive concept, the first semiconductor device 210 may include a logic device, and the second semiconductor device 220 may include a memory device. In some embodiments of the present inventive concept, the logic chip may include a microprocessor, a graphics processor, a signal processor, a network processor, an artificial intelligence semiconductor, a chipset, an audio codec, a video codec, and an application processor. In some embodiments of the present inventive concept, the memory chip may include a DRAM chip, an SRAM chip, an MRAM chip, a NAND flash memory chip, and/or a high bandwidth memory (HBM) chip.
The first semiconductor device 210 may be mounted on the second redistribution structure 170 via the third connection bumps 231. The first semiconductor device 210 may include the first semiconductor substrate 211 and first bump pads 213 that are provided on a lower surface of the first semiconductor substrate 211. The first bump pads 213 may be respectively attached to the third connection bumps 231, and may be electrically connected to the corresponding upper pads 177 of the second redistribution structure 170 via the third connection bumps 231, respectively. A first underfill material layer 235 formed of an underfill material may be disposed in gaps that are between the first semiconductor device 210 and the second redistribution structure 170. The first underfill material layer 235 may at least partially surround the third connection bumps 231.
The second semiconductor device 220 may be mounted on the second redistribution structure 170 via the fourth connection bumps 233. A second underfill material layer 237 formed of an underfill material may be disposed in gaps that are between a fourth semiconductor device and the second redistribution structure 170. The second underfill material layer 237 may at least partially surround the fourth connection bumps 233.
The second semiconductor device 220 may include the second semiconductor substrate 221, an upper connection pad 222, a lower connection pad 223, a connection terminal 225, a through electrode 227, and an inner molding layer 229.
The second semiconductor device 220 may include a plurality of slices, and each of the plurality of slices may include a second semiconductor substrate 221. A plurality of second semiconductor substrates 221 may constitute a chip stack and may be stacked in the vertical direction (e.g., the Z direction). The plurality of second semiconductor substrates 221 may be substantially the same as each other. In other words, the second semiconductor device 220 may have a stacked structure in which each of the plurality of slices operates as a memory chip, and data merging is possible between each other.
Each of the plurality of second semiconductor substrates 221 may have an active surface and an inactive surface facing each other. In this case, the inactive surface of the second semiconductor substrate 221 that is the uppermost second semiconductor substrate 221 of the plurality of second semiconductor substrates 221 may be an upper surface of the second semiconductor device 220 which is exposed to the outside of the semiconductor package 10. Each of the plurality of second semiconductor substrates 221 may include the through electrode 227. The through electrode 227 may include, for example, a through silicon via (TSV).
The upper connection pad 222 may be connected to an upper side of the through electrode 227, and the lower connection pad 223 may be connected to a lower side of the through electrode 227. In addition, the lower connection pad 223 may be provided on the active surface of the second semiconductor substrate 221 and may be electrically connected to a semiconductor distribution layer including a distribution pattern.
The connection terminal 225 may be disposed between two adjacent second semiconductor substrates 221 in the vertical direction (e.g., the Z direction). In addition, the second semiconductor substrate 221 that is the lowermost second semiconductor substrate 221 of the plurality of second semiconductor substrates 221 may be electrically and physically connected to the second conductive redistribution patterns 173 of the second redistribution structure 170 via the fourth connection bumps 233.
The inner molding layer 229 may at least partially surround the plurality of second semiconductor substrates 221. The inner molding layer 229 might not cover an upper surface of the uppermost second semiconductor substrate 221. The inner molding layer 229 may be formed of, for example, EMC.
The second molding layer 239 may be disposed on the second redistribution structure 170, and may cover at least a portion of each of the plurality of semiconductor devices. The second molding layer 239 may at least partially surround the sidewalls of the first semiconductor device 210, but might not cover an upper surface of the first semiconductor device 210 so that the upper surface of the first semiconductor device 210 is exposed to the outside of the semiconductor package 10. In addition, the second molding layer 239 may at least partially surround the sidewalls of the second semiconductor device 220, but might not cover the upper surface of the second semiconductor device 220 so that the upper surface of the second semiconductor device 220 is exposed to the outside of the semiconductor package 10. The second molding layer 239 may be formed of, for example, EMC.
According to some embodiments of the present inventive concept, the insulating base layer 121 of the connection substrate 120 may include a material having a CTE less than that of a material constituting the first molding layer 130 so that the connection substrate 120 may function as a reinforcement member configured to strengthen rigidity of the semiconductor package 10, and accordingly, warpage of the semiconductor package 10 may be prevented.
Referring to
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To form the first redistribution structure 110, an external connection pad 115 may be first formed on the carrier substrate CA. The external connection pad 115 may be formed by using a plating process. For example, after the first seed metal pattern 1135 is formed on the carrier substrate CA, the external connection pad 115 may be formed by performing a plating process by using the first seed metal pattern 1135. After the external connection pad 115 is formed, a metal wiring process may be performed to form an insulating layer, which covers the external connection pad 115 but has a via hole, the first conductive via pattern 1133, which fills the via hole of the insulating layer, and the first conductive layer 1131, which extends along an upper surface of the insulating layer. The metal wiring process for forming the first conductive via patterns 1133 and the first conductive layer 1131 may include a plating process by using the first seed metal pattern 1135. Next, by performing each of the insulating layer forming process and the metal distribution process for at least one time, the first redistribution structure 110 having a multi-layer distribution structure may be formed.
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To form the second redistribution structure 170, a metal distribution process may be performed to form an insulating layer, which includes via holes, on the upper surface of the intermediate connection structure ML. The metal distribution process may also be performed to form the second conductive via patterns 1733, which fill the via holes of the insulating layer, and the second conductive layer 1731, which extends along an upper surface of the insulating layer. The metal wiring process for forming the second conductive via patterns 1733 and the second conductive layer 1731 may include a plating process using the second seed metal patterns 1735. Next, by performing each of the insulating layer forming process and the metal distribution process for at least one time, the second redistribution structure 170 having a multi-layer distribution structure may be formed.
Next, referring to
While the present inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes in form and detail may be made thereto without departing from the spirit and scope of the present inventive concept.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0076423 | Jun 2023 | KR | national |
