Patent Application
20160225851
The present invention belongs to a field of super-large scale integrated circuit manufacturing technologies and relates to multilayer superfine silicon lines structure and a method for preparing the same, and in particular, to a method for preparing location-shape-controllable multilayer superfine silicon lines by combining a fin-shaped silicon island sidewall mask technology and a silicon anisotropic corrosion technology.
As Moore law progresses to a 22 nm process node, traditional planar devices can no longer meet the requirement of Moore law, because the performance thereof degrades seriously due to the short channel effect and the reliability problem of the devices. A three-dimensional multi-gate device (Multi-gate MOSFET, MuGFET) taking a fin-shaped field effect transistor (FinFET) as representative realizes mass production successfully at the 22 nm node due to its outstanding capacity for inhibiting short channel effect and advantages such as high integration density and compatibility with traditional CMOS processes.
Among the three-dimensional multi-gate devices, Multi-Bridge-Channel Gate-all-around Nanowire FET (MBC GAA NWFET) becomes a strong competitor after progressing to 22 nm node due to its advantages such as outstanding gate control ability, ultra-high integration density and ultra-high drive current, etc.
One of the key technologies for manufacturing a Multi-Bridge-Channel Gate-all-around Nanowire FET is to prepare multilayer superfine silicon lines with location and sectional shape being uniform and controllable.
Ricky M. Y. Ng group from Hongkong Science and Technology University forms multilayer nanowires arranged from top to bottom by combining the Bosch process and sacrificial oxidization during Inductively Coupled Plasma (ICP) Etching [M. Y. Ng Ricky, et al., EDL, 2009, 30 (5) : 520˜522]. However, the location and sectional shape of the nanowire formed by this method are uncontrollable due to process fluctuation, thereby causing device performance serious fluctuation.
Sung-Young Lee, et al., from Samsung Electronics, Korea, successfully prepare a Multi-Bridge-Channel FET on a bulk silicon substrate by taking SiGe as a sacrificial layer [Sung-Young Lee, et al., TED, 2003, 2 (4): 253-257.]. The key technology thereof is to obtain a Si—SiGe superlattice structure by epitaxy on a bulk silicon and obtain a multilayer hanging channel by removing the SiGe sacrificial layer via wet corrosion. However, the quality and thickness of each layer of film in the superlattice structure are limited by factors such as lattice mismatch and stress release, etc., and the process is relatively complex.
Therefore, it is in urgent need for a structure of multilayer superfine silicon lines and a method for preparing the same, which not only has a high integration density but also can overcome the defects of the prior art.
The invention provides a semiconductor structure and a method for forming the same, thereby improving the prior art technology.
Instruction for Terms: according to the definition in Chapter 1 of Semiconductor Physics written by Ye Liangxiu, (100), (110), (111) and (112) are Miller indices of a crystal face; <100>, <110>, <111> and <112> are crystal orientation indices.
The invention provides a semiconductor structure, which includes: a semiconductor substrate and multilayer superfine silicon lines, wherein, a profile shape of each of the multilayer superfine silicon lines is controlled dually by a crystal orientation of the substrate and an axial crystal orientation of the lines:
for the multilayer superfine silicon lines along <110> on (100) substrate, a top-layer line has a section of a pentagon, which is enclosed by one (100) crystal face, two (110) crystal faces and two (111) crystal faces; and each of lower-layer lines has a section of a hexagon, which is enclosed by two (110) crystal faces and four (111) crystal faces;
for the multilayer superfine silicon lines along <110> on (110) substrate, a top-layer line has a section of a pentagon, which is enclosed by one (110) crystal face, two (100) crystal faces and two (111) crystal faces; and the section of each of lower-layer lines has a section of a hexagon, which is enclosed by two (100) crystal faces and four (111) crystal faces;
for the multilayer superfine silicon lines along <110> on (111) substrate, each of the lines has a section of a rectangle, which is enclosed by two (111) crystal faces and two (112) crystal faces.
At the same time, the invention provides a method for forming a semiconductor structure, comprising:
A) providing a semiconductor substrate;
B) forming a fin-shaped silicon island (Fin);
In order to ensure that the anisotropic corrosion for the sidewall of the Fin can stop automatically on (111) crystal face so as to form the hanging multilayer superfine silicon lines with a polygonal section, the crystal orientation of the substrate, the length direction of the Fin and the crystal orientation of the sidewall should meet the following conditions: for (100) substrate, the length direction of the Fin and the crystal orientation of the sidewall thereof are both along <110>; for (110) substrate, the length direction of the Fin is along <110>, and the crystal orientation of the sidewall thereof is along <100>; and for (111) substrate, the length direction of the Fin is along <110>, and the crystal orientation of the sidewall thereof is along <112>;
An aspect ratio of the Fin should be selected to meet the requirement for a number of the layers of the fine lines finally formed;
C) forming a sidewall corrosion shielding layer of the Fin (sidewall mask technology);
The number and locations of the corrosion shielding layers define the number and locations of the layers of the fine lines; a layer-to-layer distance of the layers of the fine lines is defined by the thickness of the sacrificial layer, and in order to ensure that the multilayer superfine silicon lines formed after step D1 are completely separated upper and lower, the thickness (H) of the sacrificial layer and the width (WFin) of the Fin should meet the following conditions: for (100) substrate, H>WFin*tan 54.7°; for (110) substrate, H>WFin*cot 54.7°; for (111) substrate, H>0; wherein, 54.7° is an included angle between the (100) crystal face and the (111) crystal face of silicon;
It specifically comprises the steps of:
C1) preparing a sacrificial layer, including:
C2) preparing the corrosion shielding layer, including:
C3) repeating the steps C1, C2 alternately, and forming a stacked structure of cyclic “sacrificial layer-corrosion shielding layer” on the sidewall of the Fin;
C4) depositing a corrosion shielding layer on top of the Fin;
C5) defining a wet corrosion window for silicon on the stacked structure of cyclic “sacrificial layer-corrosion shielding layer” via photolithography;
C6) transferring a pattern defined by photolithography to the stacked structure of “sacrificial layer-corrosion shielding layer” via an anisotropic etching process to expose the silicon substrate;
C7) removing the sacrificial layer;
D) forming multilayer superfine silicon lines by performing anisotropic corrosion to the Fin from the sidewall thereof, wherein under the protection of the sidewall corrosion shielding layer, the corrosion finally stops automatically on (111) crystal face to form the multilayer superfine silicon lines with a polygonal section, which specifically includes the steps of:
D1) forming the multilayer superfine silicon lines with the polygonal section via anisotropic corrosion; and
D2) removing the corrosion shielding layer from the multilayer superfine silicon lines.
Further, in step D2, after the removing of the corrosion shielding layer, performing sacrificial oxidization so that the sections of the multilayer superfine silicon lines may be changed to be circular and the radius thereof may be further reduced; the sacrificial oxidization is dry oxidization, and the temperature is 850-950° C., and preferably 925° C.;
Further, a source-drain region or an STI region in micrometer scale that is connected with the two ends of the Fin formed by step B may ensure that there is enough silicon as a support for the two ends of the multilayer superfine silicon lines formed by step D1;
Further, the depositing performed in step C1, C2 and C4 may be selected from Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Inductively Coupled Plasma Enhance Chemical Vapor Deposition (ICPECVD) or sputtering, etc.,.
Further, SiO2 may be selected as the sacrificial layer material, and a BHF solution is employed for the release of the SiO2 sacrificial layer, wherein the concentration of the BHF solution is HF:NH4F=1:30˜1:100, and preferably 1:40, and the corrosion temperature is a room temperature; Si3N4 may be selected as the corrosion shielding layer material; concentrated phosphoric acid is employed for the removing of the Si3N4 corrosion shielding layer; and the corrosion temperature is 170° C.
Further, a combination of the sacrificial layer material and the corrosion shielding layer material is not limited to SiO2 and Si3N4, but they should meet the following conditions: the etching speed ratio of the sacrificial layer to the photoresist is greater than 5:1; the etching speed ratio of the corrosion shielding layer to the photoresist is greater than 5:1; the etching speed ratio of the sacrificial layer to silicon is greater than 5:1; and the etching speed ratio of the corrosion shielding layer to silicon is greater than 5:1.
Further, a Tetramethyl Ammonium Hydroxide (TMAH) solution is employed for the anisotropic corrosion for the silicon; the concentration of the TMAH solution is 10˜25 wt %, and preferably, 25 wt %; a corrosion temperature is 35˜60° C., and preferably 40° C.
The invention further provides a Multi-Bridge-Channel Gate-all-around Nanowire FET, wherein the multilayer superfine silicon lines are prepared by the above method for forming a semiconductor structure, and then the Multi-Bridge-Channel Gate-all-around Nanowire FET may be formed by a standard CMOS process.
The invention has the following advantages and positive effects:
1) The locations and the sectional shapes of the multilayer superfine silicon lines finally formed are uniform and controllable;
2) The anisotropic corrosion for silicon stop automatically, the process window is large, and silicon lines with different diameters may be achieved from the same silicon wafer;
3) ICPECVD has a stronger narrow groove filling ability so that no cavity occurs when deposing the sacrificial layer material and the corrosion shielding layer material;
4) Lines with a size less than 10nm may be prepared in conjunction with the oxidization technology, meeting the key process requirements for small-size devices;
5) For the wet corrosion for polysilicon by a TMAH solution, the operation is simple, convenient and safe, and no metallic ion will be introduced, thus it is applicable for the integrated circuit manufacturing process; and
6) A method of processing from top to bottom is employed, which may be fully compatible with the bulk silicon planar transistor process, with a lower process cost.
The invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
A 2-bridge circular nanowire structure with a diameter of about 10 nm may be achieved according to the following steps of:
1) thermally growing SiO2 of a thickness 50 Å, on a (111) bulk silicon substrate, as a stress buffer layer between a hard mask and the silicon substrate;
2) depositing Si3N4 of a thickness 100 Å as etch hard mask via LPCVD;
3) defining a pattern of a Fin and a source-drain region connected with two ends of the Fin on the hard mask via photolithography, wherein the Fin structure has a width of 20 nm and a length of 300 nm, with a length direction along <110> and sidewalls each having a crystal orientation <110>;
4) transferring the pattern to the hard mask via anisotropic etching to expose the silicon substrate;
5) transferring the pattern on the hard mask to the silicon substrate via anisotropic etching to form the Fin and the source-drain region connected with the two ends of the Fin, wherein the Fin structure has a height of 1000 Å, the width of 20 nm and the length of 300 nm, with the length direction along <110> and the sidewalls each having the crystal orientation <110>;
6) removing photoresist;
7) removing the etch hard mask of Si3N4 with hot (170° C.) concentrated phosphoric acid;
8) removing the stress buffer layer of SiO2 with a BHF solution (HF:NH4F=1:40), as shown in
9) depositing SiO2 of a thickness 1500 Å via ICPECVD;
10) exposing the top of the Fin through Chemical Mechanical Polishing (CMP), as shown in
11) removing the SiO2 of a thickness 700 Å via anisotropic etching, with the SiO2 of a thickness 300 Å retained as a first sacrificial layer, as shown in
12) depositing Si3N4 of a thickness 1200 Å via ICPECVD;
13) exposing the top of the Fin via CMP, as shown in
14) removing the Si3N4 of a thickness 500 Å via anisotropic etching, with the Si3N4of a thickness 200 Å retained as a first corrosion shielding layer for silicon, as shown in
15) depositing SiO2 of a thickness 1000 Å via ICPECVD;
16) exposing the top of the Fin via CMP;
17) removing the SiO2 of a thickness 200 Å via anisotropic etching, with the SiO2 of a thickness 50 Å 300 Å retained as a second sacrificial layer, as shown in
18) depositing Si3N4 of a thickness 1500 Å via ICPECVD;
19) retaining the Si3N4 of a thickness 100 Å as a corrosion shielding layer for silicon on the top via CMP, as shown in
20) defining a corrosion window for silicon via electron beam photolithography;
21) removing SiO2—Si3N4 stacked materials in the window via anisotropic dry etching to expose the silicon on a bottom;
22) removing photoresist, as shown in
23) removing the sacrificial layer of SiO2 via a BHF solution (HF:NH4F=1:40), as shown in
24) performing anisotropic corrosion on the silicon via a TMAH solution with a concentration of 25 wt % at 40° C. so as to completely separating a upper fine line and a lower fine line, as shown in
25) removing the corrosion shielding layer of Si3N4 via hot (170° C.) concentrated phosphoric acid;
26) performing dry-oxygen oxidization at 925° C. to obtain a silicon nanowire with a circular section and a diameter of 5 nm;
27) removing an oxide layer enwrapping around the silicon nanowire via a BHF solution (HF:NH4F=1:40), as shown in
Finally, the 2-bridge nanowire structure with a diameter of about 5 nm is obtained.
A 2-bridge quadratic nanowire structure with a diameter of about 5 nm may be achieved according to the following steps of:
1) thermally growing SiO2 of a thickness 50 Å, on a (100) bulk silicon substrate, as a stress buffer layer between a hard mask and the silicon substrate;
2) depositing Si3N4 of a thickness 100 < via LPCVD as etch hard mask;
3) defining a pattern of a Fin and a source-drain region connected with two ends of the Fin on the hard mask via photolithography, wherein the Fin structure has a width of 10 nm and a length of 300 nm, with a length direction along <110> and sidewalls each having a crystal orientation <112>;
4) transferring the pattern to the hard mask via anisotropic etching to expose the silicon substrate;
5) transferring the pattern on the hard mask to the silicon substrate via anisotropic etching to form the Fin and the source-drain region connected with the two ends of the Fin, wherein the Fin structure has a height of 1000 Å, the width of 10 nm and the length of 300 nm, with the length direction along <110> and the sidewalls each having the crystal orientation <112>;
6) removing photoresist;
7) removing the etch hard mask of Si3N4 with hot (170° C.) concentrated phosphoric acid;
8) removing the stress buffer layer of SiO2 with a BHF solution (HF:NH4F=1:40);
9) depositing SiO2 of a thickness 1500 Å via ICPECVD;
10) exposing the top of the Fin through Chemical Mechanical Polishing (CMP);
11) removing the SiO2 of a thickness 700 Å via anisotropic etching, with the SiO2 of a thickness 300 Å retained as the first sacrificial layer;
12) depositing Si3N4 of a thickness 1200 Å via ICPECVD;
13) exposing the top of the Fin via CMP;
14) removing the Si3N4 of a thickness 500 Å via anisotropic etching, with the Si3N4 of a thickness 200 Å retained as the first corrosion shielding layer for silicon;
15) depositing SiO2 of a thickness 1000 Å via ICPECVD;
16) exposing the top of the Fin via CMP;
17) removing the SiO2 of a thickness 200 Å via anisotropic etching, with the SiO2 of a thickness 300 Å retained as a second sacrificial layer;
18) depositing Si3N4 of a thickness 1500 Å via ICPECVD;
19) retaining the Si3N4 of a thickness 100 Å as a corrosion shielding layer for silicon on the top via CMP;
20) defining a corrosion window for silicon via electron beam photolithography;
21) removing SiO2—Si3N4 stacked materials in the window via anisotropic dry etching to expose the silicon on a bottom;
22) removing photoresist;
23) removing the sacrificial layer of SiO2 with a BHF solution (HF:NH4F=1:40);
24) performing anisotropic corrosion on the silicon via a TMAH solution with a concentration of 25 wt % at 40° C. so as to completely separating a upper fine line and a lower fine line, as shown in
25) removing the corrosion shielding layer of Si3N4 via hot (170° C.) concentrated phosphoric acid;
Finally, the 2-bridge nanowire structure with a quadratic section having a diameter of about 10 nm, is obtained.
A 3-bridge nanowire structure with a diameter of about 10 nm is prepared.
1) thermally growing SiO2 of a thickness 50 Å, on a (110) bulk silicon substrate, as a stress buffer layer between etch hard mask and the silicon substrate;
2) depositing Si3N4 of a thickness 100 Å via LPCVD as the etch hard mask for silicon;
3) defining a pattern of a Fin and a source-drain region connected with two ends of the Fin via photolithography, wherein the Fin structure has a width of 30 nm and a length of 300 nm, with a length direction along <110> and a sidewall having a crystal orientation <100>;
4) transferring the pattern to the hard mask via anisotropic etching to expose the silicon substrate;
5) transferring the pattern on the hard mask to the silicon substrate via anisotropic etching to form the Fin and the source-drain region connected with the two ends of the Fin, wherein the Fin structure has a height of 2100 Å, the width of 30 nm and the length of 300 nm, with the length direction along <110> and the sidewall having the crystal orientation <100>;
6) removing photoresist;
7) removing the etch hard mask of Si3N4 with hot (170° C.) concentrated phosphoric acid;
8) removing the stress buffer layer of SiO2 with a BHF solution (HF:NH4F=1:40);
9) depositing polycrystalline germanium of a thickness 2500 Å via ICPECVD;
10) exposing the top of the Fin through Chemical Mechanical Polishing (CMP);
11) removing the polycrystalline germanium of a thickness 1600 Å via anisotropic etching, with the polycrystalline germanium of a thickness 500 Å retained as a first sacrificial layer;
12) depositing SiO2 of a thickness 2000 Å via ICPECVD;
13) exposing the top of the Fin via CMP;
14) removing the SiO2 of a thickness 1400 Å via anisotropic etching, with the SiO2 of a thickness 200 Å retained as a first corrosion shielding layer for silicon;
15) depositing polycrystalline germanium of a thickness 1800 Å via ICPECVD;
16) exposing the top of the Fin via CMP;
17) removing the polycrystalline germanium of a thickness 900 Å via anisotropic etching, with the polycrystalline germanium of a thickness 500 Å retained as a second sacrificial layer;
18) depositing SiO2 of a thickness 1300 Å via ICPECVD;
19) exposing the top of the Fin via CMP;
20) removing the 700 A SiO2 via anisotropic etching, retaining 200 Å SiO2 as a corrosion shielding layer for the second layer of silicon;
21) depositing polycrystalline germanium of a thickness 1100 Å via ICPECVD;
22) exposing the top of the Fin via CMP;
23) removing the polycrystalline germanium of a thickness 200 Å via anisotropic etching, with the polycrystalline germanium of a thickness 500 Å retained as a third sacrificial layer;
24) depositing SiO2 of a thickness 1500 Å via ICPECVD;
25) retaining the SiO2 of a thickness 1000 Å via CMP as a corrosion shielding layer for silicon on the top;
26) defining a corrosion window for silicon via 193 nm immersed photolithography;
27) removing the polycrystalline germanium- SiO2 stacked materials in the window via anisotropic dry etching to expose the silicon on a bottom;
28) removing photoresist;
29) removing the sacrificial layer of germanium via a mixed solution of aqua ammonia and hydrogen peroxide (NH4OH:H2O2H2O=2:2:5) at room temperature;
30) performing anisotropic corrosion on the silicon via a TMAH solution with a concentration of 25 wt % at 40° C. so as to completely separating a upper and a lower fine lines, as shown in
31) removing the corrosion shielding layer of SiO2 via a BHF solution (HF:NH4F=1:40);
32) performing dry-oxygen oxidization at 925° C. to obtain a silicon nanowire with a circular section and a diameter of 5 nm;
33) removing an oxide layer enwrapping around the silicon nanowire via a BHF solution (HF:NH4F=1:40);
Finally, the 3-bridge nanowire structure with a diameter of about 10 nm is obtained.
The embodiments of the invention are not used to limit the invention. Various possible variations and modifications or equivalent substitutions may be made to the technical solutions of the invention based on the above disclosed method and technology by any one skilled in the art without departing from the scope of the technical solutions of the invention. Therefore, any simple changes, equivalent variations and modifications to the above embodiments based on the technical essence of the invention, without departing from the technical solutions of the invention, all fall into the protection scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201410275700.1 | Jun 2014 | CN | national |
This present application is a U.S. national phase application filed under 35 U.S.C. §371 of International Patent Application No. PCT/CN 2015/077399, entitled SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME, filed on Apr. 24, 2015, which application claims the benefit of CN Application No. 201410275700.1 filed on Jun. 19, 2014, the disclosures of which are herein incorporated by reference in their entireties.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2015/077399 | 4/24/2015 | WO | 00 |
