The invention relates to the field of semiconductors, in particular to a semiconductor structure with stacked passive elements (such as deep trench capacitors).
With the development of semiconductor technology, the size of various electronic components is getting smaller and smaller. How to accommodate more electronic components in a limited unit space is the sustainable development direction and goal of this field. Capacitance structure has the function of storing charge, so it is often used to make one of the main components of various semiconductor electronic devices such as memory.
The conventional planar capacitor structure includes three layers, in which an insulating layer is sandwiched between two metal layers. However, with the development of technology, the requirements for the storage charge of capacitors are gradually increasing. If the manufacturer wants to make a capacitor that can store more charges, it need to increase the area of the capacitor, that is to say, increase the area of the metal layer and the insulating layer, but at the same time, the capacitor will occupy a larger area of the semiconductor device, which is not conducive to the miniaturization of the product.
The invention provides a semiconductor structure, which comprises a first substrate and a second substrate stacked with each other, wherein a first passive element is located in the first substrate and a second passive element is located in the second substrate. A first wire layer is located on a top surface of the first substrate and electrically connected with the first passive element, and a first conductive pad is located on a bottom surface of the second substrate and directly contacts the first wire layer.
The invention also provides a semiconductor structure, which comprises a first substrate and a second substrate stacked with each other. A first passive element is located in the first substrate, and a second passive element is located in the second substrate. A first wire layer is located on a top surface of the first substrate and is electrically connected with the first passive element. A first conductive pad is located on a bottom surface of the second substrate, and a conductive bump is located between the first substrate and the second substrate and directly contacts the first wire layer and the first conductive pad.
The present invention is characterized by providing a stacked structure of semiconductor passive elements, such as deep trench capacitors (DTC). In order to improve the charge that can be accommodated by the capacitor structure in a cell, at least two or more substrates containing deep trench capacitors are stacked and electrically connected to each other. The stacking method may include stacking a plurality of substrates with a hybrid bond or a conductive bump. The structure provided by the invention is compatible with the current technologies, the size of the deep trench capacitor does not need to be redesigned, and since the area or height of each original deep trench capacitor is not changed, the problem that the occupied area is too large to affect other devices or the through silicon via is not easy to form due to the height is too large will not occur.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
To provide a better understanding of the present invention to users skilled in the technology of the present invention, preferred embodiments are detailed as follows. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to clarify the contents and the effects to be achieved.
Please note that the figures are only for illustration and the figures may not be to scale. The scale may be further modified according to different design considerations. When referring to the words “up” or “down” that describe the relationship between components in the text, it is well known in the art and should be clearly understood that these words refer to relative positions that can be inverted to obtain a similar structure, and these structures should therefore not be precluded from the scope of the claims in the present invention.
Please refer to
However, with the continuous progress of technology, the requirements for the capacitance value of electronic components have gradually increased. The passive element 100 (for example, deep trench capacitor) shown in the above-mentioned
However, the above two possible ways to increase the capacitance have their limitations. Firstly, increasing the planar area of the capacitor will increase the occupied area of the capacitor structure in the whole semiconductor device, and may even reduce the formation space of other elements. On the other hand, if the depth of each trench is increased, the aspect ratio of each trench will also be increased, and the gap filling ability of each material layer will be reduced, which will enhance the difficulty of the process. In addition, while increasing the depth of the trench, it is also necessary to provide a thicker substrate 110. If the thickness of the substrate 110 is too large, it is not conducive to the formation of subsequent through silicon via (TSV) structures.
Therefore, the present invention provides a semiconductor structure, which can improve the overall capacitance value without changing the size of each passive element (such as deep trench capacitor), as shown in detail below.
Please refer to
In this embodiment, the first substrate 10 and the second substrate 20 comprise silicon substrates, the first substrate 10 and the second substrate 20 are connected with each other by hybrid bond contact, so that the first passive element 12 and the second passive element 22 are electrically connected with each other. More specifically, the first substrate 10 includes a top surface 10A and a bottom surface 10B, and the second substrate 20 includes a top surface 20A and a bottom surface 20B, a first dielectric layer 14 disposed on the top surface 10A of the first substrate 10, which means that the first dielectric layer 14 contacts the top surface 10A of the first substrate 10 and the bottom surface 20B of the second substrate 20. In addition, a second dielectric layer 24 disposed on the top surface 20A of the second substrate 20. The materials of the first dielectric layer 14 and the second dielectric layer 24 described here include, for example, silicon oxide, silicon nitride or silicon oxynitride, but are not limited thereto.
In addition, the first wire layer 16 is located in the first dielectric layer 14, and a second wire layer 26 is located in the second dielectric layer 24. Besides, a conductive pad P is located in the first dielectric layer 14 and contacts the bottom surface 20B of the second substrate 20, and the contact plug V is located in the second substrate 20 and the second dielectric layer 24, and penetrates through the second substrate 20 and the second dielectric layer 24. The main materials of the first wire layer 16, the second wire layer 26, the conductive pad P and the contact plug V mentioned here include metals with good conductivity, such as copper (Cu), chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) and silver (Ag) or alloys of the above materials, but not limited thereto. The main purpose of forming the above elements is to electrically connect the first passive element 12 in the first substrate 10 to the second passive element 22 in the second substrate 20.
In more detail, as shown in
In addition, in
In
For example,
It is worth noting that in the above embodiment, the contact plug V directly contacts the conductive pad P to achieve the effect of electrical connection. This technology of direct contact between conductive pads and other adjacent components (such as wires) is also called hybrid bond technology. Hybrid bond technology allows higher density components to be bonded with each other. In this embodiment, hybrid bond contacts are combined with multiple deep trench capacitors, so that the passive elements (such as the deep trench capacitors) can be stacked and electrically connected with each other. When the passive elements are deep trench capacitors, the capacitance values of the deep trench capacitors can be added.
The following description will detail the different embodiments of the semiconductor structure and the manufacturing method of the present invention. To simplify the description, the following description will detail the dissimilarities among the different embodiments and the identical features will not be redundantly described. In order to compare the differences between the embodiments easily, the identical components in each of the following embodiments are marked with identical symbols.
In addition to stacking and electrically connecting passive elements with hybrid bond technology, the invention can also stack and electrically connect passive elements with each other in other methods. For example,
The difference between this embodiment and the embodiment shown in
In addition, in the embodiment shown in
In practical application, the structure of the embodiment shown in
Therefore, in the present invention, the first substrate 10 and the second substrate 20 are arranged between the circuit substrate S (such as a printed circuit board) and the electronic component 40 (such as a chip) and can be used as an interposer between them. In the general technology, the interposer includes a conductive wire layers or conductive plugs for conducting current, and its function is to connect the pin of a tiny chip to the pin of a larger circuit board, which usually does not include other components. A feature of this embodiment is that the interposer (the first substrate 10 and the second substrate 20) contains a capacitor unit CU and the conductive plugs V2 for connecting the upper electronic component 40 and the lower circuit substrate S, the conductive plug V2 electrically connects the conductive bump 29 (such as a solder bump) with the electronic component 40 or the circuit substrate S. In other words, the first substrate 10 and the second substrate 20 in the present invention are used as an interposer layer, so they do not include active devices such as transistors.
The stacked structure of the capacitor units CU included in the embodiment shown in
In addition, it is worth noting that in various embodiments of the present invention, passive elements are all formed in a silicon substrate, that is, in the actual manufacturing process, passive elements can be manufactured on the same wafer (the silicon substrate) to form a plurality of passive elements such as deep trench capacitors, and then the wafer is cut to form a substrate containing passive elements similar to that shown in
Based on the above description and drawings, the present invention provides a semiconductor structure, which comprises a first substrate 10 and a second substrate 20 stacked with each other. A first passive element 12 is located in the first substrate 10 and a second passive element 22 is located in the second substrate 20. A first wire layer 16 is disposed on a top surface 10A of the first substrate 10 and electrically connected to the first passive element 12. A conductive pad (the conductive pad P located between the first wire layer 16 and the second substrate 20 in
In some embodiments of the present invention, the first substrate 10 and the second substrate 20 comprise silicon substrates.
In some embodiments of the present invention, the first passive element 12 and the second passive element 22 include deep trench capacitors.
In some embodiments of the present invention, the deep trench capacitor comprises a first electrode layer 112, an insulating layer 114 and a second electrode layer 116, which are located in a plurality of parallel trenches in the first substrate 10 or the second substrate 20.
In some embodiments of the present invention, a first dielectric layer 14 is located between the first substrate 10 and the second substrate 20, and the first wire layer 16 and the conductive pad P are located in the first dielectric layer 14.
In some embodiments of the present invention, a circuit substrate S is further included, which is located below the first substrate 10 and electrically connected with the first passive element 12.
In some embodiments of the present invention, an electronic component 40, such as a chip, is located above the second substrate 20 and electrically connected to the second passive element 22.
In some embodiments of the present invention, there is further included a conductive plug V penetrating through the second substrate 20 and electrically connected with the conductive pad P.
In some embodiments of the present invention, a second wire layer 26 is located on the top surface of the second substrate 20, and the second wire layer 26 is electrically connected to the second passive element 22 and the conductive plug V.
The present invention further provides a semiconductor structure, which comprises a first substrate 10 and a second substrate 20 stacked with each other. A first passive element 12 is disposed in the first substrate 10 and a second passive element 22 is disposed in the second substrate 20. A first wire layer 16 is disposed on a top surface 10A of the first substrate 10, and the first wire layer 16 is electrically connected to the first passive element 12. A conductive pad (the conductive pad P between the conductive bump B and the second substrate 20 in
In some embodiments of the present invention, a first dielectric layer 14 is further included, which is located on the top surface 10A of the first substrate 10, the first wire layer 16 is located in the first dielectric layer 14.
In some embodiments of the present invention, a bottom dielectric layer 25 is further included, which is located on the bottom surface 20B of the second substrate 20, the conductive pad P is located in the bottom dielectric layer 25.
In some embodiments of the present invention, a filling layer 30 is further included, which is located between the first dielectric layer 10 and the bottom dielectric layer 25, the conductive bump B is located in the filling layer 30.
In some embodiments of the present invention, a conductive plug V penetrates through the second substrate 20, and the conductive plug V is electrically connected with the conductive bump B through the conductive pad P.
In some embodiments of the present invention, a second wire layer 26 is located on a top surface 20A of the second substrate 20, wherein the second wire layer 26 is electrically connected to the conductive plug V.
The present invention is characterized by providing a stacked structure of semiconductor passive elements, such as deep trench capacitors (DTC). In order to improve the charge that can be accommodated by the capacitor structure in a cell, at least two or more substrates containing deep trench capacitors are stacked and electrically connected to each other. The stacking method may include stacking a plurality of substrates with a hybrid bond or a conductive bump. The structure provided by the invention is compatible with the current technologies, the size of the deep trench capacitor does not need to be redesigned, and since the area or height of each original deep trench capacitor is not changed, the problem that the occupied area is too large to affect other devices or the through silicon via is not easy to form due to the height is too large will not occur.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Number | Date | Country | Kind |
---|---|---|---|
112144882 | Nov 2023 | TW | national |