Patent Application
20060068540
As the semiconductor manufacturing industry moves towards smaller feature sizes, the size and aspect ratio for trenches and vias used in shallow trench isolation (STI), pre-metal dielectric, and other isolation structures provides more challenges. Newer devices are being built using 90-nanometer (nm) or sub-90 nm processes, and STI trenches for these devices often have aspect ratios of 4.5:1 and higher. At these smaller sizes, the use of conventional gap-filling deposition processes, as described below, leads to a greater incidence of problems such as voids or cracking in trenches and vias. Other problems also increase, such as poor insulation due to low quality dielectric material being present within trenches and vias after gap fill, and the creation of large topographical surface variations post chemical vapor deposition which may pose great problems for subsequent chemical mechanical planarization (CMP) processes.
Plasma enhanced chemical vapor deposition (PECVD) is one commonly used technique in which one or more gaseous reactors are used to form a solid insulating or conducting layer on the surface of a substrate enhanced by the use of plasma. This process is advantageous because it may be used at lower temperatures. In general, PECVD enables gap fill with aspect ratios up to 3:1 to be filled. One drawback is that multiple PECVD/sputter sequential processes need to be carried out to completely fill a gap with a high aspect ratio. Even after multiple process sequences, the processes still tend to leave voids or seams in the trenches and the quality of the PECVD fill is still inferior to another deposition technique, known as high-density plasma chemical vapor deposition (HDPCVD). This process uses a higher density plasma and is known to fill gaps with aspect ratios of around 4.5:1. In some cases, the addition of species such as Helium, Hydrogen, NF3, and SiF4 to the deposition chemistry may be used to improve gap fill capabilities for aspect ratios up to 6:1. Gaps with higher aspect ratios, however, may not adequately be filled using HDPCVD.
Other techniques for filling gaps are low pressure chemical vapor deposition (LPCVD) and sub-atmospheric chemical vapor deposition (SACVD), both of which are performed in a vacuum environment. These processes use the chemical reaction of gaseous compounds to provide a conformal deposition. Gap fill isolation using LPCVD or SACVD is a single step, highly conformal deposition. Gaps with aspect ratios as high as 5:1 or more may be filled with this process, however, weak seams often develop in the middle of the filled valley, resulting in device failure.
Spin-on dielectrics (SOD) using silicon derivatives as a stand-alone process may be used for gap fill isolation, and have been known to fill gaps with aspect ratios as high as 10:1. The problem with SODs, however, is that the gap fill materials derived from SOD tend to have poor electrical or mechanical properties due to heterogeneous densification, high shrinkage, and incomplete oxidation. Cracking or low quality dielectric material being present within trenches and vias after gap-filling using SOD is common. Another technique that has been used is an SOD deposition followed by one of the chemical vapor deposition (CVD) processes described above. The SOD process improves the aspect ratio of the gap and the subsequent CVD process fills the gap. This technique is not suitable for sub-90 nm applications because as device dimensions decrease, the low quality SOD materials may not provide adequate electrical insulation for the smaller devices and electrical field breakdowns and leakage tend to occur.
Accordingly, improved deposition processes are needed to provide higher quality gap fill isolation for smaller devices, such as devices built using 90 nm and sub-90 nm ultra large scale integration (ULSI) processes.
Implementations of a method to practice a sequential chemical vapor deposition (CVD) process and spin-on dielectric (SOD) process are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the implementations. One skilled in the relevant art will recognize, however, that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.
The sequential CVD-SOD process of the invention may be used in semiconductor wafer manufacturing. In one implementation the CVD-SOD process may be used to fill high-aspect ratio valleys found on a surface of a semiconductor wafer or other substrate. As used herein, the term “valley” may refer to any gaps, trenches, vias, or other voids found on the surface of the semiconductor wafer. The valleys may be found between or around active areas on the semiconductor wafer, and the gap fill isolation process electrically isolates these active areas. The invention may be applicable to, but not limited to, shallow trench isolation, pre-metal dielectric, or inter-metal dielectric deposition processes. In implementations of the invention, the CVD-SOD process may fill gaps with aspect ratios of 7:1 and higher, and gap widths of 50 nm and below.
In accordance with implementations of the invention, the valleys 104 may be filled using a sequential HDPCVD-SOD process.
If used alone, the HDP deposition generally leads to voids and may not adequately handle valleys 104 with high aspect ratios. Therefore, in accordance with the invention,
The spin-on process used to deposit the dielectric material 202 may be self-planarizing; accordingly, the dielectric material 202 may have a top surface that is substantially planarized. Furthermore, in some implementations the SOD process may leave a sacrificial layer of dielectric material 202 over the structures 102 for optimal chemical mechanical polishing (CMP). The sacrificial layer may be polished by the CMP process until a thin layer of the sacrificial layer remains atop the oxide 200, or until at least a portion of the oxide 200 is exposed.
The addition of the SOD deposition may provide void-free trench-fill after the initial HDP deposition because the SOD deposition has gap fill capability that is less sensitive to trench profiles such as reentrant trench sidewalls. In addition, the self-planarizing nature of the SOD deposition enables high within-die thickness uniformity for optimized pre and post CMP uniformity. In an implementation of the invention, the sequential process described herein may be capable of providing a gap fill capability exceeding a 7:1 aspect ratio with gap space of 50 nm or less, and optimal planarized topography to enable better CMP process control.
After the SOD process, in an implementation of the invention a thermal curing process may be carried out. The thermal curing process may be used for cross-linking, oxidation, and densification of the SOD. During the thermal curing process, organic compounds may be driven out of the SOD dielectric material 202 while oxygen molecules may be driven into the dielectric material 202.
The initial HDPCVD process may result in an oxide profile that is very favorable for the subsequent SOD thermal curing process. As shown in
In an implementation, an optional thermal curing process may be conducted after the sacrificial layer of dielectric material 202 over the structures 102 has been polished by the CMP process. Since either a thin layer or no layer of the sacrificial layer may remain atop the oxide 200 after the CMP process, the diffusion path will be shortened and therefore the SOD densification will be further improved. The shortened diffusion path may allow organics to more easily diffuse out of the dielectric material 202 and allow oxygen to more easily diffuse into the dielectric material 202.
In sub-90 nm applications, the oxide profile after the initial LPCVD or SACVD process may tend to have an open seam or a narrow void due to the conformal deposition characteristics. The seams or voids may be very small and tend to be difficult for conventional CVD processes to fill. In accordance with the invention, however, such a seam or narrow void may be filled by a subsequent SOD process. Furthermore, because the seam or void will generally have a small volume, any shrinkage that occurs due to SOD densification will have a minimal impact on the overall trench isolation performance.
After the SOD process, in an implementation of the invention a thermal curing process may be carried out. The thermal curing process may be used for cross-linking, oxidation, and densification of the SOD. As described above, during the thermal curing process organic compounds may be driven out of the dielectric material 302 while oxygen molecules may be driven in.
In some implementations, the HDPCVD process conditions for 200 nm semiconductor wafers using an Applied Materials Ultima Plus™ system may include the following:
In some implementations, the SACVD process conditions for 200 mm semiconductor wafers using an Applied Materials Ultima Plus™ system may include the following range of tetraethylorthosilicate (TEOS) based conditions:
In some implementations, the SOD process conditions may include a dielectric material composed of silicon containing polymers dissolved or dispensed in suitable solvents. The dielectric material may be applied to the substrate by spin coating under the following process conditions:
In some implementations, the SOD film may exhibit oxide-like properties after the high temperature cure. Other high energy processes may be used to achieve the same effect. The high temperature cure may also be performed after the CMP to shorten the diffusion path.
In some implementations, the SOD process conditions may include the following:
In implementations of the invention, the methods described above may be carried out on separate tools for the chemical vapor deposition process and the subsequent spin-on dielectric process. For instance, the CVD process may be carried out in a CVD chamber, and the SOD process may then be carried out on a SOD tool. In some implementations, a combined system may be used that includes a spin-on dielectric tool within a chemical vapor deposition chamber. Known CVD systems and known SOD tools may be used to carry out the methods described above.
The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, implementations of the invention include CVD processes other than HDPCVD, LPCVD, and SACVD.
These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
