Silicon-on-silicon hybrid wafer assembly

Information

  • Patent Grant
  • 6558802
  • Patent Number
    6,558,802
  • Date Filed
    Tuesday, February 29, 2000
    24 years ago
  • Date Issued
    Tuesday, May 6, 2003
    21 years ago
Abstract
A hybrid silicon-on-silicon substrate. A thin film (2101) of single-crystal silicon is bonded to a target wafer (46). A high-quality bond is formed between the thin film and the target wafer during a high-temperature annealing process. It is believed that the high-temperature annealing process forms covalent bonds between the layers at the interface (2305). The resulting hybrid wafer is suitable for use in integrated circuit manufacturing processes, similar to wafers with an epitaxial layer.
Description




BACKGROUND OF THE INVENTION




The present invention relates to the manufacture of substrates. More particularly, the invention provides a technique for manufacturing a silicon-on-silicon substrate assembly. The assembly includes two substrates that are bonded together for use in the fabrication of a substrate for semiconductor integrated circuits, for example. But it will be recognized that the invention has a wider range of applicability; it can also be applied to other substrates for multi-layered integrated circuit devices, three-dimensional packaging of integrated semiconductor devices, microelectromechanical systems (“MEMS”), sensors, actuators, solar cells, biological and biomedical devices, and the like.




Wafers for electronic device fabrication are often cut from an ingot, or boule, of material with an abrasive saw. The wafer often serves as both a mechanical substrate and a semiconductor material to form electronic devices in or on. One of the most common examples of this is cutting silicon wafers from a silicon ingot. The wafers are typically polished to a very fine surface finish after “lapping” the wafer to remove the mechanical damage left by the abrasive saw, and after “backlapping” the other side of the wafer to remove saw damage and to produce a wafer of the desired thickness. In some processes, devices are fabricated directly in or on the silicon wafer. In other processes, a layer of semiconductor material is grown, for example by epitaxy, on the wafer. The epitaxial layer may provide lower impurity concentrations, or be of a different semiconductor type than the wafer. The devices are formed in what is known as the “active” layer, which is typically only a micron or so thick.




Epitaxial layers have been used successfully on smaller wafers and for smaller devices. Unfortunately, epitaxial layers have some associated problems that critically affect wafer yield and device yield as the size of either the wafer or the device increases. Epitaxial layers that are grown on a substrate typically adopt the crystalline structure of the substrate. In most cases, the substrate is a single crystal of a particular orientation. The most favored crystallographic orientation for growing an epitaxial layer, however, may not be the most favored crystallographic orientation for forming semiconductor devices. Additionally, surface defects or contamination on the surface of the substrate can lead to “pipes”, “spikes”, and other types of defects in the epitaxial layer. Often, a single defect will ruin a particular circuit, or cell, on a substrate. As the size of the cells gets bigger and more complex, the chance that any particular cell will fail because of a defect in the epitaxy layer increases. The size of the cells generally increases, given a particular processing technology, as the device count increases, which usually indicates an increase in circuit complexity and functionality.




The size of silicon wafers also continues to increase. Many state-of-the-art semiconductor devices are fabricated on 8-inch silicon wafers. Twelve-inch wafers are available. The semiconductor fabrication industry is moving toward using wafers of this size, but, as with most changes in technology, must solve some problems first. One of the problems is that growing a high-quality epitaxial layer on a 12-inch wafer is very difficult. Some conventional processes do not have a sufficient yield of good wafers through the epitaxial growth process to make using a 12-inch wafer economically attractive. This problem is compounded by the cost of a 12-inch substrate, which can be quite high.




From the above, it is seen that a technique for providing a substitute for an epitaxial layer that is cost effective and efficient is desirable.




SUMMARY OF THE INVENTION




According to the present invention, a technique for applying a thin film of silicon material to a target, or handle, wafer is provided. This technique separates thin films of material from a donor substrate by implanting particles,such as hydrogen ions, into the donor substrate, and then separating a thin film of material above the layer of implanted particles. The thin film can be bonded to a target wafer that provides mechanical support to form a hybrid substrate before or after separation.




In a specific embodiment, the present invention provides a process for forming a film of material from a donor substrate, typically a single crystal of silicon, using a controlled cleaving process. That process includes a step of introducing energetic particles (e.g., charged or neutral molecules, atoms, or electrons having sufficient kinetic energy) through a surface of a donor substrate to a selected depth underneath the surface, where the particles are at a relatively high concentration to define a thickness of donor substrate material (e.g., thin film of detachable material) above the selected depth.




The surface of the donor wafer is then typically attached to a target wafer, that will provide mechanical support for the thin film using a low-temperature bonding process. The target wafer can be a single crystal, polycrystalline, or amorphous, depending on the desired hybrid wafer characteristics. Energy is applied to a selected region of the donor substrate material to initiate a controlled cleaving action in the donor substrate, whereupon the cleaving action is made using a propagating cleave front(s) to free the donor material from a remaining portion of the donor substrate. The thin film is then permanently bonded to the target wafer, typically with a high-temperature annealing process.




In another embodiment, a layer of microbubbles is formed at a selected depth in the substrate. The substrate is globally heated and pressure in the bubbles eventually shatters the substrate material generally in the plane of the microbubbles, separating a thin film of silicon from the substrate.




The present invention achieves these benefits and others in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.











BRIEF DESCRIPTION OF THE DRAWINGS





FIGS. 1-3

are simplified diagrams illustrating a controlled cleaving technique according to an embodiment of the present invention;





FIGS. 4-6

are simplified diagrams illustrating a blister-separation technique according to another embodiment of the present invention; and





FIGS. 7-11

are simplified diagrams illustrating a method of forming a silicon-on-insulator substrate according to the present invention.











DESCRIPTION OF SPECIFIC EMBODIMENTS




The present invention provides a technique for removing a high-quality thin film of material from one substrate, and permanently bonding it to another substrate. The thin film of material forms a hybrid substrate with the second substrate and can substitute for an epitaxial layer on a conventional wafer. The invention will be better understood by reference to the FIGS. and the descriptions below. The description begins with explanations of thin film removal processes before discussing the wafer bonding processes and resultant structures.




1. Controlled Cleaving Techniques




In a controlled cleaving process, a cleave is initiated by subjecting the material with sufficient energy to fracture the material in one region, causing a cleave front, without uncontrolled shattering or cracking. The cleave front formation energy (E


c


) must often be made lower than the bulk material fracture energy (E


mat


) at each region to avoid shattering or cracking the material. The directional energy impulse vector in diamond cutting or the scribe line in glass cutting are, for example, the means in which the cleave energy is reduced to allow the controlled creation and propagation of a cleave front. The cleave front is in itself a higher stress region and once created, its propagation requires a lower energy to further cleave the material from this initial region of fracture. The energy required to propagate the cleave front is called the cleave front propagation energy (E


p


). The relationship can be expressed as:








E




c


=


E




p


+[cleave front stress energy]






A controlled cleaving process is realized by reducing E


p


along a favored direction(s) above all others and limiting the available energy to be below the E


p


of other undesired directions. In any cleave process, a better cleave surface finish occurs when the cleave process occurs through only one expanding cleave front, although multiple cleave fronts do work.




This technique uses a relatively low temperature during the controlled cleaving process of the thin film to reduce temperature excursions of the separated film, donor substrate, or multi-material films according to other embodiments. This lower temperature approach allows for more material and process latitude such as, for example, cleaving and bonding of materials having substantially different thermal expansion coefficients. The energy or stress in the substrate is limited to a value below a cleave initiation energy, which generally removes a possibility of creating random cleave initiation sites or fronts. This reduces cleave damage (e.g., pits, crystalline defects, breakage, cracks, steps, voids, excessive roughness) often caused in preexisting techniques. Moreover, a controlled-cleavage method reduces damage caused by higher than necessary stress or pressure effects and nucleation sites caused by the energetic particles as compared to other techniques.





FIG. 1

is a simplified cross-sectional view diagram of a substrate


10


according to the present invention. As merely an example, substrate


10


is a is a single-crystal silicon wafer which includes a material region


12


to be removed, which is a thin relatively uniform film derived from the substrate material. The silicon wafer


10


includes a top surface


14


, a bottom surface


16


, and a thickness


18


. Substrate


10


also has a first side (side


1


) and a second side (side


2


) (which are also referenced below in the Figs.). Material region


12


also includes a thickness


20


, within the thickness


18


of the silicon wafer.




Hydrogen ions are implanted


22


through the top surface


14


of the silicon wafer to a selected depth


24


, which defines the thickness


20


of the material region


12


, termed the thin film of material. The ions can be implanted by a variety of techniques, including beam line ion implantation, plasma immersion ion implantation (“PIII”), or ion shower. Beam line ion implantation can be performed with equipment manufactured from companies such as Applied Materials, Eaton Corporation, Varian, and others. Examples of plasma immersion implantation techniques are described in “Recent Applications of Plasma Immersion Ion Implantation,” Paul K. Chu, Chung Chan, and Nathan W. Cheung, SEMICONDUCTOR INTERNATIONAL, pp. 165-172, June 1996, and “Plasma Immersion Ion Implantation—A Fledgling Technique for Semiconductor Processing,”, P. K. Chu, S. Qin, C. Chan, N. W. Cheung, and L. A. Larson, MATERIALS SCIENCE AND ENGINEERING REPORTS: A REVIEW JOURNAL, pp. 207-280, Volume R17, Nos. 6-7, (Nov. 30, 1996), which are both hereby incorporated by reference for all purposes.




Hydrogen ions are desirable because they easily travel through the substrate material to the selected depth without substantially damaging the material region that the particles traverse through. The particles can also be derived from compounds such as gases, e.g., hydrogen gas, water vapor, methane, and hydrogen compounds, and other light atomic mass particles. Alternatively, other ions or combinations of ions may be used, depending on the material of the donor substrate, the thickness of the film to be removed, and the acceptable level of damage remaining in the thin film after processing.




Implantation dose ranges from about 10


15


to about 10


18


atoms/cm


2


, and preferably the dose is greater than about 10


16


atoms/cm


2


. Implantation energy ranges from about 1 KeV to about 1 MeV , and is generally about 50 KeV. Implantation temperature ranges from about −200 to about 600° C., and is preferably less than about 400° C. to minimize escape of the implanted particles (e.g. via the diffusion mechanism). The hydrogen ions can be selectively introduced into the silicon wafer to the selected depth at an accuracy of about +/−0.03 to +/−0.05 microns.




Effectively, the implanted particles add stress or reduce fracture energy along a plane parallel to the top surface of the substrate at the selected depth. The energies depend, in part, upon the implantation species and conditions. These particles reduce a fracture energy level of the substrate at the selected depth. This allows for a controlled cleave along the implanted plane at the selected depth.





FIG. 2

is a simplified energy diagram


200


along a cross-section of the implanted substrate


10


according to the present invention. The diagram is merely an illustration and should not limit the scope of the claims herein. The simplified diagram includes a vertical axis


201


that represents an energy level (E) (or additional energy) to cause a cleave in the substrate. A horizontal axis


203


represents a depth or distance from the bottom of the wafer to the top of the wafer. After implanting particles into the wafer, the substrate has an average cleave energy represented as E


205


, which is the amount of energy needed to cleave the wafer along various cross-sectional regions along the wafer depth. The cleave energy (E


c


) is equal to the bulk material fracture energy (E


mat


) in non-implanted regions. At the selected depth


20


, energy (E


cz


)


207


is lower since the implanted particles essentially break or weaken bonds in the crystalline structure (or increase stress caused by a presence of particles also contributing to lower energy (E


cz


)


207


of the substrate) to lower the amount of energy needed to cleave the substrate at the selected depth. This takes advantage of the lower energy (i.e. increased stress) at the selected depth to cleave the thin film in a controlled manner. If necessary, the cleave energy can further be reduced by subjecting the wafer to an intermediate thermal step below 500° C.





FIG. 3

is a simplified cross-sectional view of an implanted substrate


10


using selective positioning of cleave energy according to the present invention. This diagram is merely an illustration, and should not limit the scope of the claims herein. The implanted wafer undergoes a step of selective energy placement or positioning or targeting which provides a controlled cleaving action of the material region


12


at the selected depth. In this instance, the impulse is localized heating provided by a laser, although other heat sources, such as a heat lamp, or cold sources can be utilized. In another embodiment, a mechanical impulse is provided by twisting the target substrate with respect to the donor substrate, which generates maximum stress at the perimeter of the assembly, and minimum stress at the center. Of course, the type of source used depends upon the application.




Before locally heating the assembly, the stress in the implanted region was increased toward the energy level necessary to initiate the cleaving action without initiating the cleaving action. The global energy state of the substrate was raised by heating one side of the substrate to an intermediate temperature of about 350° C. with a heat lamp, or the substrate can be cooled, or differentially heated or cooled, that is a thermal gradient may be established across the assembly.




The removed material region provides a thin film of silicon material for processing. The silicon material possesses limited surface roughness and desired planarity characteristics for use in a silicon-on-silicon substrate. In certain embodiments, the surface roughness of the detached film has features that are less than about 60 nm, or less than about 40 nm, or less than about 20 nm. Accordingly, the present invention provides thin silicon films which can be smoother and more uniform than other techniques.




2. Another Cleaving Technique





FIGS. 4-6

are simplified cross sections of a thin film of material being separated from a wafer according to a blister-separation method, such as a process known as “Smart Cut.” An example of an implantation blister-separation method is described in U.S. Pat. No. 5,374,564, entitled Process For The Production Of Thin Semiconductor Material Films, by Michel Bruel, issued Dec. 20, 1994.





FIG. 4

shows a monocrystalline donor wafer


40


with a blister layer


41


. The blister layer was formed by implanting hydrogen into the donor wafer, which is oriented such that a crystalline plane, or cleavage plane, is approximately parallel to the blister layer. For example, a dose of about 10


16


cm


−2


hydrogen ions implanted into a {100} silicon wafer at 150 KeV formed a blister layer approximately 1.2 μm below the top surface


42


of the donor wafer


40


. It is believed that the implanted hydrogen ions capture electrons to form hydrogen atoms, which in turn form diatomic hydrogen gas. The hydrogen gas starts to form a layer of microbubbles in the blister layer, which is parallel to a cleaving plane of the donor wafer. When the wafer is heated, gas pressure builds within the blister layer, and a thin layer


45


of the donor wafer will split off along the cleavage plane.




While gases other than hydrogen may be used, such as helium, neon, krypton, and xenon, hydrogen is advantageous. The braking process of hydrogen ions in silicon is predominantly an electronic, rather than nuclear, phenomena. This allows for a relatively high dosage to be implanted with relatively little damage to the silicon lattice, as compared to implanting similar doses of heavier ions. The electronic braking also provides a smaller range of distribution of implanted ions than would typically be obtained when implanting a heavier ion. This makes it possible to obtain suitable blister formation at a moderate implanted dose, and to separate a layer of silicon with a relatively smooth surface.




The thickness of the thin layer may be determined by appropriately choosing the implant energy. The expected thickness in {100} silicon has been calculated using the public-domain “TRIM” modeling software developed by J. Zeigler, as shown in Table 1.



















TABLE 1











ENERGY (KeV)




10




50




100




150




200




500




1000






Film Thickness (μm)




0.14




0.5




0.88




1.27




1.72




5.59




15.67















FIG. 5

shows a target wafer


46


bonded to the donor wafer


40


. The target wafer provides support to the thin film


45


of silicon that will be blistered off of the donor wafer. The target wafer is a silicon wafer. The donor wafer may be bonded to the target wafer by a variety of methods, as described above. As above, it is desirable that the bonding method used not induce separation of the thin film unless that separation is intended. After bonding, heat treating the wafer assembly causes pressure to build up in the hydrogen gas bubbles that have formed in the donor substrate, to separate the top layer of silicon (about 1-15 microns thick) from the donor wafer. The bonding, heat treating, and annealing can be performed in a continuous thermal process, if desired.





FIG. 6

shows the thin film


45


of silicon attached to the target wafer


46


after separating the thin film from the donor wafer.




3. Silicon-On-Silicon Process




A process for fabricating a silicon-on-silicon substrate according to the present invention may be briefly outlined as follows:




(1) Provide a donor silicon wafer with a highly polished surface;




(2) Introduce particles into the silicon wafer through the highly polished surface to a selected depth to define a thickness of silicon film;




(3) Provide a target substrate material with a highly polished surface;




(4) Prepare the surface of the donor wafer and/or the surface of the target wafer for beta bonding the donor wafer to the target wafer (optional);




(5) Beta bond the donor silicon wafer to the target substrate material by joining the two highly polished surfaces;




(6) Separate a thin film of material from the donor substrate, the thin film of material adhering to the target substrate;




(7) Anneal the hybrid substrate of the thin film and the target substrate to complete bonding of the two layers together;




(8) Polish a surface of the thickness of silicon film (optional).




This sequence of steps is merely an example and should not limit the scope of the claims defined herein. Further details with regard to the above sequence of steps are described in below in references to the FIGS.





FIGS. 7-11

are simplified cross-sectional view diagrams of substrates undergoing a fabrication process for a silicon-on-silicon wafer according to the present invention. The process begins by providing a semiconductor substrate similar to the silicon wafer


2100


, as shown by FIG.


7


. Substrate or donor includes a material region


2101


to be removed, which is a thin relatively uniform film derived from the substrate material. The silicon wafer includes a top surface


2103


, a bottom surface


2105


, and a thickness


2107


. Material region also includes a thickness (z


0


), within the thickness


2107


of the silicon wafer above a layer


2111


of hydrogen ions or microbubbles, depending on the process used.




Hydrogen ions


2109


are implanted through the polished top surface of the silicon wafer to a selected depth, which defines the thickness of the material region, termed the thin film of material. As shown, the hydrogen ions (or microbubbles, depending on the process) have a desired concentration


2111


at the selected depth (z


0


). A variety of techniques can be used to implant the ions into the silicon wafer. These techniques include ion implantation using, for example, beam line ion implantation equipment manufactured from companies such as Applied Materials, Eaton Corporation, Varian, and others. Alternatively, implantation occurs using a plasma immersion ion implantation (“PIII”) technique. Of course, techniques used depend upon the application.




The process uses a step of preparing the implanted donor silicon wafer to bond to a workpiece, or target, silicon wafer, as illustrated in FIG.


8


. The silicon wafers are first “beta bonded” using a low temperature thermal step. Beta bonding is a relatively weak bonding process that joins the donor substrate to the target substrate. It is believed that beta bonding arises from electrostatic, or van der Waals, forces. Beta bonding produces a joint between the donor substrate and the target substrate for the target substrate to act as a mechanical support for the thin film when it is subsequently separated from the donor wafer. Beta bonding is generally not robust enough to join the thin film to the target wafer during subsequent wafer processing, such as lapping, polishing, or dicing operations, but is sufficient to hold the thin film to the target wafer until the assembly can be annealed and securely bonded.




Prior to beta bonding, the surfaces of the wafers are stripped of native or residual oxide and thoroughly cleaned, such as with an RCA-I and RCA-II cleaning sequence. An example of a solution used to clean the wafer is a mixture of H


2


O


2


—H


2


SO


4


. A dryer dries the wafer surfaces to remove any residual liquids or particles from the wafer surfaces. In an alternative process, the clean silicon surfaces of the wafers are dipped in hydrofluoric acid.




The cleaned and/or activated surfaces are then pressed together under moderate pressure. Using a low temperature beta bonding process generally ensures that the implanted particles do not initiate a fracture, or not diffuse or outgas. In one aspect, the low temperature bonding process occurs by a self-bonding process.




Alternatively, a self-bonding process occurs by activating one or both of the wafer surfaces to be bonded by plasma cleaning. In particular, plasma cleaning activates the wafer surface using a plasma derived from gases such as argon, ammonia, neon, water vapor, and oxygen. It is believed that the plasma cleaning step activates the surface of the wafer by creating dangling silicon bonds. The activated target wafer surface


2203


is placed against a face of the donor wafer surface


2103


, which will create a layer-to-layer interface. The wafers are in a sandwiched structure having exposed wafer faces, and the target wafer still has a desired concentration of particles


2111


intact. A selected amount of pressure is placed on each exposed face of the wafers to self-bond one wafer to the other.




After beta bonding the wafers into a substrate assembly


2300


, as shown in

FIG. 9

, the target wafer


46


and the donor wafer


2100


are joined at a layer-to-layer interface


2305


. The particles or microbubbles still form a separation region


2111


in the donor wafer. After beta bonding, the substrate assembly


2300


is processed to separate the thin film


2101


from the donor wafer


2100


.





FIG. 10

shows a final bonding, or annealing, step occurs between the target wafer and thin film of material to form a hybrid wafer


2410


. These embodiments often require high temperatures (e.g., above 700° C.). The final bonding step creates a strong bond between the thin film and the target substrate. It is believed that covalent bonds form between the two layers of silicon when the assembly is subjected to a sufficiently high temperature for a sufficient period of time, for example at 1,000° C. for approximately 1 hour. Lower temperatures generally require longer periods of time for the same degree of bonding to take place. During the annealing process, a thin film of thermal oxide


2406


may grow on the thin film


2101


. The final bonding process provides an electrical contact between the thin film and the target wafer, as well as a robust mechanical bond that can withstand subsequent wafer processing.




Alternatively, the two silicon surfaces can be bonded by applying voltage between the two layers to establish a current flow through the hybrid wafer. The electric current heats the wafers to induce a bonding between the wafers. This technique limits the amount of crystal defects introduced into the silicon wafers during the bonding process, since substantially no mechanical force is needed to initiate the bonding action between the wafers. Damage may also be limited because the localized heating at the layer-layer interface is greater, due to increased series resistance in this region, than in the bulk of either the target substrate or the thin film.




After bonding the wafers, silicon-on-silicon has a target substrate with an overlying film of silicon material, as also illustrated in FIG.


10


. The detached surface of the film of silicon material


2404


is often rough and may need finishing for some applications. Finishing occurs using a combination of grinding and/or polishing techniques. In some embodiments, such as when the thin film has been separated using a blister-separation method, the detached surface may undergo a step of grinding, or lapping, before the polishing step.




If the thin film was separated using a controlled cleavage process, the relative smooth and fracture-free surface allows chemical mechanical polishing or planarization (“CMP”) techniques without a prior lapping step, as illustrated by FIG.


11


. In CMP, a slurry mixture is applied directly to a polishing surface


2501


which is attached to a rotating platen


2503


. This slurry mixture can be transferred to the polishing surface by way of an orifice, which is coupled to a slurry source. The slurry is often a solution containing a mild abrasive and an oxidizer, e.g., H


2


O


2


, KIO


3


, or ferric nitrate. The abrasive is often very fine borosilicate glass, titanium dioxide, titanium nitride, aluminum oxide, aluminum trioxide, iron nitrate, cerium oxide, silicon dioxide (colloidal silica), silicon nitride, silicon carbide, graphite, diamond, and any mixtures thereof. This abrasive is mixed in a solution of deionized water and oxidizer or the like.




While the above is a full description of the specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present invention which is defined by the appended claims.



Claims
  • 1. A hybrid silicon wafer comprising:a single-crystal silicon donor wafer with an implanted layer of particles at a selected depth from a substrate-to substrate interface; and a silicon target wafer bonded to the donor wafer at the substrate-to-substrate interface by a bonding process, the bonding being suitable to provide electrical coupling between at least a portion of the donor wafer and the silicon target wafer, wherein the silicon target wafer has either a polycrystalline or amorphous structure; wherein one or both of the wafers have (100) crystal orientation.
  • 2. The hybrid silicon wafer of claim 1 wherein the particles at a selected depth are hydrogen ions.
  • 3. A hybrid silicon wafer comprising:a single-crystal silicon donor wafer with a layer of microbubbles at a selected depth from a substrate-to-substrate interface; and a silicon target wafer bonded to the donor wafer at the substrate-to-substrate interface, the bonding being suitable to provide electrical coupling between at least a portion of the donor wafer and the silicon target wafer, wherein the silicon target wafer has either a polycrystalline or amorphous structure; wherein the single-crystal silicon donor wafer has (100) crystal orientation.
  • 4. The hybrid silicon wafer of claim 3 wherein the layer of microbubbles are derived from implanting hydrogen ions at the selected depth.
  • 5. A hybrid silicon wafer, comprising:a thin film of silicon material having (100) structure being bonded to and electrically coupled to a silicon target wafer, wherein the thin film of silicon material has been separated from a donor wafer that had been implanted with hydrogen ions, wherein the thin film of silicon material has been beta bonded to the target wafer.
  • 6. The hybrid silicon wafer 5, wherein the beta bonding involves performing the bonding at a first temperature to bond the silicon material and the target wafer, so that the target wafer is bonded to the silicon material with sufficient strength to provide a mechanical support but not robust enough to bond the target wafer to the silicon material for a subsequent polishing step.
  • 7. The hybrid silicon wafer of claim 5, wherein a surface of the silicon material is cleaned to remove an oxide layer thereon.
  • 8. The hybrid silicon wafer of claim 7, wherein the surface of the silicon materials is cleaned by a plasma cleaning step.
  • 9. The hybrid silicon wafer of claim 8, wherein the plasma cleaning step involves using a plasma derived from a gas selected from the group consisting of: argon, neon, oxygen, and water vapor.
  • 10. The hybrid silicon wafer of claim 8, wherein the silicon material and the target wafer are annealed at a second temperature that is higher than the first temperature to securely bond the silicon material to the target wafer.
  • 11. The hybrid silicon wafer of claim 10, wherein the second temperature is about 1,000° C.
  • 12. A hybrid silicon wafer, comprising:a thin film of silicon material having (100) structure, the thin film of silicon material being bonded to and electrically coupled to a silicon target wafer, wherein the thin film of silicon material has been separated from a donor wafer that had been implanted with hydrogen ions, wherein the thin film of silicon material has been bonded to the target wafer at a first temperature and then at a second temperature, the second temperature being higher than the first temperature.
  • 13. The hybrid silicon wafer of claim 12 wherein the thin film is less tan about 15 microns thick.
  • 14. The hybrid silicon wafer of claim 13 wherein the bonding bonds the target wafer to the donor wafer at a temperature less than about 400° C.
  • 15. The hybrid silicon wafer of claim 13 wherein the implanted layer of particles consists of hydrogen ions.
  • 16. The hybrid silicon wafer of claim 12 wherein the thin film is beta bonded to the target wafer.
  • 17. The hybrid silicon wafer of claim 12 wherein the thin film is securely bonded to the target wafer.
  • 18. The hybrid silicon wafer of claim 12 further comprising electronic circuit devices disposed at least partially within the thin film.
CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of Ser. No. 09/025,966 filed Feb. 19, 1998 now U.S. Pat. No. 6,048,411, which claims priority from the provisional patent application entitled “A CONTROLLED CLEAVAGE PROCESS AND RESULTING DEVICE,” filed May 12, 1997 and assigned Application No. 60/046,276, the disclosures of which are hereby incorporated in their entirety for all purposes. This application is being filed on the same date as related application Ser. No. 09/028,870 entitled “A SILICON-ON-SILICON WAFER BONDING PROCESS USING A UNIFORM THIN FILM,” and application Ser. No. 09/025,967 now U.S. Pat. No. 6,159,824 entitled, “A SILICON-ON-SILICON WAFER BONDING PROCESS USING A THIN FILM BLISTER SEPARATION METHOD”.

US Referenced Citations (178)
Number Name Date Kind
2614055 Senarelens Oct 1952 A
3117022 Bronson et al. Jan 1964 A
3225820 Riordan Dec 1965 A
3390033 Brown Jun 1968 A
3551213 Boyle Dec 1970 A
3770499 Crowe et al. Nov 1973 A
3786359 King Jan 1974 A
3806380 Kitada et al. Apr 1974 A
3832219 Nelson et al. Aug 1974 A
3900636 Curry et al. Aug 1975 A
3901423 Hillberry et al. Aug 1975 A
3915757 Engel Oct 1975 A
3946334 Yonezu Mar 1976 A
3957107 Altoz et al. May 1976 A
3993909 Drews et al. Nov 1976 A
4006340 Gorinas Feb 1977 A
4039416 White Aug 1977 A
4053335 Hu Oct 1977 A
4074139 Pankove Feb 1978 A
4107350 Berg et al. Aug 1978 A
4108751 King Aug 1978 A
4116751 Zaromb Sep 1978 A
4121334 Wallis Oct 1978 A
4170662 Weiss et al. Oct 1979 A
4216906 Olsen et al. Aug 1980 A
4237601 Woolhouse et al. Dec 1980 A
4244348 Wilkes Jan 1981 A
4252837 Auton Feb 1981 A
4255208 Deutscher et al. Mar 1981 A
4274004 Kanai Jun 1981 A
4342631 White et al. Aug 1982 A
4346123 Kaufmann Aug 1982 A
4361600 Brown Nov 1982 A
4368083 Bruel et al. Jan 1983 A
4375125 Byatt Mar 1983 A
4412868 Brown et al. Nov 1983 A
4452644 Bruel et al. Jun 1984 A
4468309 White Aug 1984 A
4471003 Cann Sep 1984 A
4486247 Ecer et al. Dec 1984 A
4490190 Speri Dec 1984 A
4500563 Ellenberger et al. Feb 1985 A
4508056 Bruel et al. Apr 1985 A
4536657 Bruel Aug 1985 A
4539050 Kramler et al. Sep 1985 A
4566403 Fournier Jan 1986 A
4567505 Pease et al. Jan 1986 A
4568563 Jackson et al. Feb 1986 A
4585945 Bruel et al. Apr 1986 A
4645546 Matsushita Feb 1987 A
4684535 Heinecke et al. Aug 1987 A
4704302 Bruel et al. Nov 1987 A
4706377 Shuskus Nov 1987 A
4717683 Parrillo et al. Jan 1988 A
4727047 Bozler et al. Feb 1988 A
4764394 Conrad Aug 1988 A
4766086 Ohshima et al. Aug 1988 A
4837172 Mizuno et al. Jun 1989 A
4846928 Dolins et al. Jul 1989 A
4847792 Barna et al. Jul 1989 A
4853250 Boulos et al. Aug 1989 A
4883561 Gmitter et al. Nov 1989 A
4887005 Rough et al. Dec 1989 A
4891329 Reisman et al. Jan 1990 A
4894709 Phillips et al. Jan 1990 A
4931405 Kamijo et al. Jun 1990 A
4948458 Ogle Aug 1990 A
4952273 Popov Aug 1990 A
4956693 Sawahata et al. Sep 1990 A
4960073 Suzuki et al. Oct 1990 A
4982090 Wittmaack Jan 1991 A
4983251 Haisma et al. Jan 1991 A
4996077 Moslehi et al. Feb 1991 A
5015353 Hubler et al. May 1991 A
5034343 Rouse et al. Jul 1991 A
5070040 Pankove Dec 1991 A
5082793 Li Jan 1992 A
5102821 Moslehi Apr 1992 A
5110748 Sarma May 1992 A
5133826 Dandl Jul 1992 A
5162241 Mori et al. Nov 1992 A
5196355 Wittkower Mar 1993 A
5198371 Li Mar 1993 A
5202095 Houchin et al. Apr 1993 A
5203960 Dandl Apr 1993 A
5206749 Zavracky et al. Apr 1993 A
5213451 Frank May 1993 A
5234529 Johnson Aug 1993 A
5234535 Beyer et al. Aug 1993 A
5242861 Inaba Sep 1993 A
5250328 Otto Oct 1993 A
5252178 Moslehi Oct 1993 A
5256562 Vu et al. Oct 1993 A
5258320 Zavracky et al. Nov 1993 A
5258325 Spitzer et al. Nov 1993 A
5268880 Jolly et al. Dec 1993 A
5273610 Thomas, III et al. Dec 1993 A
5277748 Sakaguchi et al. Jan 1994 A
5303574 Matossian et al. Apr 1994 A
5304509 Sopori Apr 1994 A
5308776 Gotou May 1994 A
5317236 Zavracky et al. May 1994 A
5342472 Imahashi et al. Aug 1994 A
5344524 Sharma et al. Sep 1994 A
5354381 Sheng Oct 1994 A
5362671 Zavracky et al. Nov 1994 A
5363603 Miller et al. Nov 1994 A
5368710 Chen et al. Nov 1994 A
5370765 Dandl Dec 1994 A
5374564 Bruel Dec 1994 A
5376560 Aronowitz et al. Dec 1994 A
5377031 Vu et al. Dec 1994 A
5404079 Ohkuni et al. Apr 1995 A
5405480 Benzing et al. Apr 1995 A
5411592 Ovshinsky et al. May 1995 A
5413679 Godbey May 1995 A
5435880 Minato et al. Jul 1995 A
5438241 Zavracky et al. Aug 1995 A
5443661 Oguro et al. Aug 1995 A
5444557 Spitzer et al. Aug 1995 A
5459016 Debe et al. Oct 1995 A
5475514 Salerno et al. Dec 1995 A
5476691 Komvopoulos et al. Dec 1995 A
5480842 Clifton et al. Jan 1996 A
5487785 Horiike et al. Jan 1996 A
5494835 Bruel Feb 1996 A
5504328 Bonser Apr 1996 A
5528397 Zavracky et al. Jun 1996 A
5539245 Imura et al. Jul 1996 A
5558718 Leung Sep 1996 A
5559043 Bruel Sep 1996 A
5569620 Linn et al. Oct 1996 A
5581385 Spitzer et al. Dec 1996 A
5585304 Hayashi et al. Dec 1996 A
5611855 Wijaranakula Mar 1997 A
5643834 Harada et al. Jul 1997 A
5653811 Chan Aug 1997 A
5705421 Matsushita et al. Jan 1998 A
5710057 Kenney Jan 1998 A
5714395 Bruel Feb 1998 A
5744852 Linn et al. Apr 1998 A
5753560 Hong et al. May 1998 A
5755914 Yonehara May 1998 A
5763319 Ling et al. Jun 1998 A
5783022 Cha et al. Jul 1998 A
5804086 Bruel Sep 1998 A
5821158 Shishiguchi Oct 1998 A
5824595 Igel et al. Oct 1998 A
5827751 Nuyen Oct 1998 A
5840590 Myers, Jr. et al. Nov 1998 A
5854123 Sato et al. Dec 1998 A
5869387 Sato et al. Feb 1999 A
5877070 Goesele et al. Mar 1999 A
5882987 Srikrishnan Mar 1999 A
5909627 Egloff Jun 1999 A
5920764 Hanson et al. Jul 1999 A
5953622 Lee et al. Sep 1999 A
5966620 Sakaguchi et al. Oct 1999 A
5985742 Henley et al. Nov 1999 A
5993677 Biasse et al. Nov 1999 A
5994207 Henley et al. Nov 1999 A
6010579 Henley et al. Jan 2000 A
6013563 Henley et al. Jan 2000 A
6013567 Henley et al. Jan 2000 A
6020252 Aspar et al. Feb 2000 A
6033974 Henley et al. Mar 2000 A
6048411 Henley et al. Apr 2000 A
6077383 Laporte Jun 2000 A
6083324 Henley et al. Jul 2000 A
6120597 Levy et al. Sep 2000 A
6150239 Goesele et al. Nov 2000 A
6159824 Henley et al. Dec 2000 A
6171965 Kang et al. Jan 2001 B1
6184111 Henley et al. Feb 2001 B1
6190998 Bruel et al. Feb 2001 B1
6191007 Matsui et al. Feb 2001 B1
6214701 Matsushita et al. Apr 2001 B1
6225192 Aspar et al. May 2001 B1
Foreign Referenced Citations (131)
Number Date Country
834363 Mar 1952 DE
0084287 Jul 1983 EP
084 287 Jul 1983 EP
099 778 Feb 1984 EP
0099778 Feb 1984 EP
155 875 Feb 1984 EP
0155875 Feb 1984 EP
112 238 Jun 1984 EP
0112238 Jun 1984 EP
0164281 Dec 1985 EP
164 281 Dec 1985 EP
112 230 Apr 1987 EP
0112230 Apr 1987 EP
181 249 Jun 1989 EP
0181249 Jun 1989 EP
355 913 Feb 1990 EP
379 828 Aug 1990 EP
459 177 Dec 1991 EP
504 714 Sep 1992 EP
0504714 Sep 1992 EP
0533551 Mar 1993 EP
533 551 Mar 1993 EP
0355913 Dec 1993 EP
665 588 Feb 1995 EP
0665588 Feb 1995 EP
660 140 Jun 1995 EP
0660140 Jun 1995 EP
665 587 Aug 1995 EP
0665587 Aug 1995 EP
0379828 Sep 1995 EP
0459177 Dec 1995 EP
0703609 Mar 1996 EP
703 609 Mar 1996 EP
763 849 Mar 1997 EP
0763849 Mar 1997 EP
807 970 Nov 1997 EP
0867917 Mar 1998 EP
0867921 Mar 1998 EP
961 312 Dec 1999 EP
1558881 Jan 1969 FR
2261802 Feb 1974 FR
2261802 Feb 1974 FR
2235474 Apr 1974 FR
2235474 Apr 1974 FR
2298880 Jan 1975 FR
2298880 Jan 1975 FR
2266304 Apr 1975 FR
2266304 Apr 1975 FR
2519437 Jan 1982 FR
2519437 Jan 1982 FR
2529383 Jun 1982 FR
2529383 Jun 1982 FR
2537768 Aug 1982 FR
2537777 Dec 1982 FR
2715502 Jan 1984 FR
2560426 Feb 1984 FR
2560426 Feb 1984 FR
2563377 Apr 1984 FR
2563377 Apr 1984 FR
2537777 Dec 1984 FR
2575601 Dec 1984 FR
2575601 Dec 1984 FR
2681472 Sep 1991 FR
2681472 Sep 1991 FR
2537768 Aug 1992 FR
2714524 Dec 1993 FR
2714524 Dec 1993 FR
2715501 Jan 1994 FR
2715501 Jan 1994 FR
2715502 Jan 1994 FR
2715503 Jan 1994 FR
2715503 Jan 1994 FR
2720189 May 1994 FR
2720189 May 1994 FR
2725074 Sep 1994 FR
2725074 Sep 1994 FR
2 211 991 Jul 1989 GB
2221991 Jul 1989 GB
2 231 197 Nov 1990 GB
60-235434 Nov 1958 JP
60-235434 Nov 1958 JP
53-104156 Sep 1978 JP
53-104156 Sep 1978 JP
58-144475 Aug 1983 JP
58-144475 Aug 1983 JP
60-83591 Oct 1983 JP
60-083591 Oct 1983 JP
59-19394 Jan 1984 JP
59-019394 Jan 1984 JP
59-46750 Mar 1984 JP
59-54217 Mar 1984 JP
59-046750 Mar 1984 JP
59-054217 Mar 1984 JP
59-114744 Jul 1984 JP
59-114744 Jul 1984 JP
59-139539 Aug 1984 JP
59-139539 Aug 1984 JP
59-193904 Nov 1984 JP
60-207237 Oct 1985 JP
60-207237 Oct 1985 JP
4-76503 Jul 1990 JP
4-076503 Jul 1990 JP
3-109731 May 1991 JP
3-132055 Jun 1991 JP
3-265156 Nov 1991 JP
2901031 Jan 1992 JP
2910001 Jan 1992 JP
4-246594 Sep 1992 JP
4-246594 Sep 1992 JP
404298023 Oct 1992 JP
5-211128 Aug 1993 JP
5-211128 Aug 1993 JP
7-215800 Aug 1995 JP
7-215800 Aug 1995 JP
7-254690 Oct 1995 JP
7-254690 Oct 1995 JP
7-263291 Oct 1995 JP
7-263291 Oct 1995 JP
8-97389 Apr 1996 JP
8-097389 Apr 1996 JP
28-077800 Mar 1998 JP
10-200080 Jul 1998 JP
11-045840 Feb 1999 JP
2000-94317 Apr 2000 JP
WO 9510718 Apr 1995 WO
WO 9510718 Apr 1995 WO
WO 9520824 Aug 1995 WO
WO 9520824 Aug 1995 WO
WO 9531825 Nov 1995 WO
WO 9531825 Nov 1995 WO
WO 9935674 Jul 1999 WO
Non-Patent Literature Citations (37)
Entry
Alles, Michael et al., “Thin Film Silicon on Insulator: An Enabling Technology,” Semiconductor International, pp. 67-72 (1997). No Month.
Basta, Nicholas, “Ion-Beam Implantation,” High Technology, (1985).
Burggraff, Peter, “Advanced Plasma Source: What's Working?” Semiconductor International, pp. 56-59 (May 1994).
Carter, G. et al., “The Collection of IONS Implanted in Semiconductors Radiation Effects,” Abstract only, vol. 16 Nos. 1-2, pp. 107-114 (Sep. 1972).
Cassidy, Victor M., “Ion Implantation Process Toughens Metalworing Tools,” Modern Metals, pp. 65-67 (1984). No Month.
Cheung, N.W., “Plasma Immersion Ion Implantation for Semiconductor Processing,” Material Chemistry and Physics, 46(2-3): 132-139 (1996). No Month.
Choyke et al., “Mechanical Response of Single Crystal Si to Very High Fluence H+ Implantation,” Nuc. Instr. Meth., 209-210:407-412 (1983) No Month.
Choyke et al., “Implanted Hydrogen Effects at High Concentrations in Model Low Z Shielding Materials,” J. Nuc. Mtrls., 122-23:1585-86 (1984) No Month.
Choyke et al., “A Comparative Study of Near-Surface Effects Due to Very High Fluence H+ Implantation in Single Cyrstal FZ, CZ, and Web SI,” Mat. Res. Soc. Symp. Proc., 27:359-364 (1984) No Month.
Chu, P.K. et al. “Plasma Immersion Ion Implantation—A Fledgling Technique for Semiconductor Processing,” Materials Science and Engineering Reports: A Review Journal, R17(6-7): 207-280 (1996) No Month.
Chu, Paul K. et al., “Recent Applications of Plasma Immersion Ion Implantation,” Semiconductor International, pp. 165-172 (1996) No Month.
Chu, Paul K., “Synthesis of SOI Materials Using Plasma Immersion Ion Implantation,” 1997 Mat. Res. Soc. Symp. Proc., 438:333-343 (1997) No Month.
Corbett et al., “Embrittlement of Materials: Si(H) as a Model System,” J. Nuc. Mtrls., 169: 179-184 (1989) No Month.
Hulett, D.M. et al., “Ion Nitriding and Ion Implantation: A Comparison,” Metal Progress, pp. 18-21 (1985) No Month.
I.B.M. Technical Disclosure Bulletin, vol. 29: No. 3, p. 1416 (Aug. 1986).
Johnson et al., “Hydrogen-Induced Platelets in Silicon: Separation of Nucleation and Growth,” Mtrls. Sci. Forum. 83-87:33-38 (1992) No Month.
Lee, B.H. et al., “A Novel Pattern Transfer Process for Bonded SOI Giga-bit DRAMS,” 1996 IEEE Int'l. SOI Conference Proceedings, IEEE Electron Devices Society, (1996.) No Month.
Li, J., “Novel Semiconductor Substrate Formed by Hydrogen Ion Implantation into Silicon,” Appl. Phys. Lett., 55(21):2223-2224 (1989) No Month.
Lu, X. et al., “SOI Material Technology Using Plasma Immersion Ion Implantation,” Proceedings 1996 IEEE International SOI Conference (Oct. 1996).
Matsuda et al., “Large Diameter Ion Beam Implantation System,” Nuclear Instruments and Methods, B21:314-316 (1987) No Month.
Milnes et al., “Peeled Film Technology for solar Cells,” pp. 338-341 No Date.
Moreau, Wayne M., Semiconductor Lithography, Principles, Practices, and Materials, Plenum Press (1988) No Month.
Oshima et al., “Defects in Si irradiated with D-T neutrons, D and He ions,” J. Nuc. Mtrls., 179-181:947-950 (1991) No Month.
Patent Abstracts of Japan, vol. 7, No. 107 (E-174), (May 11, 1993) JP-58-030145 (Feb. 22, 1983).
Picraux, S. Thomas et al., “Ion Implantation of Surfaces,” Scientific American, 252(3):102-113 (1985) No Month.
Renier, M. et al., “A New Low-Energy Ion Implanter for Bombardment of Cylindrical Surfaces,” Vacuum, 35(12):577-578 (1985) No Month.
Sioshansi, Piran, “Ion Beam Modification of Materials for Industry,” Thin Solid Film, 118:61-71 (1984) No Month.
Wolf, Stanley Ph.D., Silicon Processing for the VLSI Era vol. 2, pp. 66-79, Lattice Press (1990) No Month.
U.S. Dept. of Energy, “The Fusion Connection: . . . ”, Plasma Coating, pp. 6-7 (1985) No Month.
Veldkamp, W.B. et al., Binary Optics, Scientific American, pp. 50-55 (May 1992).
Carter et al., “The Collection of Ions Implanted in Semiconductors II. Rnage distributions Derived from Collection and Sputter-Etch Curves,” Radiation Effects, 16:107-114 (1972) No Month.
Grovenor, C.R.M., Microelectronic Materials, pp. 73-75 (1989) No Month.
Mahajan et al., Principles of Growth and Processing of Semiconductors, WCB McGraw-Hill, chapter 6, pp. 262-269 No Date.
Smith, D.L., Thin-Film Deposition, McGraw-Hill, Inc., pp. 185-196, 278-293 No Date.
Sze, S.M., VLSI Technology, 2nd Edition, pp. 9-10, (1988) No Month.
Tong et al., “A ‘smarter-cut’ approach to low temperature silicon layer transfer,” Appl. Phys. Lett., 72(1):49-51 (1998) No Month.
Tong et al., Semiconductor Wafer Bonding: Science and Technology, John Wiley & Sons, Inc., pp. 152-171 No Date.
Provisional Applications (1)
Number Date Country
60/046276 May 1997 US
Continuations (1)
Number Date Country
Parent 09/025966 Feb 1998 US
Child 09/515253 US