Patent Application
20240387396
This disclosure relates generally to integrated circuit packages and, more particularly, to surface finishes for contacts and fiducial marks on integrated circuit package substrates and associated methods.
Integrated circuit (IC) chips and/or semiconductor dies are routinely connected to larger circuit boards such as motherboards and other types of printed circuit boards (PCBs) via a package substrate. Integrated circuit (IC) chips and/or dies have exhibited reductions in size and increases in interconnect densities as technology has advanced.
In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular.
As used herein, unless otherwise stated, the term “above” describes the relationship of two parts relative to Earth. A first part is above a second part, if the second part has at least one part between Earth and the first part. Likewise, as used herein, a first part is “below” a second part when the first part is closer to the Earth than the second part. As noted above, a first part can be above or below a second part with one or more of: other parts therebetween, without other parts therebetween, with the first and second parts touching, or without the first and second parts being in direct contact with one another.
Notwithstanding the foregoing, in the case of referencing a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during fabrication or manufacturing, “above” is not with reference to Earth, but instead is with reference to an underlying substrate on which relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein and unless otherwise stated or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is “above” a second component within the semiconductor die when the first component is farther away from a substrate (e.g., a semiconductor wafer) during fabrication/manufacturing than the second component on which the two components are fabricated or otherwise provided. Similarly, unless otherwise stated or implied from the context, a first component within an IC package (e.g., a semiconductor die) is “above” a second component within the IC package during fabrication when the first component is farther away from a printed circuit board (PCB) to which the IC package is to be mounted or attached. It is to be understood that semiconductor devices are often used in orientation different than their orientation during fabrication. Thus, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during use, the definition of “above” in the preceding paragraph (i.e., the term “above” describes the relationship of two parts relative to Earth) will likely govern based on the usage context.
As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween.
As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly within the context of the discussion (e.g., within a claim) in which the elements might, for example, otherwise share a same name.
As used herein, “approximately” and “about” modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections as will be understood by persons of ordinary skill in the art. For example, “approximately” and “about” may indicate such dimensions may be within a tolerance range of +/−10% unless otherwise specified in the below description.
As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.
As used herein, “programmable circuitry” is defined to include (i) one or more special purpose electrical circuits (e.g., an application specific circuit (ASIC)) structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform specific functions(s) and/or operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as Central Processor Units (CPUs) that may execute first instructions to perform one or more operations and/or functions, Field Programmable Gate Arrays (FPGAs) that may be programmed with second instructions to cause configuration and/or structuring of the FPGAs to instantiate one or more operations and/or functions corresponding to the first instructions, Graphics Processor Units (GPUs) that may execute first instructions to perform one or more operations and/or functions, Digital Signal Processors (DSPs) that may execute first instructions to perform one or more operations and/or functions, XPUs, Network Processing Units (NPUs) one or more microcontrollers that may execute first instructions to perform one or more operations and/or functions and/or integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and/or any combination(s) thereof), and orchestration technology (e.g., application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of programmable circuitry is/are suited and available to perform the computing task(s).
As used herein integrated circuit/circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), etc.
Integrated circuit packages typically include a package substrate that includes a core with a series of build-up layers on one or both sides of the core. The build-up layers include multiple layers of a conductive metal defining electrical routing or traces that are separated by layers of a dielectric material. Separate ones of the conductive layers are interconnected by metal vias extending through the intervening layer(s) of dielectric material. The outer surfaces (e.g., the top and bottom) of a package substrate typically include a plurality of openings within a solder resist layer that expose portions of the outermost layer of the conductive metal of the build-up layers. Many of the exposed portions of the conductive metal serve as interconnects (e.g., bumps, pads, lands, etc.) to enable the coupling of electrical components (e.g., semiconductor die(s), capacitor(s), etc.) to the package substrate and/or to enable the electrical coupling of the package substrate to a printed circuit board. Additionally, at least some of the exposed portions of the conductive metal serve as fiducial markers to facilitate the alignment of the electrical components when being attached to the package substrate.
Frequently, the conductive metal used within the build-up layers is copper. However, in many instances, the portions of the conductive metal (e.g., copper) at the outer surfaces of a package substrate (e.g., exposed by the openings in the solder resist layer) are treated or covered by a surface finish, which may serve as a diffusion barrier. A common surface finish for exposed copper pads or contacts includes nickel. In many instances, the surface finish for the copper also includes a layer of palladium and/or a layer of gold. Typically, a surface finish of nickel, palladium, and gold is achieved through electroless plating processes. Such processes result in the formation of hydrogen bubbles in the surface finish layers that result in voids that can undermine the mechanical and/or electrical properties of the materials. Accordingly, during the electroless plating processes, package substrates typically undergo a rock and shock operation in which the substrates are disturbed or stressed by abrupt acceleration changes (e.g., shocked) to dislodge and/or release the hydrogen bubbles, thereby reducing (e.g., avoiding) the formation of voids.
While the rock and shock operations typically involved for the electroless plating of a Ni/Pd/Au surface finish is suitable for package substrates having organic cores, such operations present problems for package substrates with glass cores. Glass cores are implemented in package substrates because glass cores provide both mechanical and electrical benefits over organic cores. Specifically, it is possible to achieve smaller pitches to achieve greater scaling and associated electrical benefits while at the same time providing increased structural support for a package. Despite these advantages, glass cores also present certain challenges. Among other things, glass is relatively brittle and so is liable to break. It is for this reason that the rock and shock operation associated with traditional surface finish plating processes are not suitable for package substrates with glass cores. Examples disclosed herein overcome this concern by providing a surface finish on copper pads that includes tin without a discrete layer at least one of nickel, palladium, or gold. That is, while there may be traces of one or more of nickel, palladium, or gold, in examples disclosed herein, the traces are insufficient to be demarcated as a discrete layer. In some examples, a tin-based surface finish include no layers and/or no traces of any of the nickel, palladium or gold. In some examples, the tin used for the surface finish is substantially pure tin. As used herein, substantially pure tin means at least 99 wt % tin. In some examples, the tin-based surface finish includes a tin alloy. Tin can be deposited onto copper through electroless plating processes, similar to nickel, palladium, and gold. However, unlike the electroless plating of nickel, palladium, and/or gold, the electroless plating of tin does not produce hydrogen bubbles and, therefore, does not require the implementation of a rock and shock operation. As a result, in accordance with teachings disclosed herein, a tin-based surface finish can be applied to copper pads on the surfaces of a package substrate that includes a glass core without concern of damage to the glass core. While examples disclosed herein are described with reference to package substrates having glass cores, teachings disclosed herein can also be used in connection with package substrates having organic cores.
In the illustrated example, each of the dies 106, 108 is electrically and mechanically coupled to the substrate 110 via corresponding arrays of interconnects 114. In
As shown in
As used herein, bridge bumps are bumps on the dies through which electrical signals pass between different ones of the dies within an IC package. More particularly, bridge bumps differ from core bumps in that bridge bumps electrically connect two or more different dies via an interconnect bridge (e.g., the interconnect bridge 128 of
In the illustrated example, the build-up regions 204 are provided on a first surface 206 of the glass core 202 and a second surface 208 of the glass core 202 opposite the first surface 206. The build-up regions 204 of the illustrated example are defined by an alternating pattern of insulation of dielectric layers 210 and patterned conductive (e.g., metal) layers 212. In some examples, the conductive layers 212 include copper. In this example, there are three dielectric layers 210 and three conductive layers 212 in the build-up regions 204 (not including the outermost layer of conductive material). However, in other examples, any other suitable number of dielectric and conductive layers 210, 212 may be employed. In some examples, the build-up region 204 on at least one side of the glass core 202 may be omitted such that the glass core defines an exterior surface of the package substrate 110. Although the glass core 202 of the example package substrate 110 is shown as a central core of the substrate 110, in some examples, the glass core 202 can be an interposer and/or any other layer of the package substrate 110. For example, the glass core 202 can be used in place of one or more of the dielectric layers 210 of the package substrate 110. In some examples, the package substrate 110 can include different material(s) including organic materials, silicon, and/or other conventional materials for fabricating package substrates.
The conductive layers 212 in the build-up regions 204 are patterned to define electrical routing or conductive traces that serve as signaling or transmission lines to transfer power and/or signals of information between two or more components (e.g., transistors, capacitors, resistors, backend layers, etc. and/or other circuitry) of an associated IC package (e.g., the IC package 100 of
In the illustrated example, the package substrate 110 includes a first plurality of connectors 218 (e.g., solder balls, bumps, contact pads, pins, etc.) on the inner surface 122 of the substrate 110 to electrically couple the package substrate 110 to one or more semiconductor die (e.g., one of the dies 106, 108 of
In this example, both the first plurality of connectors 218 and the second plurality of connectors 220 are positioned within openings distributed along respective first and second solder resist layers 222, 224 respectively defining the inner and outer surfaces 122, 124 of the substrate 110. In
In
Any suitable processes (presently known or subsequently developed) may be employed to fabricate the example package substrate 300 up to the point represented by
In some examples, the tin is deposited using an electroless plating process. More particularly, in some examples, an immersion tin plating process is used. Additionally or alternatively, in some examples, an autocatalytic tin plating process is used. An advantage of such tin-based electroless plating processes is that they can be completed without a rock and shock operation. As a result, there is less risk of mechanical damage to components in the package substrate 300 (e.g., a glass core). Furthermore, the tin-based surface finish disclosed herein does not require any additional process operations relative to the traditional electroless plating of nickel, palladium, and gold. Rather, it replaces the traditional electroless plating process with a new electroless plating process based on a different material.
After the deposition of a surface finish 404 of tin 402 (represented in
Specifically,
The example process begins at block 902 by providing a package substrate with openings in a solder resist layer on an outer surface of the substrate. In some examples, the process can apply to both surfaces (e.g., inner and outer surfaces) of a package substrate at the same time. Different ones of the openings in the solder resist layer may correspond to first level interconnects, capacitor pads, and/or fiducial markers. At block 904, the process involves depositing a surface finish of tin onto exposed portions of metal pads at the base of the openings in the solder resist layer. In some examples, the surface finish is deposited using an electroless plating process (e.g., immersion plating and/or autocatalytic plating). At block 906, the process involves depositing a dry film resist over the openings in the solder resist layer. At block 908, the process involves patterning the dry film resist to uncover the surface finish of tin in selective ones of the openings in the solder resist layer. In some examples, the selective ones of the openings correspond to first level interconnects. At block 910, the process involves depositing tin onto the exposed surface finish of tin. Unlike the deposition of the surface finish of tin at block 904, in some examples, the deposition of tin at block 910 is through an electrolytic plating process. At block 912, the process involves removing the dry film resist. As a result, the surface finish of tin in the openings that remained covered after the patterning of the dry film resist at block 908 will be exposed. At block 914, the process involves heating the tin during a reflow process. The reflow process melts the tin into a liquid state to be reshaped with a convex outer surface. Thereafter, the example process of
The example package substrates 110, 300 of
The IC device 1100 may include one or more device layers 1104 disposed on or above the die substrate 1102. The device layer 1104 may include features of one or more transistors 1140 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1102. The device layer 1104 may include, for example, one or more source and/or drain (S/D) regions 1120, a gate 1122 to control current flow between the S/D regions 1120, and one or more S/D contacts 1124 to route electrical signals to/from the S/D regions 1120. The transistors 1140 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1140 are not limited to the type and configuration depicted in
Each transistor 1140 may include a gate 1122 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some examples, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1140 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some examples, when viewed as a cross-section of the transistor 1140 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1102 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1102. In other examples, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1102 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1102. In other examples, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some examples, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some examples, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1120 may be formed within the die substrate 1102 adjacent to the gate 1122 of each transistor 1140. The S/D regions 1120 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1102 to form the S/D regions 1120. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1102 may follow the ion-implantation process. In the latter process, the die substrate 1102 may first be etched to form recesses at the locations of the S/D regions 1120. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1120. In some implementations, the S/D regions 1120 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some examples, the S/D regions 1120 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further examples, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1120.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1140) of the device layer 1104 through one or more interconnect layers disposed on the device layer 1104 (illustrated in
The interconnect structures 1128 may be arranged within the interconnect layers 1106-2010 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1128 depicted in
In some examples, the interconnect structures 1128 may include lines 1128a and/or vias 1128b filled with an electrically conductive material such as a metal. The lines 1128a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1102 upon which the device layer 1104 is formed. For example, the lines 1128a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 1106-2010 may include a dielectric material 1126 disposed between the interconnect structures 1128, as shown in
A first interconnect layer 1106 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1104. In some examples, the first interconnect layer 1106 may include lines 1128a and/or vias 1128b, as shown. The lines 1128a of the first interconnect layer 1106 may be coupled with contacts (e.g., the S/D contacts 1124) of the device layer 1104.
A second interconnect layer 1108 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1106. In some examples, the second interconnect layer 1108 may include vias 1128b to couple the lines 1128a of the second interconnect layer 1108 with the lines 1128a of the first interconnect layer 1106. Although the lines 1128a and the vias 1128b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1108) for the sake of clarity, the lines 1128a and the vias 1128b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some examples.
A third interconnect layer 1110 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1108 according to similar techniques and configurations described in connection with the second interconnect layer 1108 or the first interconnect layer 1106. In some examples, the interconnect layers that are “higher up” in the metallization stack 1119 in the IC device 1100 (i.e., further away from the device layer 1104) may be thicker.
The IC device 1100 may include a solder resist material 1134 (e.g., polyimide or similar material) and one or more conductive contacts 1136 formed on the interconnect layers 1106-2010. In
In some examples, the circuit board 1202 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1202. In other examples, the circuit board 1202 may be a non-PCB substrate. In some examples, the circuit board 1202 may be, for example, the circuit board 102 of
The IC device assembly 1200 illustrated in
The package-on-interposer structure 1236 may include an IC package 1220 coupled to an interposer 1204 by coupling components 1218. The coupling components 1218 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1216. Although a single IC package 1220 is shown in
In some examples, the interposer 1204 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some examples, the interposer 1204 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the interposer 1204 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1204 may include metal interconnects 1208 and vias 1210, including but not limited to through-silicon vias (TSVs) 1206. The interposer 1204 may further include embedded devices 1214, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1204. The package-on-interposer structure 1236 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1200 may include an IC package 1224 coupled to the first face 1240 of the circuit board 1202 by coupling components 1222. The coupling components 1222 may take the form of any of the examples discussed above with reference to the coupling components 1216, and the IC package 1224 may take the form of any of the examples discussed above with reference to the IC package 1220.
The IC device assembly 1200 illustrated in
Additionally, in various examples, the electrical device 1300 may not include one or more of the components illustrated in
The electrical device 1300 may include programmable circuitry 1302 (e.g., one or more processing devices). The programmable circuitry 1302 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1300 may include a memory 1304, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some examples, the memory 1304 may include memory that shares a die with the programmable circuitry 1302. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some examples, the electrical device 1300 may include a communication chip 1312 (e.g., one or more communication chips). For example, the communication chip 1312 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some examples they might not.
The communication chip 1312 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 808.11 family), IEEE 808.16 standards (e.g., IEEE 808.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 808.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 808.16 standards. The communication chip 1312 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1312 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1312 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 1G, 5G, and beyond. The communication chip 1312 may operate in accordance with other wireless protocols in other examples. The electrical device 1300 may include an antenna 1322 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some examples, the communication chip 1312 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1312 may include multiple communication chips. For instance, a first communication chip 1312 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1312 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first communication chip 1312 may be dedicated to wireless communications, and a second communication chip 1312 may be dedicated to wired communications.
The electrical device 1300 may include battery/power circuitry 1314. The battery/power circuitry 1314 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1300 to an energy source separate from the electrical device 1300 (e.g., AC line power).
The electrical device 1300 may include a display 1306 (or corresponding interface circuitry, as discussed above). The display 1306 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1300 may include an audio output device 1308 (or corresponding interface circuitry, as discussed above). The audio output device 1308 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1300 may include an audio input device 1324 (or corresponding interface circuitry, as discussed above). The audio input device 1324 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1300 may include GPS circuity 1318. The GPS circuity 1318 may be in communication with a satellite-based system and may receive a location of the electrical device 1300, as known in the art.
The electrical device 1300 may include any other output device 1310 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1300 may include any other input device 1320 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1320 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1300 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some examples, the electrical device 1300 may be any other electronic device that processes data.
“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities and/or steps, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.
As used herein, singular references (e.g., “a”, “an”, “first”, “second”, etc.) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements, or actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.
Further examples and combinations thereof include the following:
Example 1 includes an integrated circuit (IC) package substrate comprising a first solder resist layer, a second solder resist layer opposite the first solder resist layer, and a fiducial marker including tin in an opening in the first solder resist layer.
Example 2 includes the IC package substrate of example 1, further including a glass core between the first and second solder resist layers.
Example 3 includes the IC package substrate of example 1, further including a copper pad at a base of the opening, the copper pad including a surface finish, the surface finish corresponding to the tin.
Example 4 includes the IC package substrate of example 1, further including a metal base below the opening, the fiducial marker having an exposed surface defined by the tin within the opening, the tin different than the metal base, the tin extending from the metal base to the exposed surface.
Example 5 includes the IC package substrate of example 1, wherein an exposed surface of the fiducial marker has a convex surface.
Example 6 includes the IC package substrate of example 1, wherein the opening is one of a plurality of openings in the first solder resist layer, the IC package substrate further including a plurality of metal pads to electrically interconnect with a plurality of contacts on a semiconductor die, and the plurality of openings in the first solder resist layer, the plurality of openings aligned with the plurality of metal pads and filled with additional tin to electrically couple the plurality of metal pads with the plurality of contacts, the additional tin in direct contact with the plurality of metal pads.
Example 7 includes the IC package substrate of example 1, wherein the opening is a first opening, the IC package substrate further including a die-side capacitor pad in a second opening in the first solder resist layer.
Example 8 includes the IC package substrate of example 7, wherein the die-side capacitor pad includes a base including copper and a layer including tin, the layer on the base.
Example 9 includes the IC package substrate of example 8, wherein the layer is in contact with the base.
Example 10 includes an integrated circuit (IC) package comprising a semiconductor die, a package substrate supporting the semiconductor die, and an opening in a surface of the package substrate, a metal pad at a base of the opening, and a surface finish on the metal pad, the surface finish having a domed shape.
Example 11 includes the IC package of example 10, wherein the surface finish includes tin.
Example 12 includes the IC package of example 11, wherein the surface finish is associated with a fiducial marker, the surface finish extending from the metal pad to an exposed surface of the fiducial marker.
Example 13 includes the IC package of example 10, wherein the surface finish does not include a layer of nickel disposed therein.
Example 14 includes the IC package of example 10, wherein the package substrate includes a glass core.
Example 15 includes the IC package of example 10, further including a plurality of bumps to electrically couple the semiconductor die to a corresponding plurality of contact pads on the package substrate, the bumps defined by tin in direct contact with the contact pads.
Example 16 includes the IC package of example 10, wherein the surface finish is a first surface finish, the IC package further including at least one of a die-side capacitor pad or a land-side capacitor pad on the package substrate, the at least one of the die-side capacitor pad or the land-side capacitor pad defined by a metal base with a second surface finish including tin in direct contact with the metal base.
Example 17 includes a method comprising providing openings within a solder resist layer of a package substrate for an integrated circuit (IC) package, the openings to expose metal pads, a first one of the openings defining a fiducial marker, and depositing a surface finish onto ones of the metal pads in ones of the openings, the ones of the openings including the first opening, the surface finish including tin.
Example 18 includes the method of example 17, wherein the depositing of the surface finish is accomplished through electroless plating.
Example 19 includes the method of example 17, wherein the depositing of the surface finish is accomplished without a rock and shock operation.
Example 20 includes the method of example 17, further including constructing the package substrate with a glass core.
The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, apparatus, articles of manufacture, and methods have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, apparatus, articles of manufacture, and methods fairly falling within the scope of the claims of this patent.
