Patent Application
20070254492
The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
a schematically illustrates a cross-sectional view of a semiconductor device during a plasma enhanced chemical vapor deposition process for forming a silicon nitride layer having a high intrinsic compressive stress according to illustrative embodiments of the present invention;
b schematically illustrates a deposition system appropriate for establishing a silane-based deposition atmosphere with high-frequency power and low-frequency power in accordance with illustrative embodiments; and
a-2d schematically illustrate cross-sectional views of a semiconductor device including a transistor element during various manufacturing stages, at least in one of which a compressively stressed silicon nitride material is formed on the basis of a technique described with reference to
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present invention will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present invention with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
Generally, the present invention contemplates a technique for the formation of compressively stressed silicon nitride on the basis of a plasma enhanced chemical vapor deposition (PECVD) technique, in which process parameters may be controlled so as to obtain a high amount of intrinsic compressive stress while nevertheless a corresponding particle contamination and thus defect rate may be reduced compared to conventional approaches. As is generally known, during the deposition of silicon nitride material on the basis of chemical vapor deposition (CVD), process parameters, such as deposition pressure, temperature and the like, may be appropriately controlled in order to provide a desired high amount of compressive stress. In particular, the degree of ion bombardment during the deposition process may significantly affect the stress characteristics of the resulting silicon nitride film, since the ion bombardment during the deposition may affect the resulting silicon/nitrogen and silicon/hydrogen bondings, which may finally lead to a certain degree of stress in the silicon nitride material. Generally, by increasing the degree of ion bombardment during the deposition, the amount of intrinsic compressive stress for otherwise identical process parameters may be increased. In conventional techniques, the degree of ion bombardment, which is substantially determined by a resulting accelerating voltage between ionized particles and the substrate surface to be coated, is adjusted on the basis of the high-frequency power that is usually coupled into the precursor gases by inductive or capacitive coupling from a corresponding high frequency generator. Without intending to restrict the present invention to the following explanation, it is nevertheless believed that the high-frequency biased substrate surface may still maintain some electrical charge even after switching off the plasma, i.e., switching off the high-frequency power supply, which may lead to a further deposition of unwanted particles, thereby significantly enhancing the defect rate, in particular, when a high level of high-frequency power may have to be used to generate the required high degree of ion bombardment. Contrary to this conventional approach, in the present invention, an additional low-frequency power is supplied in order to significantly enhance the ion bombardment while substantially reducing the adverse effects of the high-frequency power on the substrate surface. In this respect, it should be appreciated that the terms “high-frequency power” and “low-frequency power” are to be understood with respect to the involved frequencies such that the frequency of the high-frequency power is significantly higher than the frequency of the low-frequency power, wherein typically the high-frequency power involves a frequency range from several MHz to several tens of MHz, for example approximately 10-20 MHz, for instance approximately 13-14 MHz, including a typical high-frequency value of approximately 13.56 MHz, while in this application the term low-frequency power may include frequencies from several MHz, typically several hundred KHz, down to a DC power. In one illustrative embodiment, the low-frequency range comprises 0 Hz to 500 KHz, for example approximately 100-200 KHz. Consequently, by using excitation power modulated by at least two significantly different frequencies, compressive silicon nitride layers may be formed having an intrinsic compressive stress of approximately 2 GPa and even higher while at the same time providing a defect rate that is comparable to conventional techniques with significantly reduced intrinsic stress. As a consequence, the technique as provided by the present invention is highly advantageous during the formation of any microstructures, in which highly compressive silicon nitride material is required and hence the present invention should not be restricted to any specific application of compressively stressed silicon nitride, unless such restrictions are explicitly set forth in the appended claims and the following detailed description.
In other illustrative embodiments, a highly compressive silicon nitride material having a low defect rate may be used in combination with advanced transistor elements in order to create a desired type of strain in a channel region of a transistor, as will be described later on in more detail.
With reference to the drawings, further illustrative embodiments of the present invention will now be described in more detail.
The substrate 101 including the surface 102 and possibly including any structure elements, such as circuit elements and the like, may be formed on the basis of well-established process techniques for the formation of microstructures, wherein the corresponding process steps may include photolithographic patterning, etch processes, implantation processes, deposition processes and the like. Thereafter, the device 100 may be exposed to a deposition atmosphere 120, which in one illustrative embodiment comprises silane (SiH4), in order to form the silicon nitride material 103. In other illustrative embodiments, the deposition atmosphere 120 may be established, in addition to silane, on the basis of ammonia (NH3) and nitrogen as further precursors or carrier gases, wherein, in one illustrative embodiment, further significant amounts of other carrier gases, such as argon, may not be required thereby reducing the process complexity for establishing and controlling the deposition atmosphere 120. In establishing the deposition atmosphere 120, the temperature of the substrate 101 and thus of the respective deposition surface 102 may also be adjusted to an appropriate range, wherein in some illustrative embodiments the respective temperature of the substrate 101 is maintained at 500° C. and less, for example 500° C. to 300° C., while in other illustrative embodiments the temperature is adjusted to approximately 400° C. Maintaining the temperature of the substrate 101 at a temperature range as specified above may reduce adverse effects of the temperature on previously formed microstructural features and materials, as will be described later on in more detail when it is referred to the formation of a transistor element. Moreover, the deposition atmosphere 120 may be established in a low pressure ambient, wherein the pressure may be controlled so as to be within a range of approximately 0.8-2.0 Torr, when a distance of ionized particles moving towards the surface 102 is in the range of approximately 200-400 mils (1 mil=0.0254 mm). In other cases, if significantly longer distances may be selected for an average path length of ionized particles, the corresponding pressure may be reduced in order to maintain scattering events at a moderately low level.
After establishing the deposition atmosphere 120 on the basis of silane, the actual deposition of silicon nitride material may be initiated by supplying high-frequency power (HF) and low-frequency power (LF) to the deposition atmosphere 120, thereby establishing the required plasma ambient and also generating an appropriate voltage between the atmosphere 120 and the substrate surface 102, which provides a high degree of directionality of the ionized particles moving to the surface 102. Consequently, a high degree of ion bombardment during the formation of the silicon nitride material 103 is generated, which in turn provides the desired high degree of intrinsic compressive stress. Since the low-frequency power may have a significantly increased “wavelength” compared to the high-frequency power, for example up to 2 orders of magnitude or more, a highly efficient creation of an acceleration voltage is achieved, while the high frequency biased excitation of the surface 102 may be reduced. As a consequence, during the ongoing deposition of the material 103, the high degree of ion bombardment ensures the generation of a high compressive stress, while after discontinuing the supply of high-frequency power and low-frequency power, an additional deposition of unwanted particles may be significantly reduced.
In one illustrative embodiment, the amount of high-frequency power supplied to the atmosphere 120 is less than the amount of low-frequency power during the entire deposition phase, thereby providing a high degree of ion bombardment while reducing adverse effects of the high-frequency modulated power. It should be appreciated that the absolute amount of high-frequency power and low-frequency power supplied to the deposition atmosphere 120 may depend on the configuration of a respective deposition reactor or chamber and corresponding values may be readily established on the basis of the above teaching and the one or more further illustrative embodiments described with reference to
After the discontinuation of the supply of high-frequency power and low-frequency power, further purge and pump processes may be performed in order to remove any unwanted byproducts created during the preceding deposition in the atmosphere 120, and thereafter the further processing may be continued on the basis of process and device requirements. Consequently, due to the effective control of the ion bombardment within the deposition atmosphere 120 on the basis of the low-frequency power, a high compressive stress in the material 103 may be obtained, wherein, in addition to a low defect rate, a reduced process time compared to conventional approaches may also be achieved, in which the ion bombardment is substantially adjusted on the basis of a high amount of high-frequency power.
With reference to
b schematically illustrates a CVD system 160 that is appropriate for PECVD processes for forming compressively stressed silicon nitride material, such as the material 103 of
The remote reactor 150 may be connected to a source of precursor gases 151 via a supply line 152, which may include appropriate valve assemblies 153 for controlling a flow rate of the precursor gases. For instance, as previously explained, in one illustrative embodiment, precursor gases may include silane, ammonia and nitrogen. Moreover, the remote reactor 150 may be coupled to an appropriate excitation unit 155, wherein the coupling is indicated by arrows 156 which may represent an appropriate coupling mechanism to be used depending on the type of excitation unit used. An appropriate excitation unit, such as a high-frequency generator, may be provided in order to create a plasma within the remote reactor 150 and also to provide a desired accelerating voltage between the first plate 162 and the surface of the substrate 101. In other cases, the high-frequency power may be coupled into the chamber 170, while the reactor 150 may act as a gas supply. For example, the coupling 156 may be accomplished by inductive coupling or capacitive coupling for supplying the high-frequency power for the excitation of the precursor gases. Similarly, the low-frequency power may be coupled into the process chamber 170 by inductive coupling or capacitive coupling or by an ohmic contact to the first and second plates 162, 163, when a DC or very low-frequency power is used. Furthermore, the process chamber 170 may be connected to a pump source 169 that is adapted to controllably establish a predefined pressure within the process chamber 170 in order to provide the required environmental conditions for a respective deposition atmosphere, such as the atmosphere 120 as described with reference to
During operation of the system 160, the substrate 101 may be loaded onto the plate 163 by means of any appropriate loading system, such as a robotic arm and the like, wherein the lift pins 166 may be appropriately positioned to receive the substrate 101 and to attach the substrate to the plate 163. Moreover, after receiving the substrate 101, the plate 163 may be appropriately positioned by the drive assembly 164, as indicated by the arrow 165, in order to obtain a desired distance 165D with respect to the plate 162. In some illustrative embodiments, the distance 165D may be maintained constant throughout the subsequent processing of the substrate 101, i.e., during a setup phase, an actual deposition phase and a subsequent purge and pump phase, thereby reducing the control complexity and also reducing the cycle time of the deposition process. For example, the system 160 may represent a single chamber CVD system configured for the processing of 200 mm substrates, as is for instance available from Applied Materials Inc under the name “Producer system.” In this case, the distance 165D may be adjusted within a range of 200-400 mils, depending on the selected chamber pressure and the amount of high-frequency power and low-frequency power supplied to the respective deposition atmosphere 120, since these parameters may significantly affect the kinematic behavior of the ionized particles when moving from the first plate 162 to the substrate 101.
For the above-specified configuration of the system 160, the deposition atmosphere 120 may be established on the basis of silane, ammonia and nitrogen with flow rates of approximately 10-80 sccm (standard cubic centimeters per minute), 0-70 sccm and 500-2000 sccm, respectively. The pressure within the deposition atmosphere 120 may be maintained within a range of approximately 0.8-2.0 Torr, while the distance 165D may be maintained within the above-specified range of approximately 200-400 mils. With a substrate temperature of less than 500° C., for instance of approximately 400° C., the actual deposition of silicon nitride material may be initiated by supplying high-frequency power of approximately 20-100 Watts and a low-frequency power of approximately 60-100 Watts. For the above-specified tool configuration, the high-frequency power may involve a frequency of 13-14 MHz while the low-frequency power may be provided with a frequency range of several hundred KHz. While adjusting one of the process parameters, such as flow rates, pressure, distance, temperature, high-frequency power and low-frequency power, the degree of compressive stress in the silicon nitride material, such as the layer 103, may be appropriately adjusted. For instance, for a temperature of approximately 400° C. and a pressure of approximately 1.4 Torr, a distance of approximately 290 mils, and flow rates for silane, ammonia and nitrogen, respectively, of approximately 50 sccm, 40 sccm and 1200 sccm, a compressive stress of approximately 2 GPa may be obtained. On the basis of the above-specified parameter value ranges, the corresponding compressive stress may be varied from approximately 1.5 GPa to approximately 2.5 GPa, wherein, for instance, in some illustrative embodiments, the high-frequency power and/or the low-frequency power may be varied while the other process parameters may be substantially maintained constant. Consequently, a highly efficient control mechanism with reduced complexity may be accomplished, while nevertheless providing increased levels of compressive stress.
The actual deposition phase may be preceded by a respective setup step in which the required gas components may be supplied to the process chamber 170 or the remote reactor, depending on the configuration, on the basis of a desired pressure, while also the respective distance 165D may be adjusted and the temperature of the substrate 101 may be reached. For example, a setup time for establishing the deposition atmosphere 120 may range from approximately 8-12 seconds. Thereafter, the actual deposition phase may be initiated by supplying the low-frequency power and the high-frequency power, wherein, for the above presented parameter ranges, a deposition time of approximately 21-28 seconds may result in a layer thickness of approximately 50 nm. After the deposition, the process chamber 170 may be purged, for instance on the basis of nitrogen, which may be accomplished by discontinuing the supply of the precursor gases silane and ammonia. In one illustrative embodiment, the flow rate of nitrogen as specified above may be maintained during this purge step. For example, under these conditions, a purge time of approximately 5 seconds may be appropriate, wherein the distance 165D as well as the temperature of the substrate 101 may be maintained at the same values as previously used for the actual deposition. Thereafter, a pump step may be performed, for instance for approximately 10 seconds, in order to efficiently remove gaseous components from the chamber 170.
It should be appreciated that although a specific design of the deposition system 160 is described with reference to
With reference to
a schematically illustrates a semiconductor device 200 which may comprise a substrate 201. The substrate 201 may represent any appropriate substrate having formed thereon a semiconductor layer 204 that is suitable for the formation of transistor elements, such as a P-channel field effect transistor 210. For example, the substrate 201 and the semiconductor layer 204, which may represent a silicon-based semiconductor layer, may in combination define a “bulk” transistor configuration wherein the semiconductor layer 204 may represent an upper portion of the substrate 201, while in other embodiments the substrate 201 in combination with the layer 204 may constitute a silicon-on-insulator (SOI) configuration, wherein a buried insulating layer (not shown) may be provided on the substrate 201 so as to form an interface with the semiconductor layer 204. In this manufacturing stage, the P-channel transistor 210 may comprise a gate electrode 206 formed above the semiconductor layer 204 and separated therefrom by a gate insulation layer 207, which may be comprised of silicon dioxide, silicon nitride, combinations thereof and the like. For instance, in highly advanced devices, a thickness of the gate insulation layer 207 may range from approximately several nanometers to 1.5 nanometers, while a length of the gate electrode 206, that is, the horizontal extension thereof in
The semiconductor device 200 as shown in
b schematically illustrates the semiconductor device 200 in a further advanced manufacturing stage. The device 200 comprises a spacer element 203A, which in one illustrative embodiment may be comprised of silicon nitride material having a high intrinsic compressive stress, while in still other illustrative embodiments when high compressive stress of the spacer elements 203A is not desired, the spacer layer 203 as shown in
The device 200 as shown in
c schematically illustrates the semiconductor device 200 in a further advanced manufacturing stage in which the device is exposed to a deposition ambient for depositing a compressively stressed silicon nitride material 213, wherein the deposition atmosphere may have substantially the same characteristics as previously described with respect to the atmosphere 220 and 120. Hence, based on appropriately selected process parameters and using at least two different modulation frequencies for power supplied to the deposition atmosphere 220, a high degree of compressive stress may be obtained. For instance, as previously described with reference to
d schematically illustrates the semiconductor device 200 in a further advanced manufacturing stage in which an interlayer dielectric material 214, for instance comprised of silicon dioxide, may be formed above the layer 213. Furthermore, a respective opening 214A may be formed in the material 214 on the basis of a respective anisotropic etch process 215, during which, in some illustrative embodiments, the silicon nitride layer 213 may act as an etch stop layer. Thereafter, a further etch process may be carried out to form a respective opening in the layer 213 in order to contact one or more of the metal silicide regions 212. It should be appreciated that, in highly advanced applications, other strain-inducing sources in addition to the silicon nitride layer 213 and possibly the spacers 203A may be provided, such as embedded strained semiconductor material in the drain and source regions 211. Furthermore, it may be appreciated that the silicon nitride layer 213 may be locally formed above the transistor 210 in order to enhance the hole mobility in the respective channel region 208, whereas the layer 213 may locally be modified or removed, for instance above N-channel transistors, in order to reduce or eliminate any adverse influence on these transistors. It should further be appreciated that the layer 213 may be formed in combination with one or more other thin dielectric etch stop layers, which may be provided below and/or above the silicon nitride layer 213, for instance in the form of respective silicon dioxide liners, in order to enhance the overall process for forming stressed layers having a different type of intrinsic stress and/or for enhancing the patterning process for forming respective contact openings in the material 214 and the layer 213.
As a result, the present invention provides a technique that enables the formation of a highly compressively stressed silicon nitride material on the basis of a PECVD process, in which high-frequency power and low-frequency power are supplied to the respective deposition atmosphere in order to significantly enhance the ion bombardment during deposition, while maintaining particle contamination at a low level. Thereby, the required high-frequency power may be reduced significantly compared to conventional approaches in which the degree of ion bombardment is substantially controlled on the basis of the amount of high-frequency power. Hence, in some illustrative embodiments, the low-frequency power may be provided with a higher amount compared to the high-frequency power, thereby effectively enhancing the ion bombardment while significantly reducing any adverse effects of high frequency biasing of the substrate surface. Moreover, the concept of the present invention may be readily implemented into standard CVD tools without requiring significant modifications, thereby providing the potential for using the respective deposition tool for single frequency processes, when standard recipes are required, while also performing double frequency processes for enhanced levels of compressive stress. Since the reduced effect of high-frequency power may also enable a reduced time interval for setting up the respective deposition atmosphere and for purging and pumping the process chamber after the deposition, even a reduced cycle time may be achieved while additionally the control complexity may also be reduced as, for instance, a fixed spacing may be used during the entire process sequence. The new technique may be efficiently used in combination with manufacturing of advanced P-channel transistors wherein a corresponding silicon nitride layer, such as a contact etch stop layer, may be formed above the respective transistor element in order to significantly increase the compressive strain in the respective channel region. Furthermore, in addition or alternatively, one or more spacer elements may be formed on the basis of a highly compressively stressed silicon nitride material so as to even further enhance the strain-inducing mechanism. By way of example, for otherwise identical device parameters, a P-channel transistor, such as the transistor 210 as shown in
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2006 019 881.6 | Apr 2006 | DE | national |
