Thermal enhanced package

Abstract

A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material. The method also includes removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface. The method further includes forming a plurality of conductive traces on the routing surface. Each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified cross-sectional view of an integrated circuit package according to an embodiment of the present invention;

FIG. 2 is a simplified cross-sectional view of an integrated circuit package according to another embodiment of the present invention;

FIG. 3 is a simplified flowchart illustrating a method of manufacturing an integrated circuit package according to an embodiment of the present invention;

FIGS. 4A-4E are simplified cross-sectional views of a package during various stages of manufacturing according to an embodiment of the present invention;

FIGS. 5A-5E are simplified cross-sectional views of a package during various stages of manufacturing according to another embodiment of the present invention;

FIG. 6 is a simplified perspective view of a package with multi-layer routing according to an embodiment of the present invention;

FIG. 7 is a simplified perspective view of a multi-die package according to an embodiment of the present invention; and

FIGS. 8A-8H show various devices in which the present invention may be embodied.

Claims

1. A method of manufacturing an integrated circuit package, the method comprising: attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate;forming a plurality of die connectors on a second surface of the semiconductor die;encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material;removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface; andforming a plurality of conductive traces on the routing surface, wherein each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector.

2. The method of claim 1 further comprising forming a solder mask layer coupled to the routing surface.

3. The method of claim 1 wherein the thermally and/or electrically conductive substrate comprises a metal substrate.

4. The method of claim 3 wherein the metal substrate comprises a copper plate.

5. The method of claim 1 wherein the encapsulant material comprises a dielectric material.

6. The method of claim 5 wherein the dielectric material comprises an epoxy resin.

7. The method of claim 1 wherein removing a portion of the encapsulant material comprises grinding an exposed portion of the encapsulant material.

8. The method of claim 1 wherein the package connector comprises a solder ball.

9. The method of claim 1 further comprising: forming an insulating layer over the routing surface; andforming a plurality of second-level conductive traces on the insulating layer, thereby forming an integrated circuit package with multi-layer routing.

10. A thermally enhanced integrated circuit package comprising: a thermally and/or electrically conductive substrate;a die attach material formed on the thermally and/or electrically conductive substrate;a semiconductor die having a first surface, a plurality of side surfaces, and a second surface opposing the first surface, wherein the first surface is adjacent to the die attach material;a plurality of die connectors in electrical communication with a plurality of die pads provided on the second surface of the semiconductor die;an encapsulant layer characterized by a first encapsulant surface positioned adjacent to the thermally and/or electrically conductive substrate and a second encapsulant surface opposing the first surface, wherein the encapsulant layer surrounds the plurality of side surfaces of the semiconductor die and is positioned over a first portion of the second surface of the semiconductor die; anda routing layer formed on the second encapsulant surface of the encapsulant layer.

11. The thermally enhanced integrated circuit package of claim 10 further comprising: a first via passing from the routing layer to the thermally and/or electrically conductive substrate, wherein the first via is adapted to be in electrical communication with a first voltage;a second via passing from the routing layer to the thermally and/or electrically conductive substrate, wherein the second via is adapted to be in electrical communication with a second voltage; anda plating layer adapted to receive solder and coupled to the routing layer.

12. The thermally enhanced integrated circuit package of claim 11 further comprising a capacitor coupled to the thermally and/or electrically conductive substrate, wherein a first terminal of the capacitor is in electrical communication with the first via and a second terminal of the capacitor is in electrical communication with the second via.

13. The thermally enhanced integrated circuit package of claim 10 wherein the thermally and/or electrically conductive substrate comprises a copper substrate.

14. The thermally enhanced integrated circuit package of claim 10 wherein the encapsulant material comprises a dielectric material.

15. The thermally enhanced integrated circuit package of claim 14 wherein the dielectric material comprises an epoxy resin.

16. The thermally enhanced integrated circuit package of claim 10 wherein the die connectors are selected from the group consisting of copper bumps and gold bumps.

17. The thermally enhanced integrated circuit package of claim 10 wherein the encapsulant layer spans from the second surface of the semiconductor die to the routing layer.

18. A integrated circuit package comprising: a semiconductor die comprising a first surface attached to a thermally and/or electrically conductive substrate and a second surface opposing the first surface;a plurality of die connectors formed on the second surface of the semiconductor die;an encapsulant material encapsulating the semiconductor die and a portion of the plurality of die connectors, wherein a routing surface of the encapsulating material comprises exposed portions of the plurality of die connectors; anda plurality of conductive traces formed on the routing surface, wherein each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector.

19. The integrated circuit package of claim 18 further comprising a solder mask layer coupled to the routing surface.

20. The integrated circuit package of claim 18 wherein the thermally and/or electrically conductive substrate comprises a metal substrate.

21. The integrated circuit package of claim 20 wherein the metal substrate comprises a copper plate.

22. The integrated circuit package of claim 18 wherein the encapsulant material comprises a dielectric material.

23. The integrated circuit package of claim 22 wherein the dielectric material comprises an epoxy resin.

24. The integrated circuit package of claim 18 wherein the routing surface is formed using a grinding process to remove a portion of the encapsulant material.

25. The integrated circuit package of claim 18 wherein the package connector comprises a solder ball.

26. The integrated circuit package of claim 18 further comprising: an insulating layer formed over the routing surface; anda plurality of second-level conductive traces formed on the insulating layer to form an integrated circuit package with multi-layer routing.

27. A method of fabricating a thermally enhanced integrated circuit package, the method comprising: forming a die attach material layer on a surface of a thermally and/or electrically conductive substrate;mounting a first surface of a semiconductor die to the die attach material layer, wherein the semiconductor die is defined by a plurality of side surfaces and a second surface opposing the first surface;forming a plurality of die connectors in electrical communication with a plurality of die pads provided on the second surface of the semiconductor die;forming an encapsulant layer characterized by a first encapsulant surface positioned adjacent to the thermally and/or electrically conductive substrate and a second encapsulant surface opposing the first encapsulant surface, wherein the encapsulant layer surrounds the plurality of side surfaces of the semiconductor die and is positioned over a first portion of the second surface of the semiconductor die; andforming a routing layer on the second encapsulant surface.

28. The method of claim 27 further comprising: forming a first via passing from the routing layer to the thermally and/or electrically conductive substrate, wherein the first via is adapted to be in electrical communication with a first voltage;forming a second via passing from the routing layer to the thermally and/or electrically conductive substrate, wherein the second via is adapted to be in electrical communication with a second voltage; andforming a plating layer coupled to the routing layer and adapted to receive solder.

29. The method of claim 28 further comprising mounting a capacitor coupled to the thermally and/or electrically conductive substrate, wherein a first terminal of the capacitor is in electrical communication with the first via and a second terminal of the capacitor is in electrical communication with the second via.

30. The method of claim 27 wherein the thermally and/or electrically conductive substrate comprises a copper substrate.

31. The method of claim 27 wherein the encapsulant material comprises a dielectric material.

32. The method of claim 31 wherein the dielectric material comprises an epoxy resin.

33. The method of claim 27 wherein the die connectors are selected from the group consisting of copper bumps and gold bumps.

34. The method of claim 27 wherein the encapsulant layer spans from the package surface of the semiconductor die to the routing layer.